CN107432086B - Method for manufacturing electronic device and electronic device - Google Patents

Method for manufacturing electronic device and electronic device Download PDF

Info

Publication number
CN107432086B
CN107432086B CN201680016337.9A CN201680016337A CN107432086B CN 107432086 B CN107432086 B CN 107432086B CN 201680016337 A CN201680016337 A CN 201680016337A CN 107432086 B CN107432086 B CN 107432086B
Authority
CN
China
Prior art keywords
circuit pattern
electronic component
substrate
conductive
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201680016337.9A
Other languages
Chinese (zh)
Other versions
CN107432086A (en
Inventor
半古明彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stanley Electric Co Ltd
Original Assignee
Stanley Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stanley Electric Co Ltd filed Critical Stanley Electric Co Ltd
Publication of CN107432086A publication Critical patent/CN107432086A/en
Application granted granted Critical
Publication of CN107432086B publication Critical patent/CN107432086B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1283—After-treatment of the printed patterns, e.g. sintering or curing methods
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F7/00—Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting wherein at least one part is obtained by sintering or compression
    • B22F7/06—Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting wherein at least one part is obtained by sintering or compression of composite workpieces or articles from parts, e.g. to form tipped tools
    • B22F7/08—Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting wherein at least one part is obtained by sintering or compression of composite workpieces or articles from parts, e.g. to form tipped tools with one or more parts not made from powder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H01B1/20—Conductive material dispersed in non-conductive organic material
    • H01B1/22—Conductive material dispersed in non-conductive organic material the conductive material comprising metals or alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/097—Inks comprising nanoparticles and specially adapted for being sintered at low temperature
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/102—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by bonding of conductive powder, i.e. metallic powder
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F2999/00—Aspects linked to processes or compositions used in powder metallurgy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0108—Transparent
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1131—Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Dispersion Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Composite Materials (AREA)
  • Nanotechnology (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

Provided is a method for manufacturing an electronic device, wherein an electronic component can be connected with a high-density circuit pattern with high accuracy. A solution in which conductive nanoparticles having a particle diameter of less than 1 [ mu ] m and an insulating material are dispersed or a solution in which conductive nanoparticles coated with an insulating material layer are dispersed is applied in a desired shape on the surface of a light-transmitting substrate to form a film of conductive nanoparticles coated with an insulating material. An electronic component is mounted on the film. The film is irradiated with light in a predetermined pattern from the back side of the light-transmitting substrate, and the conductive nanoparticles are sintered by the light. Thereby, the 1 st circuit pattern connected to the electrode of the electronic component is formed, and the 1 st circuit pattern is fastened to the electrode of the electronic component.

Description

Method for manufacturing electronic device and electronic device
Technical Field
The present invention relates to an electronic device having a circuit pattern on a substrate.
Background
Conventionally, as a mounting method for mounting an electronic component on a substrate, the following methods are known: a bump is formed on a circuit pattern on a substrate with an Au wire or the like, and an electronic component is mounted thereon, electrically connected by irradiation of heat and ultrasonic waves, and fastened to the circuit pattern. Further, the following methods are also known: solder paste or the like is applied to the circuit pattern on the substrate, and an electronic component is mounted thereon, and heated to melt the solder, whereby electrical connection is performed and the electronic component is fastened to the circuit pattern.
As a method for forming a circuit pattern, a method of etching a copper foil using a mask is widely used, but the manufacturing process of this method is complicated and time-consuming, and the manufacturing apparatus is expensive. In recent years, in order to simplify the manufacturing process and to reduce the manufacturing apparatus cost, the technical field of so-called printed electronic products in which a circuit pattern is formed by printing has been widely studied.
For example, patent document 1 discloses the following technique: a non-conductive film containing copper nanoparticles is stacked by an ink jet printer or the like, and the formed film is irradiated with light from above, whereby copper particles are fused to form a conductive circuit.
Prior art documents
Patent document
Patent document 1: japanese patent laid-open No. 2014-116315
Disclosure of Invention
Problems to be solved by the invention
In a method of mounting an electronic component on a circuit pattern using a bonding material such as solder paste, positional displacement occurs at the time of forming the circuit pattern, at the time of supplying the bonding material, and at the time of mounting the electronic component. The circuit pattern is designed based on the size and shape (pattern gap) in consideration of these positional deviations, and therefore, high-density mounting of electronic components is prevented.
Further, when the solder paste is used as the bonding material, positional displacement occurs due to a force acting to pull the electronic component due to surface tension when the solder paste is melted, and therefore, mounting accuracy of the electronic component varies.
On the other hand, in the method using the convex balls, although positional deviation such as that in the case of melting the solder paste does not occur, variation in mounting accuracy due to the accuracy of the pattern size in forming the wiring pattern occurs. Further, since there is a limitation in the pattern gap that can be formed, there is also a limitation in high-density mounting of electronic components.
The invention aims to provide a method for manufacturing an electronic device capable of accurately connecting an electronic component to a high-density circuit pattern.
Means for solving the problems
In order to achieve the above object, the present invention provides a method for manufacturing an electronic device, comprising a step 1 of applying a solution in which conductive nano-particles having a particle diameter of less than 1 μm and an insulating material are dispersed or a solution in which the conductive nano-particles coated with an insulating material layer are dispersed onto a surface of a light-transmitting substrate in a desired shape to form a film of the conductive nano-particles coated with the insulating material. In step 2, an electronic component is mounted on the film. In the 3 rd step, the film is irradiated with light in a predetermined pattern from the back side of the light-transmitting substrate, the conductive nano-particles are sintered by the light, and a layer of the predetermined pattern, which is formed by sintering the conductive nano-particles, is formed, whereby the 1 st circuit pattern connected to the electrode of the electronic component is formed, and the 1 st circuit pattern and the electrode of the electronic component are fastened.
Effects of the invention
According to the present invention, the circuit pattern is formed at a high density by light irradiation and connected to the electronic component, so that mounting variation of the electronic component with respect to the circuit pattern can be reduced.
Drawings
Fig. 1 (a) to (g) are explanatory views showing a method of manufacturing an electronic component according to embodiment 1, and (h) is a bottom view of the manufactured electronic component.
Fig. 2 is an electronic device that can be manufactured by embodiment 1, (a) is a top view, (B) is a sectional view a-a of (a), and (c) is a sectional view B-B of (a).
Fig. 3 is a plan view of the electronic device in the case where the film 41 is removed in embodiment 1.
Fig. 4 is a plan view of the electronic device manufactured according to embodiment 4, where (a) is a state where the upper substrate 10-2 is removed, (B) is a state where the lower substrate 10-2 is not removed and is a sectional view a-a of (a), and (c) is a state where the lower substrate 10-2 is not removed and is a sectional view B-B of (a).
Fig. 5 is an enlarged view of the electronic device manufactured by embodiment 4.
Fig. 6 (a) to (c) are explanatory views showing the manufacturing method of embodiment 5.
FIGS. 7 (a-1) to (c-2) are explanatory views showing the production method of embodiment 6.
Fig. 8 is an enlarged view of an electronic device according to a modification of fig. 5 of embodiment 7.
Detailed Description
A method for manufacturing an electronic device according to an embodiment of the present invention will be described below.
< embodiment 1 >
A method for manufacturing an electronic device according to embodiment 1 will be described with reference to fig. 1 (a) to (h).
In the present embodiment, a light-transmitting substrate is used as the substrate 10, and the 1 st circuit pattern 40 is formed by irradiating light from the back surface side of the substrate.
First, as shown in fig. 1 (a), a substrate 10 on which a 2 nd circuit pattern 50 having a thick film is formed in advance is prepared.
Next, as shown in fig. 1 (b), a solution in which conductive nano-particles having a particle diameter of 1 μm or less (hereinafter, referred to as conductive nanoparticles) and an insulating material are dispersed in a solvent or a solution in which conductive nanoparticles coated with a layer of an insulating material are dispersed in a solvent is applied to a region 20 on the surface of the substrate 10 in a desired shape. As shown in fig. 1 (c), the surface of the applied solution is smoothed on the substrate 10, and a coating film (film 41) is formed. The end of the film 41 overlaps the end of the 2 nd circuit pattern 50. The film 41 is dried by heating as necessary. The conductive nanoparticles are dispersed in the film 41, and the periphery of the conductive nanoparticles is covered with an insulating material. Thus, the membrane 41 is non-conductive.
Next, as shown in fig. 1 (d), the electronic component 30 is mounted while being aligned with a predetermined position on the film 41, and as shown in fig. 1 (e), the electrode 31 of the electronic component 30 is brought into close contact with the film 41.
Next, as shown in fig. 1 (f), the film 41 is irradiated with light in a desired pattern from the back surface side of the substrate 10, and the conductive nanoparticles are sintered by the light, thereby forming a conductive nanoparticle layer (1 st circuit pattern 40) in the desired pattern. The irradiation pattern of light includes a region of the film 41 where the electrode 31 of the electronic component 30 abuts. Since the position of the electrode 31 of the mounted electronic component 30 is confirmed and the irradiation pattern is determined based on the electrode position, the positional deviation between the circuit pattern 40 and the electronic component 30 can be suppressed. Since the 1 st circuit pattern 40 continuous with the 2 nd circuit pattern 50 is formed, the region overlapping with the 2 nd circuit pattern 50 is also irradiated with light. Upon irradiation with light, the conductive nanoparticles melt at a temperature lower than the melting point of the main body of the material constituting the particles. The insulating material layer around the conductive nanoparticles is evaporated or softened by light irradiation. Thus, the fused conductive nanoparticles fuse directly with adjacent particles, or break through the softened insulating material layer and fuse with adjacent particles. This allows the conductive nanoparticles to be sintered to each other, and the region irradiated with light becomes the 1 st circuit pattern 40 having electrical conductivity. Thereby, as shown in fig. 1 (g), a pair of 1 st circuit patterns 40 is formed. In addition, the conductive nanoparticles after light irradiation are bonded to each other, but the particle shape is also retained to some extent.
The conductive nanoparticles are fused at the time of sintering, and thus are also bonded to the electrodes 31 of the electronic component 30, and the 1 st circuit pattern 40 and the electrodes 31 can be fastened. That is, the formation of the 1 st circuit pattern 40 and the bonding of the 1 st circuit pattern 40 to the electrode 31 may be simultaneously performed by light irradiation. Further, the bonding of the 1 st circuit pattern 40 and the electrode 31 can be performed using only the circuit pattern forming material and the electrode 31 without using an additional bonding material. The electrode 31 is directly bonded to the layer sintered from the conductive nanoparticles.
The wavelength of the light to be irradiated is a wavelength absorbed by the conductive nanoparticles contained in the film 41, and a wavelength that is not easily absorbed by the substrate 10 is selected and used. The light to be irradiated may be any of ultraviolet light, visible light, and infrared light. For example, when Ag, Cu, Au, Pd, or the like is used as the conductive nanoparticles, visible light of 400 to 600nm can be used. The predetermined pattern of the irradiation light can be formed by irradiating light through a mask having an opening in the shape of the predetermined pattern. Further, by using a light beam having a smaller irradiation diameter than the predetermined pattern and scanning the light beam in the predetermined pattern on the film 41, it is also possible to irradiate only the predetermined pattern with light.
The areas of the film 41 not irradiated with light are not sintered, and thus remain non-conductive. The nonconductive film 41 may be removed in a subsequent process. For example, the film 41 may be removed using an organic solvent or the like.
As a result, as shown in fig. 1 (h) when the substrate 10 is viewed from the back, the 1 st circuit pattern 40 connecting the electrodes 31 of the electronic component 30 and the 2 nd circuit pattern 50 can be formed in a state where the electronic component 30 is mounted.
As a method for forming the 2 nd circuit pattern 50 on the substrate 10, a conventional method can be used. For example, a method of forming a metal thin film on the substrate 10 and then forming a pattern having a desired shape by etching may be used. Alternatively, after a solution in which conductive particles are dispersed is printed on the substrate 10 to form a coating film in the shape of the 2 nd circuit pattern 50, the conductive particles may be sintered by applying heat or heat and pressure to form the 2 nd circuit pattern 50.
The structure of the electronic circuit device that can be manufactured by the above-described manufacturing method will be described with reference to (a), (b), and (c) of fig. 2.
The electronic circuit device of fig. 2 includes a substrate 10 having a circuit pattern and an electronic component 30. An area 20 for mounting an electronic component 30 is provided on the substrate 10, and a 1 st circuit pattern 40 electrically connected to the electronic component 30 is arranged in the area 20. Further, a 2 nd circuit pattern 50 is disposed on the substrate 10, and the 2 nd circuit pattern 50 is connected to the 1 st circuit pattern 40 at the peripheral edge portion of the region 20. The 2 nd circuit pattern 50 supplies a current to the 1 st circuit pattern 40 from a power supply 60 disposed outside the region 20.
A part or the whole of the 1 st circuit pattern 40 is composed of a layer containing conductive nanoparticles having a particle diameter of less than 1 μm. Since the 1 st circuit pattern 40 can be formed by sintering only a portion of the irradiated light, the 1 st circuit pattern 40 having a fine line width smaller than the 2 nd circuit pattern 50 can be formed in a desired shape and at a high density according to the size and arrangement of the electrodes of the electronic component 30. The region of the film 41 not irradiated with light remains non-conductive because it is not sintered, and remains continuous with the 1 st circuit pattern 40. The non-sintered region of the non-conductive film 41 may be left or removed in a subsequent step.
Specifically, as shown in fig. 2 (a) and (b), the 2 nd circuit pattern 50 is disposed on both ribs of the region 20 for mounting the electronic component 30. At least one pair of the 1 st circuit patterns 40 is arranged in the region 20, and each of the 1 st circuit patterns is connected to the 2 nd circuit patterns 50 on both ribs of the region 20. A non-conductive layer 41 is disposed between the pair of 1 st circuit patterns 40. The electrodes 31 of the electronic component 30 are directly fastened to the pair of 1 st circuit patterns 40.
As shown in (b) of fig. 2, the thickness of the 2 nd circuit pattern 50 is greater than that of the 1 st circuit pattern 40. In the present embodiment, the 1 st circuit pattern 40 forms only the inside of the region 20 on which the electronic component 30 is mounted, which requires fine wiring, and the 2 nd circuit pattern 50, which is thick, forms the outside of the region 20, thereby enabling a large current to be supplied to the electronic component 30.
In fig. 2, the power supply 60 is mounted on the substrate 10, but the power supply 60 is not necessarily disposed on the substrate 10. For example, a connector may be disposed on the substrate 10 instead of the power supply 60. In this case, a power supply not mounted on the board 10 can be connected to the connector by a cable or the like. The connector is connected with the 2 nd circuit pattern. Further, a power generation device such as a solar cell may be used as the power source 60.
The substrate 10 may be formed in a curved shape as shown in fig. 2 (b) and (c). In this case, the 1 st circuit pattern 40 and the 2 nd circuit pattern 50 are arranged along the surface of the curved substrate 10. In the present embodiment, since the 1 st circuit pattern 40 and the 2 nd circuit pattern 50 can be formed by applying a film containing conductive particles and irradiating the film with light to sinter the film, the circuit pattern on the substrate 10 can be easily formed without disconnection or disconnection by bending the substrate 10 before the sintering step.
As the material of the substrate 10, any material as described below can be used: the first and second circuit patterns 40 and 50 can be supported, at least the surfaces of which have insulating properties, have light-transmitting properties that enable light irradiation of a film containing conductive particles during formation of the first circuit pattern 40, and can withstand light irradiation during formation of the first circuit pattern 40. For example, a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, a glass epoxy substrate, a phenol laminate substrate, a flexible printed substrate, a ceramic substrate, a glass substrate, a metal substrate whose surface is covered with an insulating layer, or the like can be used. That is, the substrate transmits at least a part of the irradiated light. In addition, the substrate 10 of the present embodiment may have a film (film) structure.
As the material of the conductive nanoparticles constituting the 1 st circuit pattern 40, 1 or more kinds of conductive metals and conductive metal acid compounds such as Ag, Cu, Au, Pd, ITO, Pt, and Fe can be used. In the case of forming the 2 nd circuit pattern 50 by sintering the conductive particles, 1 or more kinds of the conductive metal and the conductive metal acid compound described above can be used as the material of the conductive particles, similarly to the 1 st circuit pattern 40.
As the insulating material containing the conductive nanoparticles and coating the conductive nanoparticles in the non-conductive film 41 continuous with at least the 1 st circuit pattern 40, resins such as styrene resin, epoxy resin, silicone resin, and acryl resin, and SiO can be used2、 Al2O3、TiO2And 1 or more of inorganic materials and organic and inorganic mixed materials. The thickness of the insulating material layer covering the conductive nanoparticles in the film 41 is preferably about 1nm to 10000 nm. This is because, if the insulating material layer is too thin, the voltage resistance of the non-conductive film 41 is lowered. In addition, if the insulating material layer is too thick, the electric conductivity of the 1 st circuit pattern 40 sintered by light irradiation decreases, and the thermal resistance value increases.
The 1 st circuit pattern 40 contains conductive particles having a particle diameter of 0.01 to 1 μm. The wiring width of the 1 st circuit pattern 40 (the portion to be baked) may be, for example, 1 μm or more. The thickness of the 1 st circuit pattern 40 may be formed to be about 1nm to 10 μm. Further, the resistance value of the 1 st circuit pattern 40 is preferably 10-4Ω/cm2Particularly preferably 10 or less-6Ω/cm2Low resistance of orders of magnitude or less.
As the electronic component 30, any electronic component can be used, and as an example, a light-emitting element (LED, LD), a light-receiving element, an integrated circuit, or a display element (a liquid crystal display, a plasma display, an EL display, or the like) can be used. In fig. 1, only 1 electronic component 30 is mounted on the substrate 10, but it is needless to say that 2 or more regions 20 may be provided and 2 or more electronic components 30 may be mounted. In this case, the 2 nd circuit pattern 50 is formed to connect a plurality of electronic components 30 by a desired circuit pattern such as series or parallel connection.
As described above, in the present embodiment, the fine 1 st circuit pattern 40 having a desired pattern connected to the electrode 31 of the electronic component 30 can be directly formed by mounting the electronic component 30 on the film 41 on the transparent substrate 10 and then irradiating light from the back surface side of the transparent substrate 10. Therefore, since light irradiation can be performed with reference to the position of the mounted electronic component 30, an error in the position of the electronic component 30 and the 1 st circuit pattern 40 can be prevented, and connection failure due to positional deviation can be reduced. Further, since the electronic component 30 on the 1 st circuit pattern 40 can be bonded simultaneously with the formation of the 1 st circuit pattern 40 at the time of light irradiation, a separate bonding material is not required, and thus, the problem of positional deviation or amount deviation at the time of supplying the bonding material, which has been the conventional problem, does not occur.
Further, since the fine 1 st circuit pattern can be formed at high density by irradiation with light, the electronic component 30 can be mounted at high density.
Further, since it is not necessary to design a circuit pattern in which a mounting deviation of the electronic component 30 and a bonding material supply deviation (position/amount) are predicted, the 1 st circuit pattern 40 can be designed more finely, and the electronic component 30 can be mounted with higher density.
The 1 st circuit pattern and the 2 nd circuit pattern 50 of a thick film may be connected to each other. Therefore, a large current can be supplied from the 2 nd circuit pattern 50 of a thick film of low resistance to the electronic component 30 through the 1 st circuit pattern 40.
In this embodiment, after the step (f) in fig. 1, the non-conductive film 41 around the 1 st circuit pattern 40 may be dissolved in an organic solvent or the like and removed. Thus, as shown in fig. 3, only the 1 st circuit pattern 40 may be disposed below the electronic component 30.
In the above description, the formation region of the film 41 formed in the steps (b) and (c) of fig. 1 may be defined as one region including both the pair of 1 st circuit patterns 40 (see fig. 1 (h)) for forming the 1 st circuit pattern 40, or may be divided into two regions including the pair of 1 st circuit patterns 40. In this case, the film 41 formed in both areas is formed continuously with the 2 nd circuit pattern 50.
< embodiment 2 >
In embodiment 2, the 2 nd circuit pattern 50 is formed by light irradiation.
In embodiment 2, a part or the whole of the 2 nd circuit pattern 50 is constituted by a layer formed by sintering conductive particles. In this case, as the conductive particles, conductive nanoparticles having a particle diameter of less than 1 μm and conductive micron-sized particles having a particle diameter of 1 μm or more (referred to as conductive microparticles) are mixed and used. Thus, when the conductive particles are irradiated with light, the conductive nanoparticles are melted first and are bonded to the surrounding conductive microparticles. Therefore, the conductive microparticles can be sintered at a temperature lower than that of the main body by light irradiation from the conductive nanoparticles. Therefore, by using the conductive microparticles and the conductive nanoparticles in combination, a layer having a large thickness can be formed relatively easily, and the 2 nd circuit pattern can be formed by sintering the conductive microparticles and the conductive nanoparticles by light irradiation.
The 2 nd circuit pattern 50 contains conductive particles having a particle diameter of 1 to 100 μm. The wiring width of the 2 nd circuit pattern 50 may be 10 μm or more, and may be formed to be, for example, about 100 μm. The 2 nd circuit pattern 50 may be formed to have a thickness of about 1 μm to 100 μm, for example, about 20 μm. Further, the resistance value of the 2 nd circuit pattern 50 is preferably 10-4Ω/cm2Hereinafter, particularly preferably 10-6Ω/cm2Low resistance of orders of magnitude or less.
The production method is explained below. First, the substrate 10 is prepared.
Next, a solution in which conductive nanoparticles, conductive microparticles, and an insulating material are dispersed in a solvent, or a solution in which conductive nanoparticles and conductive microparticles covered with a layer of an insulating material are dispersed in a solvent is prepared. As the solvent, an organic solvent or water can be used.
The solution is applied in a desired shape to the area on the surface of the substrate 10 where the 2 nd circuit pattern 50 is to be formed. The applied solution forms a coating film. The coating film is dried by heating as necessary. The conductive nanoparticles and the conductive microparticles are dispersed in the coating film, and the periphery of each particle is covered with an insulating material. Therefore, the coating film is nonconductive in this state.
Next, the shape of the 2 nd circuit pattern 50 is irradiated with light on the coating film. The electrically conductive nanoparticles are melted by light at a temperature lower than the electrically conductive microparticles and fuse with adjacent electrically conductive nanoparticles and electrically conductive microparticles. In this way, sintering occurs starting from the nanoparticles, and thus sintering at a lower temperature than the bulk (bulk) can be achieved. Further, sintering can also occur only in a desired range in the thickness direction of the coating film. Thereby, the 2 nd circuit pattern 50 of a desired shape may be formed.
As the wavelength of the light to be irradiated, a wavelength that can be absorbed by the conductive nanoparticles and the conductive microparticles contained in the coating film is selected and used. The shape of the 2 nd circuit pattern 50 to which light is applied can be formed using a mask having a predetermined opening. Further, it is also possible to use a light beam condensed to an irradiation diameter smaller than the wiring width of the 2 nd circuit pattern 50 and scan the light beam, thereby irradiating only the 2 nd circuit pattern 50 with light.
The areas of the coating film not irradiated with light do not sinter and therefore remain non-conductive. The non-sintered region of the non-conductive film 41 may be left or removed in a subsequent step.
In the above-described manufacturing method, the method of forming the coating film in a range larger than the region of the 2 nd circuit pattern 50 and irradiating only the region of the 2 nd circuit pattern 50 with light has been described, and the coating film may be formed by printing the solution in which the conductive particles are dispersed on the shape of the 2 nd circuit pattern 50 by using a printing method. In this case, the entire coating film formed by printing is irradiated with light, whereby the 2 nd circuit pattern 50 can be formed.
After the 2 nd circuit pattern 50 is formed through the above steps, the manufacturing steps of embodiment 1 are performed to manufacture an electronic device.
< embodiment 3 >
In embodiment 2, after the 2 nd circuit pattern 50 is formed on the substrate 10, the manufacturing method of embodiment 1 is performed, whereas in embodiment 3, after the 2 nd circuit pattern 50 is formed as a coating film in embodiment 2, the manufacturing method of embodiment 1 is performed without light irradiation, and the film 41 as the 1 st circuit pattern 40 is formed.
And, the photo-sintering of the 2 nd circuit pattern 50 and the 1 st circuit pattern 40 is performed continuously or simultaneously. The region of the 2 nd circuit pattern 50 is irradiated with light having a wavelength absorbed by the conductive particles of the coating film of the 2 nd circuit pattern 50, and the region of the 1 st circuit pattern 40 is irradiated with light having a wavelength absorbed by the conductive nanoparticles of the film 41. The intensity of the light to be irradiated is also adjusted to an intensity that can sinter the 2 nd circuit pattern 50 and the 1 st circuit pattern 40, respectively.
Thereafter, the manufacturing method of embodiment 1 is performed to complete an electronic device.
In this way, the firing is performed continuously or simultaneously by the light irradiation of the 2 nd circuit pattern 50 and the 1 st circuit pattern 40, and thus the light irradiation step in the entire manufacturing process can be performed at one time, and thus the manufacturing efficiency is improved.
In the manufacturing method of embodiment 2, the order of the step of forming the 2 nd circuit pattern 50 and the step of forming the 1 st circuit pattern 40 may be changed, and the 2 nd circuit pattern 50 may be formed after the 1 st circuit pattern 40 is formed. Similarly, in embodiment 3, the order of forming the coating film of the 2 nd circuit pattern 50 and the film 41 of the 1 st circuit pattern 40 may be interchanged, and the coating film of the 2 nd circuit pattern 50 may be formed after the film 41 of the 1 st circuit pattern 40 is formed. After that, light irradiation of the two circuit patterns is performed continuously or simultaneously.
< embodiment 4 >
A manufacturing method of embodiment 4 will be described with reference to fig. 4 and 5.
In embodiment 4, an electronic component 30 having electrodes 31 on both the upper surface and the lower surface is used. The electronic component 30 is sandwiched between 2 substrates 10-1, 10-2 from above and below.
Through the steps (a) to (g) of fig. 1 of embodiment 1, the 1 st circuit pattern 40-1 is formed, and the electrode 31-1 on the lower surface of the electronic component 30 is fastened to the 1 st circuit pattern 40-1 on the substrate 10-1.
On the other hand, the other substrate 10-2 is subjected to the treatments (a) to (c) of FIG. 1 to form a film 41-2. The other substrate 10-2 is mounted on the electronic component 30 in such a manner that the film 41-2 contacts the electrode 31-2 on the upper surface. Then, the film 41-2 on the upper side is irradiated with light in a predetermined pattern from the back surface (upper surface) side of the other substrate 10-2. Thereby, the 1 st circuit pattern 40-2 connected to the electrode 31-2 of the upper surface of the electronic component 30 is formed. At the same time, the 1 st circuit pattern 40-2 is fastened to the electrode 31-2 of the upper surface of the electronic component 30.
Thus, an electronic device in which the electronic component 30 is sandwiched by 2 substrates 10-1 and 10-2 can be manufactured.
In addition, here, the 1 st circuit pattern 40-1 of the lower substrate 10-1 is connected to the electrode 31 of the electronic component 30 first compared to the upper substrate 10-1, but the present invention is not limited to this order. The connection is preferably performed from the side requiring high positional accuracy.
In the structure of fig. 4, the 2 nd circuit pattern 50-1 formed on the substrate 10-1 and the 2 nd circuit pattern 50-2 formed on the substrate 10-2 are connected in the vertical direction by the vertical conduction part 50-3. After the 2 nd circuit patterns 50-1 and 50-2 are formed, the substrates 10-1 and 10-2 are stacked and the 2 nd circuit patterns 50-1 and 50-2 are irradiated with light and sintered in a state where they are in contact with each other, whereby the vertical conduction portions 50-3 can be formed simultaneously with the formation of the 2 nd circuit patterns 50-1 and 50-2.
< embodiment 5 >
As embodiment 5, a case where the electronic component 30 is an integrated circuit and there are many electrodes will be described. As a substrate, as shown in fig. 6 (a), a substrate on which a plurality of 2 nd circuit patterns 50 are formed is prepared. Then, a solution containing conductive nanoparticles is applied so as to be connected to the entire 2 nd circuit pattern 50 in fig. 6 (a), and a film 41 is formed as shown in fig. 6 (b). Next, as shown in fig. 6 (c), the electronic component 30 is mounted on the surface of the film 41, and the pattern connecting the electrode of the electronic component 30 and the 2 nd circuit pattern 50 is irradiated with light from the back surface of the transparent substrate 10 and fired. Thereby, the formation of the 1 st circuit pattern 40 and the fastening of the 1 st circuit pattern 40 to the electrode can be performed simultaneously.
< embodiment 6 >
As embodiment 6, an example in which the 1 st circuit pattern 40 is formed only in the area of the electronic component 30 will be described.
As shown in fig. 7 (a-1) and (a-2), a solution containing conductive nanoparticles is applied to a region of the transparent substrate 10 on which the electronic component 30 is mounted, thereby forming a film 41. Next, as shown in fig. 7 (b-1) and (b-2), the electronic component 30 is mounted on the surface of the film 41. As shown in fig. 7 (c-1) and (c-2), the pattern connecting the electrodes of the electronic component 30 and the 2 nd circuit pattern (not shown) is irradiated with light from the back surface of the substrate (not shown) and fired. Thereby, the formation of the 1 st circuit pattern 40 and the fastening of the 1 st circuit pattern 40 to the electrode of the electronic component 30 can be performed simultaneously.
In the present embodiment, it is possible to realize a configuration that cannot be realized in normal solder bonding, that is, to perform electrical connection and fastening in a region smaller than an electrode arrangement region (terminal portion) of the electronic component 30. Further, contact between the region other than the electrode 31 of the electronic component 30 and the 1 st circuit pattern 40 can be avoided, and problems such as electrical short-circuiting can be suppressed.
< 7 th embodiment >
As embodiment 7, a modification example of fig. 5 of embodiment 4 will be described.
In the structure of fig. 5, since the corner of the electronic component 30 is close to the 1 st circuit pattern 40-2, when the substrate 10-2 or the electronic component 30 is mounted while being tilted, the 1 st circuit pattern 40-2 may contact an edge or a burr of a semiconductor of the electronic component 30, thereby causing an electrical short circuit.
In the present embodiment, in order to prevent this, as shown in fig. 8, when light irradiation is performed from the back surface (upper surface) of the substrate 10-2 in order to form the 1 st circuit pattern 40-2, the light output of the 1 st circuit pattern 40-2 is weakened in a region near the corner of the electronic component 30, and the thickness of the sintered body is reduced. Thereby, the non-conductive portion 42 is formed.
With this structure, even if the electronic component 30 is inclined and contacts the non-conductive portion 42, an electrical short circuit can be prevented.
In addition, when the substrate 10 is bent, in the manufacturing method of embodiment 1, in order to prevent disconnection or disconnection of the 2 nd circuit pattern 50, it is preferable to bend the substrate 10 before the 2 nd circuit pattern 50 is formed. In the manufacturing methods of embodiments 2 to 3, if the substrate 10 is bent before the first light irradiation step is performed, disconnection of the 1 st and 2 nd circuit patterns can be prevented.
The effects of the embodiments are summarized as follows. In each embodiment, drawing of the 1 st circuit pattern 40 of a fine line pattern can be realized as compared with a relief printing method, whereby high-density wiring can be realized and high-density mounting can be performed. Further, the 1 st circuit pattern 40 can be drawn finely, and thus the electronic component 30 to be mounted can be downsized.
Since the 1 st circuit pattern 40 can be wired (formed) after the electronic component 30 is mounted, the mounting position accuracy of the electronic component 30 is improved. Further, as shown in embodiment 7, it is possible to realize a configuration that cannot be realized in normal solder bonding, that is, to realize electrical connection and fastening between the 1 st circuit pattern and the electrode in an area smaller than the terminal portion of the electronic component 30. Further, since the electronic component 30 can be continuously fixed while being mounted on the board 10, improvement of the production rhythm and the like can be realized.
According to the present embodiment, various electronic components can be mounted on the substrate 10 with high precision and high density, and can be mounted at a time by a small number of manufacturing steps to manufacture an electronic device. Further, the circuit pattern can be easily changed by light irradiation, and the design change can be easily coped with.
As the electronic component of the present embodiment, any configuration can be used as long as it is a component in which an electronic component is mounted on a substrate. For example, it can be used for a dashboard (meter display panel) of an automobile, a display portion of a game device, or the like. Further, since the substrate can be bent, it can be used for wearable (wearable on the body) electronic devices (glasses, watches, displays, medical devices, and the like) or curved displays.
Description of the reference symbols
10. substrate, 20. area for mounting electronic components, 30. electronic components, 31. electrode, 40. 1. 2. circuit pattern, 41. electrode.

Claims (7)

1. A method of manufacturing an electronic device, the electronic device having: a light-transmissive substrate; a 2 nd circuit pattern disposed on the substrate; a 1 st circuit pattern connected to the 2 nd circuit pattern; and an electronic component connected to the 1 st circuit pattern,
the method of manufacturing an electronic device is characterized in that,
the 1 st circuit pattern forming step includes:
a first step of applying a solution in which conductive nano-sized particles having a particle diameter of less than 1 μm and an insulating material are dispersed or a solution in which the conductive nano-sized particles coated with an insulating material layer are dispersed onto a surface of the substrate in a desired shape to form a film of the conductive nano-sized particles coated with the insulating material;
a 2 nd step of mounting the electronic component on the film; and
a 3 rd step of irradiating the film with light in a predetermined pattern from the back surface side of the substrate, sintering the conductive nano-sized particles by the light, and forming a layer of the predetermined pattern, which is formed by sintering the conductive nano-sized particles, to thereby form a 1 st circuit pattern connected to an electrode of the electronic component and fasten the 1 st circuit pattern to the electrode of the electronic component,
the 2 nd circuit pattern forming step includes:
a 4 th step of applying a solution in which conductive nano-sized particles having a particle diameter of less than 1 μm, conductive micro-sized particles having a particle diameter of 1 μm or more, and an insulating material are dispersed, or a solution in which the conductive nano-sized particles and the conductive micro-sized particles, each being coated with an insulating material layer, are dispersed, onto a surface of the substrate in a desired shape to form a 2 nd film of the conductive nano-sized particles and the conductive micro-sized particles coated with the insulating material; and
and a 5 th step of irradiating the 2 nd film with light in a predetermined pattern from the back surface side of the substrate, and sintering the conductive nano-sized particles and the conductive micro-sized particles with the light to form a 2 nd circuit pattern.
2. The method of manufacturing an electronic device according to claim 1,
the 4 th step and the 5 th step are performed before the 1 st step.
3. The method of manufacturing an electronic device according to claim 1,
the 4 th step is performed before the 1 st step or after the 1 st step and before the 3 rd step,
the light irradiation in the 5 th step is performed continuously or simultaneously with the light irradiation in the 3 rd step.
4. The method of manufacturing an electronic device according to claim 1,
as the electronic component, an electronic component having electrodes on both upper and lower surfaces is used,
after the electrodes on the lower surface of the electronic component and the 1 st circuit pattern of the substrate are fastened in the 3 rd step, the 2 nd substrate on which the 1 st step has been performed in advance is mounted on the electronic component such that the film contacts the electrodes on the upper surface, the film of the 2 nd substrate is irradiated with light in a predetermined pattern from the back surface side of the 2 nd substrate, the 1 st circuit pattern connected to the electrodes on the upper surface of the electronic component is formed, and the 1 st circuit pattern and the electrodes on the upper surface of the electronic component are fastened.
5. An electronic device, the electronic device having: a light-transmissive substrate; a 2 nd circuit pattern disposed on the substrate; a 1 st circuit pattern connected to the 2 nd circuit pattern; and an electronic component connected to the 1 st circuit pattern,
a part or the whole of the 1 st circuit pattern is composed of a layer sintered from conductive nano-particles having a particle diameter of less than 1 μm,
the electronic component has an electrode on the lower surface, the electrode on the lower surface being directly bonded to a layer formed by sintering the conductive nano-scale particles,
a non-conductive layer containing conductive nano-scale particles coated with an insulating film is continuously disposed on the layer sintered from the conductive nano-scale particles,
the 1 st circuit pattern is arranged in a region for mounting an electronic component provided on the substrate,
the substrate is further provided with the 2 nd circuit pattern, the 2 nd circuit pattern supplies current to the 1 st circuit pattern from the outside of the region,
the thickness of the 2 nd circuit pattern is greater than that of the 1 st circuit pattern,
the 2 nd circuit pattern is partially or entirely composed of a layer in which conductive particles are sintered, and the conductive particles include conductive nano-sized particles having a particle diameter of less than 1 μm and conductive micro-sized particles having a particle diameter of 1 μm or more.
6. The electronic device according to claim 5, wherein a width of the layer sintered from the conductive nano-scale particles in the 1 st circuit pattern is smaller than a width of the 2 nd circuit pattern.
7. The electronic device according to claim 5 or 6,
at least 2 of the substrates are provided, 2 of the substrates are oppositely arranged, and the 1 st circuit pattern is respectively provided on the surfaces which are opposite to each other,
the upper and lower surfaces of the electronic parts are connected to the 1 st circuit patterns of the 2 substrates facing each other, respectively.
CN201680016337.9A 2015-03-25 2016-03-17 Method for manufacturing electronic device and electronic device Active CN107432086B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2015-063328 2015-03-25
JP2015063328A JP6473361B2 (en) 2015-03-25 2015-03-25 Electronic device manufacturing method and electronic device
PCT/JP2016/058529 WO2016152728A1 (en) 2015-03-25 2016-03-17 Method for producing electronic device, and electronic device

Publications (2)

Publication Number Publication Date
CN107432086A CN107432086A (en) 2017-12-01
CN107432086B true CN107432086B (en) 2020-05-01

Family

ID=56978475

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201680016337.9A Active CN107432086B (en) 2015-03-25 2016-03-17 Method for manufacturing electronic device and electronic device

Country Status (4)

Country Link
US (1) US10085349B2 (en)
JP (1) JP6473361B2 (en)
CN (1) CN107432086B (en)
WO (1) WO2016152728A1 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6771346B2 (en) * 2016-09-23 2020-10-21 スタンレー電気株式会社 Manufacturing method of electronic device and electronic device
JP2018124743A (en) * 2017-01-31 2018-08-09 スタンレー電気株式会社 card
JP2018146632A (en) * 2017-03-01 2018-09-20 スタンレー電気株式会社 Display device and line of sight induction sheet
JP7037278B2 (en) * 2017-03-01 2022-03-16 スタンレー電気株式会社 Display device
JP6887321B2 (en) * 2017-06-14 2021-06-16 スタンレー電気株式会社 Light emitting device and its manufacturing method
JP6998138B2 (en) * 2017-06-21 2022-01-18 スタンレー電気株式会社 A light transmitting plate with a light emitting function and its manufacturing method
US10665576B2 (en) 2017-06-21 2020-05-26 Stanley Electric Co., Ltd. Optically transparent plate with light emitting function and method of producing the same
JP2019168622A (en) * 2018-03-26 2019-10-03 スタンレー電気株式会社 Visual line guide sheet, visual line guide system, vehicle luminaire, and vehicle
CN110416395A (en) * 2019-07-19 2019-11-05 厦门理工学院 A kind of LED chip
JP7408985B2 (en) 2019-10-07 2024-01-09 Ｔｏｐｐａｎホールディングス株式会社 Printing method, printing device and printed matter
CN111526669B (en) * 2020-05-07 2021-07-23 深圳市晶泓科技有限公司 Transparent circuit board and manufacturing method of transparent LED display screen

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014017364A (en) * 2012-07-09 2014-01-30 Panasonic Corp Manufacturing system and manufacturing method of component mounting substrate
JP2014075461A (en) * 2012-10-04 2014-04-24 Ricoh Co Ltd Conductive wiring and method for fabricating conductive wiring

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49121171A (en) 1973-03-28 1974-11-19
JPS61244094A (en) 1985-04-22 1986-10-30 株式会社東芝 Manufacture of multilayer wiring board
JPH0320907A (en) 1989-06-16 1991-01-29 Kawasaki Steel Corp Conductive paste
JP3791085B2 (en) 1997-01-16 2006-06-28 松下電器産業株式会社 Resistor paste, resistor using the same, and manufacturing method thereof
KR100687147B1 (en) * 2002-07-12 2007-02-27 샤프 가부시키가이샤 Active device substrate, method for manufacturing the active device substrate, active functional device, multi-color display apparatus, and display module
EP1626614B1 (en) * 2003-05-16 2013-08-28 Harima Chemicals, Inc. Method for forming fine copper particle sintered product type of electric conductor having fine shape, method for forming fine copper wiring and thin copper film
JP4536601B2 (en) * 2004-06-14 2010-09-01 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US7494923B2 (en) 2004-06-14 2009-02-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of wiring substrate and semiconductor device
JP2006165517A (en) 2004-11-11 2006-06-22 Sharp Corp Flexible wiring board, manufacturing method therof semiconductor device and electronic apparatus using it
WO2006076603A2 (en) * 2005-01-14 2006-07-20 Cabot Corporation Printable electrical conductors
JP2007129007A (en) * 2005-11-02 2007-05-24 Hitachi Ltd Method of manufacturing semiconductor device having organic semiconductor film
JP2008041960A (en) * 2006-08-07 2008-02-21 Nissan Chem Ind Ltd Manufacturing method of electronic circuit component
JP5181587B2 (en) * 2006-09-29 2013-04-10 大日本印刷株式会社 Organic semiconductor device and manufacturing method thereof, organic transistor array, and display
JP4965989B2 (en) * 2006-12-19 2012-07-04 新光電気工業株式会社 Electronic component built-in substrate and method for manufacturing electronic component built-in substrate
US8404160B2 (en) 2007-05-18 2013-03-26 Applied Nanotech Holdings, Inc. Metallic ink
US10231344B2 (en) 2007-05-18 2019-03-12 Applied Nanotech Holdings, Inc. Metallic ink
US20100000762A1 (en) 2008-07-02 2010-01-07 Applied Nanotech Holdings, Inc. Metallic pastes and inks
WO2010003138A1 (en) * 2008-07-03 2010-01-07 Ajjer Llc Novel electrochromic materials, devices and applications of the same
JP5503132B2 (en) 2008-10-29 2014-05-28 三ツ星ベルト株式会社 Resistor paste and resistor
JP5531843B2 (en) * 2009-07-31 2014-06-25 大日本印刷株式会社 Device material for hole injection transport layer, ink for forming hole injection transport layer, device having hole injection transport layer, and method for producing the same
WO2011036981A1 (en) * 2009-09-24 2011-03-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9812621B2 (en) * 2011-08-01 2017-11-07 Shikoku Instrumentation Co., Ltd. Semiconductor device and fabrication method for same
JP5895474B2 (en) * 2011-11-22 2016-03-30 東ソー株式会社 Conductive ink composition
KR101609497B1 (en) 2012-01-20 2016-04-05 도와 일렉트로닉스 가부시키가이샤 Bonding material and bonding method in which said bonding material is used
JP2014013828A (en) * 2012-07-04 2014-01-23 Panasonic Corp Manufacturing system of ic card and manufacturing method
JP6630053B2 (en) 2015-03-25 2020-01-15 スタンレー電気株式会社 Electronic device manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014017364A (en) * 2012-07-09 2014-01-30 Panasonic Corp Manufacturing system and manufacturing method of component mounting substrate
JP2014075461A (en) * 2012-10-04 2014-04-24 Ricoh Co Ltd Conductive wiring and method for fabricating conductive wiring

Also Published As

Publication number Publication date
WO2016152728A1 (en) 2016-09-29
JP2016184621A (en) 2016-10-20
JP6473361B2 (en) 2019-02-20
US20180077805A1 (en) 2018-03-15
CN107432086A (en) 2017-12-01
US10085349B2 (en) 2018-09-25

Similar Documents

Publication Publication Date Title
CN107432086B (en) Method for manufacturing electronic device and electronic device
US10383214B2 (en) Electronic device, method for producing same, and circuit substrate
JP6491032B2 (en) Manufacturing method of resistor and resistor
US10932373B2 (en) Circuit board, electronic circuit device, and production method of circuit board
EP3300129A1 (en) Semiconductor light-emitting device and method for producing the same
US9870072B2 (en) Touch device structure having through holes
JP6771346B2 (en) Manufacturing method of electronic device and electronic device
CN107871810B (en) Display device
WO2016170901A1 (en) Method for producing circuit board, method for producing electronic device, and electronic device
WO2016170902A1 (en) Electronic device production method, electronic device, circuit board production method, and circuit board
JP5846594B1 (en) Wiring formation method
JP7137354B2 (en) Multilayer circuit board and manufacturing method thereof
US10912201B2 (en) Electronic device and production method thereof
JP2020039002A (en) Electronic device
EP4117397A1 (en) Wiring formation method
KR20180057152A (en) Printed circuit board and package substrate
JP2005259988A (en) Multilayered wiring board and its manufacturing method
JP2016213325A (en) Multilayer wiring structure, multilayer wiring board, and manufacturing method of multilayer wiring structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant