CN107431001A - Semiconductor element and its manufacture method - Google Patents

Semiconductor element and its manufacture method Download PDF

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Publication number
CN107431001A
CN107431001A CN201680019663.5A CN201680019663A CN107431001A CN 107431001 A CN107431001 A CN 107431001A CN 201680019663 A CN201680019663 A CN 201680019663A CN 107431001 A CN107431001 A CN 107431001A
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CN
China
Prior art keywords
lateral electrode
back side
semiconductor element
electrode
phosphorus
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Granted
Application number
CN201680019663.5A
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Chinese (zh)
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CN107431001B (en
Inventor
砂本昌利
上野隆二
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Abstract

The semiconductor element (1) of the present invention is in the surface lateral electrode (3a) and back side lateral electrode (3b) of surface back side conducting type substrate (2) formed with non-electrolytic nickel-phosphorus coating (4) and electroless plating layer gold (5).Surface lateral electrode (3a) and back side lateral electrode (3b) include aluminium or aluminium alloy.In addition, the thickness for the non-electrolytic nickel-phosphorus coating (4) being formed in surface lateral electrode (3a) is more than 1.0 and less than 3.5 relative to the ratio of the thickness for the non-electrolytic nickel-phosphorus coating (4) being formed in back side lateral electrode (3b).The semiconductor element (1) of the present invention can prevent from producing emptying aperture inside solder when installing by soldering.

Description

Semiconductor element and its manufacture method
Technical field
The present invention relates to semiconductor element and its manufacture method.Specifically, the present invention relates to surface back side conducting type Semiconductor element, the power converter more particularly to IGBT (insulated gate bipolar transistor), diode etc. for representative Power semiconductor and its manufacture method.
Background technology
In the past, in the case of by the semiconductor element mounting of surface back side conducting type to module, the back of the body of semiconductor element Surface side electrode is soldered to substrate etc., and the surface lateral electrode of semiconductor element is by wire bonding.However, in recent years, according to shortening Manufacturing time and the viewpoint for cutting down fee of material, use the peace of the direct brazing metal electrode of surface lateral electrode to semiconductor element The situation of dress method becomes more.The surface lateral electrode of semiconductor element generally comprises aluminium or aluminium alloy, so in order to carry out soldering, Need to form nickel film, golden film etc. in the surface lateral electrode of semiconductor element.
Nickel film reacts in soldering and reduced with the solder of tin system, so needing to make nickel film by several μm of horizontal thick film Change.However, in the case where using the vacuum film formation mode such as evaporation or sputtering, generally, maximum can only obtain 1.0 μm or so Thickness.In addition, if wanting forcibly to make nickel thickness membranization, then manufacturing cost rises.Therefore, as can realize it is low into Originally, the film build method of high speed and thick-film, plating technique are attracted attention.
As plating technique, existing can be only in electrode (hereinafter referred to as " Al electrodes ") table including aluminium or aluminium alloy The non-electrolytic plating of plating layer is formed selectively on face.As non-electrolytic plating, typically palladium chtalyst method and zinc are utilized Hydrochlorate method.
In palladium chtalyst method, palladium is separated out on the surface of Al electrodes as catalyst core, form electroless plating coating. In palladium method, the etch quantity of Al electrodes is few, and the flatness on the surface of electroless plating coating is good, on the other hand, because your gold palladium is Category, so manufacturing cost rises.
In addition, in zincate method, by making zinc be replaced with Al to be separated out as catalyst core on the surface of Al electrodes, shape Into electroless plating coating.The zincic acid saline solution used in the method is cheap, so being widely adopted.
In fact, in patent document 1, it is proposed that selected on the surface of the Al electrodes of semiconductor element by zincate method Form nickel coating and Gold plated Layer to property.
Prior art literature
Patent document 1：Japanese Unexamined Patent Publication 2005-51084 publications
The content of the invention
In the case of by the semiconductor element mounting of surface back side conducting type to module, place weld in substrate at normal temperatures Material, and after also semiconductor element is placed thereon, heated with reflow ovens, so as to by the back side lateral electrode of semiconductor element It is soldered to substrate.Now, the scaling powder in solder, be formed at the hydrogen included in the electroplated film of electrode or moisture etc. and be used as gas Produce.If these gases keep remaining in inside solder, as emptying aperture (hole).Emptying aperture inside solder hinders electrical conduction Or heat transfer, so the reason for action as generation semiconductor element is bad.In order to remove emptying aperture inside solder, it is necessary to Micro-vibration etc. is applied to semiconductor element in soldering, but in the case of by multiple semiconductor element mountings to substrate, needed Complicated device is wanted, and productivity ratio also reduces.
The present invention completes to solve the problems, such as above-mentioned, and its object is to provide one kind to install by soldering When, can prevent inside solder produce emptying aperture semiconductor element and its manufacture method.
Present inventor carries out wholwe-hearted research discovery afterwards to solve the above problems, and electrode and plating are used by selection The material of layer, and the thickness of plating layer is controlled, have before the brazing in a manner of the surface for making semiconductor element is in inner side Meaning ground makes semiconductor element warpage, thereby, it is possible to easily be discharged to the outside the emptying aperture inside solder, and completes the present invention.
That is, the present invention provides a kind of semiconductor element, surface lateral electrode and the back side in surface back side conducting type substrate It is characterised by lateral electrode formed with non-electrolytic nickel-phosphorus coating and electroless plating layer gold, the semiconductor element, the table Surface side electrode and the back side lateral electrode include aluminium or aluminium alloy, also, are formed at described in the surface lateral electrode The ratio of the thickness of the relative non-electrolytic nickel-phosphorus coating being formed in the back side lateral electrode of the thickness of non-electrolytic nickel-phosphorus coating Example is more than 1.0 and less than 3.5.
In addition, the present invention provides a kind of manufacture method of semiconductor element, by surface lateral electrode and back side lateral electrode It is formed at after surface back side conducting type substrate, using zincate method, to the surface lateral electrode and the back side lateral electrode This two side carries out electroless phosphorus plating and electroless plating gold simultaneously, and the feature of the manufacture method of the semiconductor element exists Include aluminium or aluminium alloy in, the surface lateral electrode and the back side lateral electrode, also, by the table of the surface lateral electrode Area is set to more than 0.3 and less than 0.85 relative to the ratio of the surface area of the back side lateral electrode.
In accordance with the invention it is possible to provide the semiconductor that can prevent that emptying aperture is produced inside solder when being installed by soldering Element and its manufacture method.
Brief description of the drawings
Fig. 1 is the profile of the semiconductor element of embodiment 1.
Fig. 2 is the figure for illustrating the method for a non-electrolytic nickel phosphor plating.
Fig. 3 is the figure for illustrating the method for another non-electrolytic nickel phosphor plating.
Fig. 4 is the figure for illustrating the method for another non-electrolytic nickel phosphor plating.
(symbol description)
1：Semiconductor element；2：Surface back side conducting type substrate；3a：Surface lateral electrode；3b：Back side lateral electrode；4：Non-electrical Solve nickel-phosphorus coating；5：Electroless plating layer gold；6：Diaphragm；10：Electroless phosphorus plating solution；11：Dummy material.
Embodiment
Hereinafter, using accompanying drawing, the semiconductor element of the present invention and its preferred embodiment of manufacture method are illustrated.
Embodiment 1.
Fig. 1 is the profile of the semiconductor element of present embodiment.
In Fig. 1, the semiconductor element 1 of present embodiment includes surface back side conducting type substrate 2, is formed at surface back side The surface lateral electrode 3a of one interarea (surface) of conducting type substrate 2, another master for being formed at surface back side conducting type substrate 2 The back side lateral electrode 3b in face (back side), the non-electrolytic nickel-phosphorus coating 4 formed on surface lateral electrode 3a and back side lateral electrode 3b And it is formed at the electroless plating layer gold 5 on non-electrolytic nickel-phosphorus coating 4.In addition, it is provided with diaphragm on the lateral electrode 3a of surface 6。
The semiconductor element 1 of present embodiment is characterised by, in order to be prevented when being installed by soldering inside solder Emptying aperture is produced, intentionally sticks up semiconductor element 1 in a manner of the surface for making semiconductor element 1 is in inner side before the brazing It is bent.In addition, in Fig. 1, the warpage of semiconductor element 1 is not shown.
In order to apply warpage to semiconductor element 1, it is necessary to system will be expanded with the line bigger than surface back side conducting type substrate 2 Several electrodes and plating layer, which are set, arrives surface back side conducting type substrate 2.Therefore, in the semiconductor element 1 of present embodiment, As electrode, selection includes the surface lateral electrode 3a and back side lateral electrode 3b of aluminium or aluminium alloy, as plating layer, selects non- It is electrolysed nickel-phosphorus coating 4 and electroless plating layer gold 5.In addition, it is generally used for the line expansion system of the silicon of surface back side conducting type substrate 2 Number is about 2.3ppm/ DEG C, in contrast, the linear expansion coefficient of aluminium is about 23ppm/ DEG C, the linear expansion coefficient of nickel phosphorus is about 12~ 13ppm/ DEG C, golden linear expansion coefficient is about 14.2ppm/ DEG C.
Next, the surface of semiconductor element 1 is set to be in the warpage of inner side, it is necessary to make in order to apply to semiconductor element 1 The electrode on the surface of semiconductor element 1 and the thickness of plating layer are more than the electrode and plating layer at the back side of semiconductor element 1 Thickness.Wherein, according to the viewpoint of the productivity ratio of semiconductor element 1, be preferably controlled in electrode and plating layer it is most thick simultaneously And it is easily controlled the thickness of the non-electrolytic nickel-phosphorus coating 4 of thickness.Therefore, the non-electrolytic nickel phosphor plating for being formed at surface lateral electrode 3a is made The thickness of layer 4 is more than the thickness for the non-electrolytic nickel-phosphorus coating 4 being formed on the lateral electrode 3b of the back side.
In particular, it is desirable to the thickness for the non-electrolytic nickel-phosphorus coating 4 for making to be formed on the lateral electrode 3a of surface is relative to formation In the non-electrolytic nickel-phosphorus coating 4 on the lateral electrode 3b of the back side thickness ratio for more than 1.0 and less than 3.5, preferably 1.05 with It is upper and less than 3.5, more preferably more than 1.2 and less than 3.4.When the ratio is less than 1.0, the warpage of semiconductor element 1 is not filled Point, emptying aperture is produced inside solder in soldering.On the other hand, when the ratio is more than 3.5, the warpage of semiconductor element 1 becomes Too much, warpage residues in semiconductor element 1 after the brazing.
As surface back side conducting type substrate 2, it is not particularly limited, Si substrates, SiC substrate, GaAs chemical combination can be used The known semiconductor substrate in the technical field such as thing system substrate.There is surface back side conducting type substrate 2 diffusion layer (not scheme Show), possess the function of controlling the actions of semiconductor element 1 such as PN junction, gate electrode.
As described above, surface lateral electrode 3a and back side lateral electrode 3b includes aluminium or aluminium alloy.
As aluminium alloy, it is not particularly limited, the known material in the technical field can be used.Aluminium alloy preferably contains There is the element of (noble) more expensive than aluminium.By the way that containing the element more expensive than aluminium, electroless phosphorus plating is being carried out using zincate method When, electronics is easily from the existing aluminium outflow around the element, so promoting the dissolving of aluminium.In addition, aluminium dissolving part, Zinc intensively separates out, and the precipitation quantitative change as the zinc for the starting point for forming non-electrolytic nickel-phosphorus coating 4 is more, so easily forming non-electrolytic Nickel-phosphorus coating 4.
As the element more expensive than aluminium, be not particularly limited, for example, can enumerate iron, nickel, tin, lead, silicon, copper, silver, gold, Tungsten, cobalt, platinum, palladium, iridium, rhodium etc..In these elements, preferably copper, silicon, iron, nickel, silver, gold.In addition, these elements can be single Solely use or combine two or more use.
The content of the expensive element of ratio aluminium in aluminium alloy is not particularly limited, preferably below 5 mass %, more preferably More than 0.05 mass % and below 3 mass %, more preferably more than 0.1 mass % and below 2 mass %.
The element expensive for the ratio aluminium contained in surface lateral electrode 3a and the back side lateral electrode 3b aluminium alloy both can phase Together can also be different.However, rear side is being formed by the element ratio for making to contain in the aluminium alloy for forming surface lateral electrode 3a The element contained in electrode 3b aluminium alloy is expensive, easily makes the thickness for being formed at surface lateral electrode 3a non-electrolytic nickel-phosphorus coating 4 More than the thickness for the non-electrolytic nickel-phosphorus coating 4 being formed on the lateral electrode 3b of the back side.
Surface lateral electrode 3a and the back side lateral electrode 3b thickness are not particularly limited, and apply according to semiconductor element 1 Make semiconductor element 1 surface be in inner side warpage viewpoint, preferably surface lateral electrode 3a thickness is more than back side lateral electrode 3b thickness.
Surface lateral electrode 3a thickness is in general 1 μm~8 μm, preferably 2 μm~7 μm, more preferably 3 μm~6 μm.
Back side lateral electrode 3b thickness is in general 0.1 μm~4 μm, preferably 0.5 μm~3 μm, more preferably 0.8 μm ~2 μm.
The non-electrolytic nickel-phosphorus coating 4 formed on surface lateral electrode 3a and back side lateral electrode 3b is not particularly limited, energy Enough use the material of various compositions.
Phosphorus concentration in non-electrolytic nickel-phosphorus coating 4 is in general below 15 mass %, the matter of preferably 1 mass %~12 Measure %, the mass % of more preferably 3 mass %~10.Phosphorus concentration in the non-electrolytic nickel-phosphorus coating 4 is in non-electrolytic nickel-phosphorus coating 4 Thickness it is more thick, become lower tendency.
The thickness of the non-electrolytic nickel-phosphorus coating 4 formed on surface lateral electrode 3a and back side lateral electrode 3b is as long as there is upper The ratio of bright thickness is stated, is not particularly limited.
The thickness for the non-electrolytic nickel-phosphorus coating 4 being formed on the lateral electrode 3a of surface is in general 3 μm~10 μm, is preferably 4 μm~9 μm, more preferably 3 μm~8 μm.
The thickness for the non-electrolytic nickel-phosphorus coating 4 being formed on the lateral electrode 3b of the back side is in general 1 μm~7 μm, is preferably 1.5 μm~6 μm, more preferably 2 μm~5 μm.
The thickness for the electroless plating layer gold 5 being formed on non-electrolytic nickel-phosphorus coating 4 is not particularly limited, it is however generally that is Less than 0.1 μm, preferably 0.01 μm~0.08 μm, more preferably 0.02 μm~0.05 μm.
In addition, the surface for making semiconductor element 1 according to applying to semiconductor element 1 is in the viewpoint of the warpage of inner side, table The thickness of the electroless plating layer gold 5 in face is preferably greater than the thickness of the electroless plating layer gold 5 at the back side.
As diaphragm 6, it is not particularly limited, the known example in the technical field can be used.
Semiconductor element 1 with above-mentioned construction is in the warpage of inner side with making the surface of semiconductor element 1.
Specifically, the amount of warpage of semiconductor element 1 is preferably 0.2mm~2mm, more preferably 0.3mm~1.8mm, is entered One step is preferably 0.4mm~1.6mm.If the amount of warpage of such scope, then semiconductor device 1 is being installed by soldering When, it can prevent from producing emptying aperture inside solder.
Here, the amount of warpage of semiconductor element 1 means make the backside down of semiconductor element 1 be configured on platform When the distance away from platform surface of the end of semiconductor element 1 that tilts.
After surface lateral electrode 3a and back side lateral electrode 3b are formed at into surface back side conducting type substrate 2, zinc is used Hydrochlorate method, electroless phosphorus plating and electroless plating are carried out simultaneously to surface lateral electrode 3a and this two side of back side lateral electrode 3b Gold, so as to manufacture the semiconductor element 1 with above-mentioned construction.
In order to carry out electroless phosphorus plating simultaneously to surface lateral electrode 3a and this two side of back side lateral electrode 3b and half-and-half Conductor element 1, which applies, makes the surface of semiconductor element 1 be in the warpage of inner side, it is necessary to make surface lateral electrode 3a surface area relative In back side lateral electrode 3b surface area ratio be more than 0.3 and less than 0.85, preferably more than 0.5 and less than 0.85, it is more excellent Elect more than 0.6 and less than 0.8 as.
Specifically, as shown in Fig. 2 by formed with surface area different surface lateral electrode 3a's and back side lateral electrode 3b Surface back side conducting type substrate 2 is impregnated into electroless phosphorus plating solution 10.In addition, in fig. 2, omit diaphragm 6.Pass through Above-mentioned difference is set to surface lateral electrode 3a and the back side lateral electrode 3b surface area, surface lateral electrode 3a and rear side can be made The formation velocity variations of non-electrolytic nickel-phosphorus coating 4 at electrode 3b, so can be in surface lateral electrode 3a and back side lateral electrode The different non-electrolytic nickel-phosphorus coating 4 of thickness is formed at 3b.
In addition, the in order that formation speed of the non-electrolytic nickel-phosphorus coating 4 at surface lateral electrode 3a and back side lateral electrode 3b Change, can also make bath (bath) load variations.Here, bath load means that the electrode of electroless phosphorus plating will be carried out Surface area (dm2) divided by the capacity (L) of plating solution obtained from value.Surface lateral electrode 3a bath load is preferably 0.2dm2/ L~2dm2/ L, more preferably 0.3dm2/ L~1.5dm2/L.Back side lateral electrode 3b bath load is preferably 1.0dm2/ L~ 10dm2/ L, more preferably 2.0dm2/ L~9.0dm2/L。
In addition, the in order that formation speed of the non-electrolytic nickel-phosphorus coating 4 at surface lateral electrode 3a and back side lateral electrode 3b Change, can also be as shown in figure 3, carry out electroless phosphorus in the position configuration dummy material 11 opposed with back side lateral electrode 3b Plating.In addition, in figure 3, omit diaphragm 6.Electroless phosphorus plating is carried out by using such method, surface can be increased The difference of the formation speed of non-electrolytic nickel-phosphorus coating 4 between lateral electrode 3a and back side lateral electrode 3b.
As dummy material 11, as long as easily forming the material of non-electrolytic nickel-phosphorus coating 4, it is not particularly limited.Make For the example of dummy material 11, iron, platinum, gold, nickel, cobalt, silver or their alloy etc. can be enumerated.In them, it is preferably Iron, platinum, gold, nickel, cobalt.
Back side lateral electrode 3b and the distance of dummy material 11 are not particularly limited, preferably 2mm~20mm, more preferably 3mm~15mm, more preferably 4mm~12mm, most preferably 5mm~10mm.
In addition, the in order that formation speed of the non-electrolytic nickel-phosphorus coating 4 at surface lateral electrode 3a and back side lateral electrode 3b Change, can also be as shown in figure 4, prepare to turn on formed with surface lateral electrode 3a and back side lateral electrode 3b multiple surface back sides Type substrate 2, make the back side lateral electrode 3b of surface back side conducting type substrate 2 is opposite each other to carry out electroless phosphorus plating.In addition, In Fig. 4, diaphragm 6 is omitted.By using such method carry out electroless phosphorus plating, can increase surface lateral electrode 3a with The difference of the formation speed of non-electrolytic nickel-phosphorus coating 4 between the lateral electrode 3b of the back side, and can be to being turned in multiple surface back sides The surface lateral electrode 3a and back side lateral electrode 3b that are formed on type substrate 2 while electroless phosphorus plating is carried out, so productivity ratio Also improve.
The distance between back side lateral electrode 3b is not particularly limited, preferably 2mm~50mm, more preferably 3mm~40mm, More preferably 4mm~35mm, most preferably 5mm~30mm.
As the method that surface lateral electrode 3a and back side lateral electrode 3b are formed at into surface back side conducting type substrate 2, Known in the technical field, so the description thereof will be omitted, below explanation using zincate method electroless phosphorus plating and Electroless plating gold.
When forming non-electrical on the surface lateral electrode 3a and back side lateral electrode 3b for being formed at surface back side conducting type substrate 2 In the case of solving nickel-phosphorus coating 4 and electroless plating layer gold 5, typically, carry out successively plasma clean process, degreasing process, Pickling process, the first zincate treatment process, zincate stripping process, the second zincate treatment process, electroless phosphorus plating Process, electroless plating gold process.Between each operation, should sufficiently it be washed, the treatment fluid or residue of process before preventing It is brought into rear process.Hereinafter, the outline of each operation is illustrated.
In plasma clean process, surface lateral electrode 3a and the back of the body to being formed at surface back side conducting type substrate 2 Surface side electrode 3b carries out plasma clean.In order to carry out oxidation Decomposition etc. by using plasma, removal is firmly adhered to Surface lateral electrode 3a and the back side lateral electrode 3b debris, nitride or oxide, and ensure surface lateral electrode 3a and back side lateral electrode 3b and the pretreatment liquid of plating or the reactivity of plating solution, carry out plasma clean.Plasma Body cleaning is to surface lateral electrode 3a and back side lateral electrode 3b this two side progress, but preferably emphasis is carried out to surface lateral electrode 3a. In addition, the order as plasma clean, is not particularly limited, plasma clean preferably is being carried out to back side lateral electrode 3b Afterwards, plasma clean is carried out to surface lateral electrode 3a.The reason for this is that in the table side of semiconductor element 1, with face side electricity The diaphragm 6 that is made up of organic matter together be present in pole 3a, the residue of the diaphragm 6 be attached to surface lateral electrode 3a situation compared with It is more.
In degreasing process, surface lateral electrode 3a and back side lateral electrode 3b degreasing is carried out.Table is attached in order to remove Slight organic matter, lubricant component, the oxide-film on surface side electrode 3a and the back side lateral electrode 3b surface, carry out degreasing.Typically For, to surface lateral electrode 3a and back side lateral electrode 3b using the strong alkaline decoction of etching power, carry out degreasing.Pass through degreasing Process, lubricant component are saponified.In addition, on the material not being saponified, the solvable material of alkali is dissolved into the decoction, and alkali is not Solvable material is pulled away by surface lateral electrode 3a and the back side lateral electrode 3b etching.
In pickling process, pickling is carried out to surface lateral electrode 3a and back side lateral electrode 3b.In order to surface lateral electrode 3a and the back side lateral electrode 3b surface are neutralized and are roughened by etching, the treatment fluid after raising in process Reactivity, the adhesive force of plating is improved, so as to carry out pickling.
In the first zincate treatment process, zincic acid salt treatment is carried out to surface lateral electrode 3a and back side lateral electrode 3b. Here, zincic acid salt treatment refers to be etched oxide film dissolving of making a return journey on the surface to surface lateral electrode 3a and back side lateral electrode 3b While formed zinc overlay film processing.In general, surface lateral electrode 3a and back side lateral electrode 3b are being impregnated into dissolving When having the aqueous solution (the zincate treatment fluid) of zinc, due to compared to form surface lateral electrode 3a and back side lateral electrode 3b aluminium or Person's aluminium alloy, the standard oxidationreduction potential of zinc is more expensive, so aluminium is as ion-solubility.By this caused electronics, zinc from Son receives electronics at surface lateral electrode 3a and the back side lateral electrode 3b surface, lateral electrode 3a and back side lateral electrode on surface 3b surface forms the overlay film of zinc.
In zincate stripping process, by the surface lateral electrode 3a and back side lateral electrode of overlay film of the surface formed with zinc 3b is impregnated into nitric acid, dissolves zinc.
In the second zincate treatment process, by the surface lateral electrode 3a obtained by zincate stripping process and the back side Lateral electrode 3b is impregnated into zincate treatment fluid again.Thus, removing aluminium and its while oxide-film, on surface lateral electrode 3a with And back side lateral electrode 3b surface forms the overlay film of zinc.
The reasons why carrying out above-mentioned zincate stripping process and the second zincate treatment process is, makes surface lateral electrode 3a And back side lateral electrode 3b surface is smoothened.In addition, the repetition time of zincate treatment process and zincate stripping process Number is more, then surface lateral electrode 3a and the back side lateral electrode 3b surface are more smooth, forms more uniform non-electrolytic nickel-phosphorus coating 4 And electroless plating layer gold 5.But when considering the balance of surface smoothness and productivity ratio, preferably zincic acid salt treatment is carried out Twice, more preferably carry out three times.
In electroless phosphorus plating process, by the way that the surface lateral electrode 3a and rear side of the overlay film formed with zinc is electric Pole 3b is impregnated into electroless phosphorus plating solution 10, forms non-electrolytic nickel-phosphorus coating 4.The face side of the overlay film formed with zinc is electric When pole 3a and back side lateral electrode 3b are impregnated into electroless phosphorus plating solution 10, initially, zinc is compared to nickel, standard oxidation reduction electricity Position is low-priceder, so nickel separates out on surface lateral electrode 3a and back side lateral electrode 3b.Next, when being covered on surface by nickel, lead to The effect of the reducing agent included is crossed in electroless phosphorus plating solution 10, is separated out to nickel self-catalysis.In the precipitation of the self-catalysis, The composition of reducing agent (hypophosphorous acid) is introduced in electroplated film, so forming the non-electrolytic nickel-phosphorus coating 4 as alloy.In addition, When the concentration of reducing agent is high, non-electrolytic nickel-phosphorus coating 4 turns into noncrystal.In addition, persistently produced all the time in electroless phosphorus plating Raw hydrogen, so the occlusion hydrogen in non-electrolytic nickel-phosphorus coating 4.
In electroless plating gold process, by the surface lateral electrode 3a formed with non-electrolytic nickel-phosphorus coating 4 and the back side Lateral electrode 3b carries out electroless plating gold, forms electroless plating layer gold 5.In general, carried out by the method for being referred to as displaced type Electroless plating gold.By using the effect of the complexing agent included in electroless plating gold liquid, nickel and the gold of non-electrolytic nickel-phosphorus coating 4 Enter line replacement, so as to carry out the electroless plating gold of displaced type.In addition, surface quilt of the electroless plating gold in non-electrolytic nickel-phosphorus coating 4 Reaction stops during gold covering, so being difficult to make electroless plating layer gold 5 thickening, its thickness maximum is 0.08 μ, is in general 0.08 μm or so.But as soldering purposes, come in the case of utilizing, the even above-mentioned value of thickness of electroless plating layer gold 5 is not yet Can be too small.
Embodiment
Hereinafter, by embodiment, the present invention is described in detail, but the present invention is not limited to this.
(embodiment 1)
In embodiment 1, the semiconductor element 1 with the construction shown in Fig. 1 is made.
First, as surface back side conducting type substrate 2, the thickness for preparing diffusion layer be 70 μm Si substrates (14mm × 14mm)。
Next, on the surface of Si substrates, the aluminium electrode (5 μm of thickness) and diaphragm as surface lateral electrode 3a are formed 6, at the back side of Si substrates, form the aluminium electrode (1 μm of thickness) as back side lateral electrode 3b.Here, by surface lateral electrode 3a's Surface area is set to 0.60 relative to the ratio of back side lateral electrode 3b surface area.
Next, by carrying out each operation under conditions of shown in following tables 1, semiconductor element 1 is obtained.It is in addition, logical The method shown in Fig. 2 is crossed, carries out electroless phosphorus plating.In addition, between each operation, the washing using pure water is carried out.
[table 1]
Process Project Condition etc.
1 Plasma clean Ar (100cc/ minutes), 800W, 2 minutes, vacuum IOPa
2 Degreasing Alkaline degreaser, pH9.5,70 DEG C, 3 minutes
3 Pickling 10% sulfuric acid, 30 DEG C, 1 minute
4 First zincic acid salt treatment Alkaline zincate treatment fluid, pH12,25 DEG C, 20 seconds
5 Zincate is peeled off Nitric acid, 25 DEG C, 15 seconds
6 Second zincic acid salt treatment Alkaline zincate treatment fluid, pH12,25 DEG C, 20 seconds
7 Electroless phosphorus plating Acid electroless phosphorus plating solution, pH5.0,85 DEG C, 25 minutes
8 Electroless plating gold Acid electroless plating gold liquid, pH6.5,90 DEG C, 30 minutes
The fluorescent X-ray film thickness measuring device sold using market, is determined in surface lateral electrode 3a and back side lateral electrode The non-electrolytic nickel-phosphorus coating 4 and the thickness of electroless plating layer gold 5 formed on 3b.As a result, it is formed on the lateral electrode 3a of surface Non-electrolytic nickel-phosphorus coating 4 and the thickness of electroless plating layer gold 5 be 7.1 μm and 0.03 μm respectively.In addition, it is formed at the back side The thickness of non-electrolytic nickel-phosphorus coating 4 and electroless plating layer gold 5 on lateral electrode 3b is 3.9 μm and 0.03 μm respectively.
Next, after making non-electrolytic nickel-phosphorus coating 4 be dissolved into the water containing acid or alkali, determined using ICP in table The phosphorus concentration of the non-electrolytic nickel-phosphorus coating 4 formed on surface side electrode 3a and back side lateral electrode 3b.As a result, it is formed at face side The phosphorus concentration of non-electrolytic nickel-phosphorus coating 4 on electrode 3a is 6.9 mass %, the electroless phosphorus being formed on the lateral electrode 3b of the back side The phosphorus concentration of coating 4 is 8.2 mass %.
Next, the backside down for the semiconductor element 1 for making to produce is placed on platform, by the semiconductor element of tilting The distance away from platform surface of the end of part 1 determines as the amount of warpage of semiconductor element 1.As a result, amount of warpage is 0.7mm。
Collect the result of embodiment 1 in following tables 2.
[table 2]
(embodiment 2)
In example 2, the semiconductor element 1 with the construction shown in Fig. 1 is made.
First, as surface back side conducting type substrate 2, the thickness for preparing diffusion layer be 70 μm Si substrates (14mm × 14mm)。
Next, on the surface of Si substrates, the aluminum alloy anode (5 μm of thickness) as surface lateral electrode 3a and guarantor are formed Cuticula 6, at the back side of Si substrates, form the aluminum alloy anode (1 μm of thickness) as back side lateral electrode 3b.Here, in aluminium alloy In electrode, shown in table 3 described as follows, at a predetermined ratio containing predetermined element.In addition, make surface lateral electrode 3a surface area Ratio relative to back side lateral electrode 3b surface area is 0.60.
[table 3]
Next, by method same as Example 1 and under the conditions of carry out each operation, obtain semiconductor element 1.
Similarly to Example 1, the electroless phosphorus formed on surface lateral electrode 3a and back side lateral electrode 3b is determined The amount of warpage of the thickness and semiconductor element 1 of coating 4 and electroless plating layer gold 5.Its result is shown in following tables 4.
[table 4]
(embodiment 3)
In embodiment 3, the semiconductor element 1 with the construction shown in Fig. 1 is made.
In embodiment 3, the species of the aluminium alloy for surface lateral electrode 3a and back side lateral electrode 3b is changed to carry out Experiment.Shown in table 5 described as follows, aluminium alloy contains predetermined element at a predetermined ratio.In addition, the table by surface lateral electrode 3a Area is set to 0.60 relative to the ratio of back side lateral electrode 3b surface area.
[table 5]
Next, by method same as Example 1 and under the conditions of carry out each operation, obtain semiconductor element 1.
Similarly to Example 1, the electroless phosphorus formed on surface lateral electrode 3a and back side lateral electrode 3b is determined The amount of warpage of the thickness and semiconductor element 1 of coating 4 and electroless plating layer gold 5.Its result is shown in following tables 6.
[table 6]
(embodiment 4)
In example 4, the semiconductor element 1 with the construction shown in Fig. 1 is made.
In example 4, surface lateral electrode 3a surface area is changed relative to the ratio of back side lateral electrode 3b surface area And bath load is tested.In addition to the ratio and bath load that change the surface area, same as Example 1 Method and under the conditions of, carry out each operation, so as to obtain semiconductor element 1.
Similarly to Example 1, the electroless phosphorus formed on surface lateral electrode 3a and back side lateral electrode 3b is determined The amount of warpage of the thickness and semiconductor element 1 of coating 4 and electroless plating layer gold 5.Its result is shown in following tables 7.
[table 7]
(embodiment 5)
In embodiment 5, the semiconductor element 1 with the construction shown in Fig. 1 is made.
In embodiment 5, except the ratio by surface lateral electrode 3a surface area relative to back side lateral electrode 3b surface area Beyond example is set to 0.70 and carries out electroless phosphorus plating with the method shown in Fig. 3, in method same as Example 1 and Under the conditions of, each operation is carried out, so as to obtain semiconductor element 1.In addition, the dummy material 11 during as electroless phosphorus plating, Use the material shown in following tables 8.In addition, shown in the distance of back side lateral electrode 3b and dummy material 11 table 8 described as follows.
Similarly to Example 1, the electroless phosphorus formed on surface lateral electrode 3a and back side lateral electrode 3b is determined The amount of warpage of the thickness and semiconductor element 1 of coating 4 and electroless plating layer gold 5.Its result is shown in following tables 8.
[table 8]
(embodiment 6)
In embodiment 6, the semiconductor element 1 with the construction shown in Fig. 1 is made.
In embodiment 6, except the ratio by surface lateral electrode 3a surface area relative to back side lateral electrode 3b surface area Beyond example is set to 0.70 and carries out electroless phosphorus plating with the method shown in Fig. 4, in method same as Example 1 and Under the conditions of, each operation is carried out, so as to obtain semiconductor element 1.In addition, the distance between back side lateral electrode 3b tables 9 described as follows It is shown.
Similarly to Example 1, the electroless phosphorus formed on surface lateral electrode 3a and back side lateral electrode 3b is determined The amount of warpage of the thickness and semiconductor element 1 of coating 4 and electroless plating layer gold 5.Its result is shown in following tables 8.
[table 9]
(embodiment 7)
By placing solder and after the semiconductor element 1 obtained in embodiment 1~6 is also placed on thereon in substrate, With backflow stove heat, the back side lateral electrode 3b of semiconductor element 1 is soldered to substrate.As a result, confirm in solder part not Emptying aperture be present, and the semiconductor element 1 of soldering is without warpage.
(embodiment 8)
In embodiment 8, surface lateral electrode 3a and the back side lateral electrode 3b non-electrolytic nickel phosphor plating are formed at except changing Beyond ratio of the thickness and change surface lateral electrode 3a of layer relative to back side lateral electrode 3b surface area, use and embodiment 1 identical method and condition are come after making the semiconductor element 1 with the construction shown in Fig. 1, by same as Example 7 Method, the back side lateral electrode 3b of semiconductor element 1 is soldered to substrate.
Similarly to Example 1, the electroless phosphorus formed on surface lateral electrode 3a and back side lateral electrode 3b is determined The amount of warpage of the thickness and semiconductor element 1 of coating 4 and electroless plating layer gold 5.In addition, evaluation whether there is sky in solder part Hole.These results are shown in following tables 10.
[table 10]
As shown in table 10, the thickness of the non-electrolytic nickel-phosphorus coating on surface lateral electrode 3a is formed at relative to be formed at the back of the body When the ratio of the thickness of non-electrolytic nickel-phosphorus coating on the electrode 3b of surface side is more than 1.0, emptying aperture (sample is not produced in solder part 8-1~8-3), in contrast, when the ratio is less than 1.0, emptying aperture (sample 8-4) is produced in solder part.
In addition, the surface area in surface lateral electrode 3a relative to the ratio of back side lateral electrode 3b surface area is less than 0.85 When, do not produce emptying aperture (sample 8-1~8-3) in solder part, in contrast, when the ratio is more than 0.85, in solder part Produce emptying aperture (sample 8-4).
It was found from result more than, in accordance with the invention it is possible to which providing can prevent in solder when being installed by soldering Portion produces the semiconductor element and its manufacture method of emptying aperture.
In addition, this international application is advocated based in Japanese patent application 2015-077528 filed in 6 days April in 2015 Number priority, home quote the full contents of these Japanese patent applications in the application of border.

Claims (8)

  1. A kind of 1. semiconductor element, formed with non-in the surface lateral electrode and back side lateral electrode of surface back side conducting type substrate It is electrolysed nickel-phosphorus coating and electroless plating layer gold, the semiconductor element is characterised by,
    The surface lateral electrode and the back side lateral electrode include aluminium or aluminium alloy, and
    The thickness for the non-electrolytic nickel-phosphorus coating being formed in the surface lateral electrode is relative to be formed at the back side lateral electrode On the ratio of thickness of the non-electrolytic nickel-phosphorus coating be more than 1.0 and less than 3.5.
  2. 2. semiconductor element according to claim 1, it is characterised in that
    The aluminium alloy for forming the surface lateral electrode and the back side lateral electrode contains the element more expensive than aluminium.
  3. 3. semiconductor element according to claim 2, it is characterised in that
    The element ratio contained in the aluminium alloy for forming the surface lateral electrode is forming the back side lateral electrode The element contained in the aluminium alloy is expensive.
  4. 4. a kind of manufacture method of semiconductor element, surface lateral electrode and back side lateral electrode are being formed at surface back side conducting After type substrate, non-electrolytic is carried out simultaneously to the surface lateral electrode and this two side of the back side lateral electrode using zincate method Nickel phosphor plating is coated with and electroless plating gold, and the manufacture method of the semiconductor element is characterised by,
    The surface lateral electrode and the back side lateral electrode include aluminium or aluminium alloy, and
    By the surface area of the surface lateral electrode relative to the ratio of the surface area of the back side lateral electrode be set to more than 0.3 and Less than 0.85.
  5. 5. the manufacture method of semiconductor element according to claim 4, it is characterised in that
    The aluminium alloy for forming the surface lateral electrode and the back side lateral electrode contains the element more expensive than aluminium.
  6. 6. the manufacture method of semiconductor element according to claim 5, it is characterised in that
    The element ratio contained in the aluminium alloy for forming the surface lateral electrode is forming the back side lateral electrode The element contained in the aluminium alloy is expensive.
  7. 7. the manufacture method of the semiconductor element described in any one in claim 4~6, it is characterised in that
    Dummy material is being configured with the position of the rear side electrode contraposition to carry out electroless phosphorus plating.
  8. 8. the manufacture method of the semiconductor element described in any one in claim 4~6, it is characterised in that
    Prepare multiple surface back side conducting type substrates formed with the surface lateral electrode and the back side lateral electrode, make The back side lateral electrode of multiple surface back side conducting type substrates carries out electroless phosphorus plating opposite each otherly.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110060926A (en) * 2018-01-19 2019-07-26 三菱电机株式会社 The manufacturing method of semiconductor device
CN110249074A (en) * 2017-02-15 2019-09-17 三菱电机株式会社 Semiconductor element and its manufacturing method
CN111742395A (en) * 2018-02-22 2020-10-02 三菱电机株式会社 Semiconductor device and method for manufacturing the same
WO2024065293A1 (en) * 2022-09-28 2024-04-04 泉州三安半导体科技有限公司 Light-emitting diode and light-emitting apparatus

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10937657B2 (en) * 2016-10-28 2021-03-02 Mitsubishi Electric Corporation Semiconductor device including a reactant metal layer disposed between an aluminum alloy film and a catalyst metal film and method for manufacturing thereof
CN106773384A (en) * 2016-12-20 2017-05-31 深圳市华星光电技术有限公司 Goa circuit structure
JP2019016738A (en) * 2017-07-10 2019-01-31 トヨタ自動車株式会社 Semiconductor device
DE102017125096B4 (en) * 2017-10-26 2022-05-19 Hanon Systems Method of making a scroll compressor and scroll compressor made with the method
JP7229330B2 (en) * 2018-01-19 2023-02-27 三菱電機株式会社 Semiconductor device manufacturing method
US20220049357A1 (en) * 2019-04-10 2022-02-17 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011066341A (en) * 2009-09-18 2011-03-31 Toyota Motor Corp Method for manufacturing semiconductor device
JP2011077460A (en) * 2009-10-02 2011-04-14 Toyota Motor Corp Semiconductor device, and manufacturing method thereof
JP2013194291A (en) * 2012-03-21 2013-09-30 Mitsubishi Electric Corp Semiconductor device and method for manufacturing the same
CN104425580A (en) * 2013-09-09 2015-03-18 株式会社东芝 Power semiconductor device and manufacturing method thereof

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58102556A (en) * 1981-12-14 1983-06-18 Mitsubishi Electric Corp Semiconductor device
JP2003068959A (en) * 2001-08-22 2003-03-07 Denso Corp Semiconductor device
JP3767585B2 (en) * 2003-07-11 2006-04-19 株式会社デンソー Semiconductor device
JP4344560B2 (en) 2003-07-30 2009-10-14 富士電機ホールディングス株式会社 Semiconductor chip and semiconductor device using the same
US7993983B1 (en) * 2003-11-17 2011-08-09 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with chip and encapsulant grinding
JP2005179724A (en) 2003-12-18 2005-07-07 Meltex Inc Electroless plating apparatus
JP2005200687A (en) 2004-01-14 2005-07-28 Murata Mfg Co Ltd Electroless plating method
KR100907841B1 (en) * 2004-09-24 2009-07-14 이비덴 가부시키가이샤 Plating method and plating device
JP4815905B2 (en) * 2005-07-11 2011-11-16 株式会社デンソー Semiconductor device and manufacturing method thereof
JP2008305948A (en) * 2007-06-07 2008-12-18 Denso Corp Semiconductor device and manufacturing method of the same
JP2009249659A (en) * 2008-04-02 2009-10-29 Nippon Mektron Ltd Electroplating device and electroplating method
US7838332B2 (en) * 2008-11-26 2010-11-23 Infineon Technologies Ag Method of manufacturing a semiconductor package with a bump using a carrier
JP5483906B2 (en) * 2009-03-04 2014-05-07 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP5452130B2 (en) * 2009-08-20 2014-03-26 株式会社デンソー Manufacturing method of semiconductor device
JP6020040B2 (en) * 2012-10-26 2016-11-02 富士電機株式会社 Manufacturing method of semiconductor device
JP2015050347A (en) * 2013-09-02 2015-03-16 トヨタ自動車株式会社 Semiconductor device and manufacturing method of the same
JP2017059636A (en) * 2015-09-15 2017-03-23 三菱電機株式会社 Method for manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011066341A (en) * 2009-09-18 2011-03-31 Toyota Motor Corp Method for manufacturing semiconductor device
JP2011077460A (en) * 2009-10-02 2011-04-14 Toyota Motor Corp Semiconductor device, and manufacturing method thereof
JP2013194291A (en) * 2012-03-21 2013-09-30 Mitsubishi Electric Corp Semiconductor device and method for manufacturing the same
CN104425580A (en) * 2013-09-09 2015-03-18 株式会社东芝 Power semiconductor device and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110249074A (en) * 2017-02-15 2019-09-17 三菱电机株式会社 Semiconductor element and its manufacturing method
CN110249074B (en) * 2017-02-15 2021-11-02 三菱电机株式会社 Semiconductor device and method for manufacturing the same
CN110060926A (en) * 2018-01-19 2019-07-26 三菱电机株式会社 The manufacturing method of semiconductor device
CN110060926B (en) * 2018-01-19 2023-06-13 三菱电机株式会社 Method for manufacturing semiconductor device
CN111742395A (en) * 2018-02-22 2020-10-02 三菱电机株式会社 Semiconductor device and method for manufacturing the same
WO2024065293A1 (en) * 2022-09-28 2024-04-04 泉州三安半导体科技有限公司 Light-emitting diode and light-emitting apparatus

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