CN107424553A - Scan drive circuit plate and display device - Google Patents
Scan drive circuit plate and display device Download PDFInfo
- Publication number
- CN107424553A CN107424553A CN201710871460.5A CN201710871460A CN107424553A CN 107424553 A CN107424553 A CN 107424553A CN 201710871460 A CN201710871460 A CN 201710871460A CN 107424553 A CN107424553 A CN 107424553A
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- Prior art keywords
- signal
- parameter
- delay
- unit
- debugging
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
Abstract
The present invention discloses a kind of scan drive circuit plate and display device.Display device includes viewing area, signal connecting plate, SECO plate, signal transducer and scan drive circuit plate, and SECO plate includes timing controller and electrical level transferring chip, and scan drive circuit plate includes debugging interface and connects online debugging apparatus；The time sequence parameter of memory storage driving time；Drive control chip reads the time sequence parameter of driving time and the time sequence parameter by debugging interface on-line debugging driving time, and produces signal waveform according to time sequence parameter, with by carrying out on-line debugging to driving time to meet the testing requirement of display device.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of scan drive circuit plate and display device.
Background technology
GOA (Gate Driver On Array, the driving of array base palte row) is to be collected using array process on array base palte
Into grid horizontal drive circuit, the grid drive chip originally on array base palte can be saved, reaching reduces production cost and reality
The purpose of existing narrow frame, the structural representation of existing display device is as shown in figure 1, it supports UD (Ultra High
Definition) Display Technique is the SECO with 3840 × 2160 (4K × 2K) and above resolution ratio (8K)
(Timing Controller, TCON) chip, it can not carry out on-line debugging to the driving time of display device, therefore can not
Meet the testing requirement of display device.
The content of the invention
The present invention solves the technical problem of a kind of scan drive circuit plate and display device is provided, with by aobvious
The driving time of showing device carries out on-line debugging to meet the testing requirement of display device.
In order to solve the above technical problems, one aspect of the present invention is：A kind of scan drive circuit plate is provided,
Including：
Debugging interface, for connecting online debugging apparatus；
Memory, the time sequence parameter for the storage driving time；
Drive control chip, the memory is connected, for reading the sequential ginseng of the driving time from the memory
Number is to be initialized, and the drive control chip is also connected with the debugging interface, for by being connected with the debugging interface
On-line debugging device on-line debugging described in driving time time sequence parameter, and according to the time sequence parameter produce signal waveform.
In order to solve the above technical problems, one aspect of the present invention is：A kind of display device is provided, its feature
It is, the display device includes viewing area, the signal connecting plate being connected with the viewing area and the signal connecting plate
The SECO plate of connection, the signal transducer and scan drive circuit plate being connected with the SECO plate, the signal turn
Change plate to be used to connect video source, the scan drive circuit plate is used to connect online debugging apparatus, and the signal connecting plate is used for
Oscillograph is connected, the SECO plate includes timing controller and electrical level transferring chip, wherein the scan drive circuit
Plate includes：
Debugging interface, for connecting online debugging apparatus；
Memory, the time sequence parameter for the storage driving time；
Drive control chip, the memory is connected, for reading the sequential ginseng of the driving time from the memory
Number is to be initialized, and the drive control chip is also connected with the debugging interface, for by being connected with the debugging interface
On-line debugging device on-line debugging described in driving time time sequence parameter, and according to the time sequence parameter produce signal waveform.
The beneficial effects of the invention are as follows：The situation of prior art is different from, the display device of the invention passes through setting
The scan drive circuit plate, and drive control chip, memory and debugging interface are set on the scan drive circuit plate,
To cause the scan drive circuit plate to connect the SECO plate and on-line debugging device, and filled by the on-line debugging
Put and on-line debugging is carried out to the time sequence parameter of the driving time, the testing requirement of the display device is met with this.
Brief description of the drawings
Fig. 1 is the structural representation of existing display device；
Fig. 2 is the structural representation of the display device of the present invention；
Fig. 3 is the circuit diagram of the scan drive circuit plate in Fig. 2 and SECO plate；
Fig. 4 is the circuit diagram of the scan drive circuit plate in Fig. 2；
Fig. 5 is the driving time waveform diagram of the present invention.
Embodiment
Fig. 2 to Fig. 4 is refer to, is the structural representation of the display device of the present invention.The display device 1 includes viewing area
Domain 10, the signal connecting plate 11 being connected with the viewing area 10, the SECO plate 12 being connected with the signal connecting plate 11,
The signal transducer 13 and scan drive circuit plate 14 being connected with the SECO plate 12, the signal transducer 13 are used to connect
Connecing video source 2, the scan drive circuit plate 14 is used to connect online debugging apparatus by I2C buses jig plate 3, such as computer 4,
The signal connecting plate 11 is used to connect oscillograph 5, and the SECO plate 12 includes timing controller 121 and level conversion
Chip 122, wherein the scan drive circuit plate 14 includes：
Debugging interface 143, for connecting online debugging apparatus, such as computer 3；
Memory 141, the time sequence parameter for the storage driving time；And
Drive control chip 142, the memory 141 is connected, for reading the driving time from the memory 141
Time sequence parameter to be initialized, the drive control chip 142 is also connected with the debugging interface 143, for by with institute
The time sequence parameter of driving time described in the on-line debugging device on-line debugging of the connection of debugging interface 143 is stated, and according to the sequential
Parameter produces signal waveform.
In the present embodiment, the viewing area 10, the signal connecting plate 11, the signal transducer 13 and it is described when
Other devices and function on sequence control panel 12 are same as the prior art, the timing controller on the SECO plate 12
121 and electrical level transferring chip 122 it is also same as the prior art, will not be repeated here.The on-line debugging device is computer 4, its
It is electrically connected with by I2C buses jig plate 3 and the scan drive circuit plate 14, wherein the I2C buses jig plate 3 is existing
Technology, it will not be repeated here.The signal transducer 13 is used to picture signal being converted to control signal, as LVDS signals are changed
For Vx1 signals.
Specifically, the drive control chip 142 includes parameter configuration unit 1421 and driving time unit 1422, described
Parameter configuration unit 1421 is used to read the time sequence parameter of the driving time from the memory 141 to be initialized and be led to
Cross the time sequence parameter of driving time described in the on-line debugging device on-line debugging being connected with the debugging interface 143, the driving
Time quantum 1422 is used to produce signal waveform according to the time sequence parameter.
Specifically, the parameter configuration unit 1421 includes master unit 14211 and from unit 14212, the master unit
14211 are used to read the time sequence parameter of the driving time from the memory 141 to be initialized, described from unit
The 14212 sequential ginseng for driving time described in the on-line debugging device on-line debugging by being connected with the debugging interface 143
Number.
Specifically, the driving time unit 1422 includes：
Trigger signal delay unit 14221, the delay parameter in the parameter configuration unit 1421 is to the video
Data effective index signal DE enters line delay, to produce Time delay signal STV_DE；
Clock signal delay unit 14222, the delay parameter in the parameter configuration unit 1421 is to the video
Data effective index signal DE enters line delay, to produce clock delay signal CK_DE；Wherein, the clock signal delay unit
14222 is same with the function phase of the trigger signal delay unit 14221, but the two units are independent, are so being carried out
When line is debugged, it can not disturb mutually.
Trigger signal generation unit 14223, trigger signal parameter in the parameter configuration unit 1421 and described
Time delay signal STV_DE produces trigger signal STV waveforms；
Dock signal generation unit 14224, the clock signal CK parameters in the parameter configuration unit 1421, video
Data effective index signal DE parameters and the clock delay signal CK_DE produce clock signal CK waveforms, such as clock signal
CK1, CK2, CK3, CK4 are until CKN clock signal waveform；And
Circuit switch-over control signal generation unit 14225, the circuit switching control in the parameter configuration unit 1421
The signal LC processed upset cycle and frame number is produced to be produced in the invalid period of frame by counting the Time delay signal STV_DE
Raw circuit switch-over control signal LC waveform.
In the present embodiment, the memory 141 is EEPROM, its driving time stored
Time sequence parameter includes trigger signal STV high level width, trigger signal STV delay clock number, clock signal CK height
Level width, clock signal CK delay clock number, circuit switch-over control signal LC upset cycle, video data effectively refer to
Show signal DE effective read clock number and the clock number of video data effective index signal DE clear area；The debugging
Interface 143 is I2C bus debugging interfaces, and the main equipment 14211 is I2C bus masters, and the slave unit 14212 is I2C
Bus slave, the video counts of the scan drive circuit plate 14 and the timing controller 121 on the SECO plate 12
Connected according to effective index signal DE and clock signal clk, on the scan drive circuit plate 14 and the SECO plate 12
The trigger signal STV of electrical level transferring chip 122, the first circuit switch-over control signal LC1, second circuit switch-over control signal LC2
And some clock signal CK connections.
Wherein, the scan drive circuit plate 14 passes through in flexible PCB (not shown) and the SECO plate 12
Timing controller 121 video data effective index signal DE and clock signal clk connection, and simultaneously with the SECO
The trigger signal STV of electrical level transferring chip 122 on plate 12, the first circuit switch-over control signal LC1, second circuit switching control
Signal LC2, the first clock signal CK1, second clock signal CK2, the 3rd clock signal CK3, the 4th clock signal CK4 etc. are straight
To the CKN connections of N clock signals, wherein N numerical value depends on the number of scanning lines of the display device.
The operation principle of the display device on-line tuning driving time is described as follows：
The oscillograph 5 and the signal connecting plate 11 are electrically connected with, the scan drive circuit plate 14 is controlled by I2C
Tool plate 3 is connected with computer 4, and the signal transducer 13 starts the display device 1 after being connected with video source 2, and the scanning is driven
The meeting power-up initializing of drive control chip 142 on dynamic circuit board 14, the inside of memory 141 is read by I2C buses and deposited
The time sequence parameter of the driving time of storage, after the time sequence parameter configuration successful, it is described to indicate to light corresponding indicator lamp
Time sequence parameter configuration is completed.Afterwards, the drive control chip 142 on the scan drive circuit plate 14 can join according to the sequential
Number sets corresponding registers, under the control of the clock signal clk of the timing controller 121 on the SECO plate 12 not
The disconnected detection video data effective index signal DE, the drive control chip on the scan drive circuit plate 14
142 can accordingly produce trigger signal STV, the first circuit switch-over control signal LC1, second circuit switch-over control signal LC2, first
Clock signal CK1, second clock signal CK2 ... N clock signal CKN, and shown (as shown in Figure 5) by oscillograph 5
To be supplied to tester to watch, such as described trigger signal STV dutycycle signal waveforms, due to the scan drive circuit plate
14 are connected to computer 4 by I2C jig plates 3, and now the software in computer 4 just passes through I2C jig plates 3 and turntable driving electricity
Road plate 14 is communicated, and now the drive control chip 142 on the scan drive circuit plate 14 turns into the slave of I2C buses,
And computer 4 turns into the main frame of I2C buses, test image (such as pure red, pure green, the ethereal blue etc. specified is played by the video source 2
Test image), tester sends driving time according to the signal waveform that the oscillograph 5 is shown by the computer 4
Time sequence parameter with the register of drive control chip 142 described in real-time update, realized with this and driving time exist
Line is debugged, to meet the testing requirement of the display device 1.After the completion of on-line debugging is carried out to the driving time, produce
To after the optimal time sequence parameter of the driving time, the computer 4 passes through the optimal time sequence parameter of the driving time described
I2C buses jig plate 3 is burnt in the memory 141 on the scan drive circuit plate 14, with the display device 1 again
During startup, the scan drive circuit plate 14 will use the optimal time sequence parameter of the driving time, and then can be to described aobvious
The other specification (algorithm of such as described timing controller) of showing device 1 is tested, to meet the survey of the display device 1
Examination demand.
The display device sets on the scan drive circuit plate and driven by setting the scan drive circuit plate
Dynamic control chip, memory and debugging interface, to cause the scan drive circuit plate to connect the SECO plate and online
Debugging apparatus, and on-line debugging is carried out to the time sequence parameter of the driving time by the on-line debugging device, met with this
The testing requirement of the display device.
Embodiments of the present invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize this
The equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other correlations
Technical field, it is included within the scope of the present invention.
Claims (10)
1. a kind of scan drive circuit plate, it is characterised in that the scan drive circuit plate includes：
Debugging interface, for connecting online debugging apparatus；
Memory, the time sequence parameter for the storage driving time；
Drive control chip, connect the memory, for the time sequence parameter of the driving time is read from the memory with
Initialized, the drive control chip is also connected with the debugging interface, for by being connected with the debugging interface
The time sequence parameter of driving time described in line debugging apparatus on-line debugging, and signal waveform is produced according to the time sequence parameter.
2. scan drive circuit plate according to claim 1, it is characterised in that the drive control chip is matched somebody with somebody including parameter
Unit and driving time unit are put, the parameter configuration unit is used for the sequential ginseng that the driving time is read from the memory
Number with initialized and the on-line debugging device on-line debugging by being connected with the debugging interface described in driving time when
Order parameter, the driving time unit are used to produce signal waveform according to the time sequence parameter.
3. scan drive circuit plate according to claim 2, it is characterised in that the parameter configuration unit includes master unit
And from unit, the master unit is used for the time sequence parameter from the memory reading driving time to be initialized, institute
The sequential from unit for driving time described in the on-line debugging device on-line debugging by being connected with the debugging interface is stated to join
Number.
4. scan drive circuit plate according to claim 3, it is characterised in that the driving time unit includes：
Trigger signal delay unit, the delay parameter in the parameter configuration unit effectively indicate to believe to the video data
Number enter line delay, to produce Time delay signal；
Clock signal delay unit, the delay parameter in the parameter configuration unit effectively indicate to believe to the video data
Number enter line delay, to produce clock delay signal；
Trigger signal generation unit, trigger signal parameter and Time delay signal production in the parameter configuration unit
Raw trigger signal waveform；
Dock signal generation unit, clock signal parameter, video data in the parameter configuration unit effectively indicate to believe
Number parameter and the clock delay signal produce clock signal waveform；And
Circuit switch-over control signal generation unit, the upset week of the circuit switch-over control signal in the parameter configuration unit
Phase and frame number is produced with the ripple of the invalid period generation circuit switch-over control signal of frame by counting the Time delay signal
Shape.
5. scan drive circuit plate according to claim 3, it is characterised in that the memory is electric erazable programmable
Read memory, the high level width of the time sequence parameter including trigger signal of its driving time stored, trigger signal delay when
Clock number, the high level width of clock signal, the delay clock number of clock signal, the upset week of circuit switch-over control signal
The clock of the clear area of phase, effective read clock number of video data effective index signal and video data effective index signal
Number；The debugging interface is I2C bus debugging interfaces, and the main equipment is I2C bus masters, and the slave unit is I2C
Bus slave.
A kind of 6. display device, it is characterised in that the letter that the display device includes viewing area, is connected with the viewing area
Number connecting plate, the SECO plate being connected with the signal connecting plate, the signal transducer being connected with the SECO plate and
Scan drive circuit plate, the signal transducer are used to connect video source, and the scan drive circuit plate is used to connect online tune
Trial assembly is put, and the signal connecting plate is used to connect oscillograph, and the SECO plate includes timing controller and level conversion
Chip, wherein the scan drive circuit plate includes：
Debugging interface, for connecting online debugging apparatus；
Memory, the time sequence parameter for the storage driving time；
Drive control chip, connect the memory, for the time sequence parameter of the driving time is read from the memory with
Initialized, the drive control chip is also connected with the debugging interface, for by being connected with the debugging interface
The time sequence parameter of driving time described in line debugging apparatus on-line debugging, and signal waveform is produced according to the time sequence parameter.
7. display device according to claim 6, it is characterised in that the drive control chip includes parameter configuration unit
And driving time unit, the parameter configuration unit are used for from the time sequence parameter of the memory reading driving time to enter
The time sequence parameter of driving time described in row initialization and the on-line debugging device on-line debugging by being connected with the debugging interface,
The driving time unit is used to produce signal waveform according to the time sequence parameter.
8. display device according to claim 7, it is characterised in that the parameter configuration unit includes master unit and from list
Member, the master unit is used for the time sequence parameter from the memory reading driving time to be initialized, described from list
Time sequence parameter of the member for driving time described in the on-line debugging device on-line debugging by being connected with the debugging interface.
9. display device according to claim 8, it is characterised in that the driving time unit includes：
Trigger signal delay unit, the delay parameter in the parameter configuration unit effectively indicate to believe to the video data
Number enter line delay, to produce Time delay signal；
Clock signal delay unit, the delay parameter in the parameter configuration unit effectively indicate to believe to the video data
Number enter line delay, to produce clock delay signal；
Trigger signal generation unit, trigger signal parameter and Time delay signal production in the parameter configuration unit
Raw trigger signal waveform；
Dock signal generation unit, clock signal parameter, video data in the parameter configuration unit effectively indicate to believe
Number parameter and the clock delay signal produce clock signal waveform；And
Circuit switch-over control signal generation unit, the upset week of the circuit switch-over control signal in the parameter configuration unit
Phase and frame number is produced with the ripple of the invalid period generation circuit switch-over control signal of frame by counting the Time delay signal
Shape.
10. display device according to claim 8, it is characterised in that the memory is deposited for electric erazable programmable is read-only
Reservoir, the time sequence parameter of its driving time stored include the high level width of trigger signal, the delay clock of trigger signal
Number, the high level width of clock signal, the delay clock number of clock signal, circuit switch-over control signal the upset cycle, regard
Frequency according to effective index signal effective read clock number and video data effective index signal clear area clock number；
The debugging interface is I2C bus debugging interfaces, and the main equipment is I2C bus masters, the slave unit be I2C buses from
Equipment, the video data effective index signal of the scan drive circuit plate and the timing controller on the SECO plate
And clock signal connects, the trigger signal of the electrical level transferring chip on the scan drive circuit plate and the SECO plate,
First circuit switch-over control signal, second circuit switch-over control signal and the connection of some clock signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710871460.5A CN107424553B (en) | 2017-09-22 | 2017-09-22 | Scanning driving circuit board and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710871460.5A CN107424553B (en) | 2017-09-22 | 2017-09-22 | Scanning driving circuit board and display device |
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| CN107424553A true CN107424553A (en) | 2017-12-01 |
| CN107424553B CN107424553B (en) | 2020-12-04 |
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| CN201710871460.5A Active CN107424553B (en) | 2017-09-22 | 2017-09-22 | Scanning driving circuit board and display device |
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| CN108520714A (en) * | 2018-03-27 | 2018-09-11 | 苏州佳智彩光电科技有限公司 | A kind of test method and system for supporting OLED screen multiple-working mode |
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| CN110888766A (en) * | 2019-11-18 | 2020-03-17 | 珠海泰芯半导体有限公司 | Chip starting method |
| CN114255712A (en) * | 2020-09-22 | 2022-03-29 | 咸阳彩虹光电科技有限公司 | Display method and display device |
| CN114255712B (en) * | 2020-09-22 | 2023-02-03 | 咸阳彩虹光电科技有限公司 | Display method and display device |
| CN112133236A (en) * | 2020-09-28 | 2020-12-25 | 深圳创维－Rgb电子有限公司 | Display screen testing method, oscilloscope and storage medium |
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