CN107423160A - A kind of method and device of raising NAND flash reading rates - Google Patents
A kind of method and device of raising NAND flash reading rates Download PDFInfo
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- CN107423160A CN107423160A CN201710606312.0A CN201710606312A CN107423160A CN 107423160 A CN107423160 A CN 107423160A CN 201710606312 A CN201710606312 A CN 201710606312A CN 107423160 A CN107423160 A CN 107423160A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Abstract
The present invention discloses a kind of method and device of raising NAND flash reading rates, stressed operation is put into hardware and realized by the present invention, and when error bit number occur and exceed ECC error correction scope, automatic triggering, which is read again, to be operated, it is not required to software and is reconfigured at an order, saves the time that CPU accesses bottom；Secondly the present invention allows CPU to update stressed parameter, and dynamic, which adjusts, reads parameter again, improves stressed hit rate to greatest extent, and hardware is configured from optimal voltage parameter, is reduced and is read number again, so as to improve reading rate.The present apparatus retains the stressed function of original traditional software control, while can also select actively to be initiated to read again by hardware；Hardware is read again automatically, eliminates break period and CPU processing setup times；CPU can be adjusted according to stressed result to the stressed parameter in SRAM, can also be adjusted read voltage during common read command, double shield, be improved and read hit rate again, reduce and read number again, so as to improve flash reading rate.
Description
Technical field
The present invention relates to a kind of method and apparatus of raising NAND flash reading rates, belong to Design of Digital Integrated Circuit skill
Art field.
Background technology
Determined by NAND flash characteristics, flash every page data is divided into one or more ECC block, and data are write
Fashionable, each ECC block will carry out ECC error correction coding；When reading data, each ECC block carry out ECC error correction solution
Code, to ensure that this ECC block data are correct.ECC can correction bits number have certain limit, during beyond the scope, that is, send out
The mistake that ECC can not be corrected is given birth to.Now need to read the ECC block again, i.e., by parameter adjustment, change current reading electricity
The offset of pressure, re-reads data.
P/E cycle are the important indicators for judging NAND flash life cycles, regardless of whether P/E cycle how much, NAND
It is the same the time required to flash read command；And the reading rate of NAND flash is influenceed it is critical that flash was operated
Cheng Zhong, the read voltage of acquiescence correctly can not read data, it is necessary to adjust read voltage sometimes, re-read data.This
Operation is divided into two steps, the first successive step read voltage；Second step resends read command.And this operation is generally required and repeatedly followed
Ring, be required for every time one by one parameter go to test, the time for reading page of data becomes this page and reads multiple time.It is i.e. existing
The method of data is re-read by software can cause flash reading rate very slow.
The content of the invention
The defects of for prior art, the present invention provide a kind of method and device of raising NAND flash reading rates, this
Stressed operation is put into hardware and realized by invention, so as to improve flash reading rate.
In order to solve the technical problem, the technical solution adopted by the present invention is：One kind improves NAND flash reading rates
Method, realized by following hardware system, the system includes NAND control systems and stressed module, and NAND control systems include
NAND controller and register, NAND controller is interior to set correction module, reads again and reads command sequence, correction module built in module again
Selector is connected to by logic and operation device with register, module is read again and NAND controller is connected to by selector；Work
When, by CPU configuration registers, decide whether enabled automatically stressed function；If do not enabled, it is not turned on reading module again；Error correction
Module make a mistake spilling when, produce interruption, from CPU control whole system new order is re-write to register；If make
Function can be read again automatically, make a mistake spilling when, NAND control systems from stressed module read in read again command sequence, start weight
Read, current page data is all read correctly or reading failure, terminates to read process again, reads module again and stressed result is write into register
Interrupt bit, read successful parameter again, CPU controls whole system to carry out subsequent treatment afterwards.
The method of raising NAND flash reading rates of the present invention, the stressed module also include address generation module,
Order generation module and SRAM module, the input of address generation module are connected with NAND controller, for receiving NAND controls
Device is transmitted through the info signals come；The input of order generation module is connected with the output end of address generation module, for receiving ground
The address parameter of location generation module output；Read again to deposit in command sequence and read order again, and read the input of command sequence again
It is connected with the output end of order generation module, updates the information for reading order again for receiving, the output end for reading command sequence again connects
NAND controller is connect, command sequence is read again for being exported to NAND controller；SRAM module accesses configuration by CPU and reads parameter again,
And the output end of SRAM module is connected with order generation module, parameter is read again for being transmitted to order generation module.
The method of raising NAND flash reading rates of the present invention, when stressed module is triggered, read module each several part again
Operation be：1st, the data that address generation module receives the current page address of NAND controller write-in, current page needs to read are grown
The initial address of degree, the data length that success is read and data buffer area；Then address generation module output current operation page
Stressed address, address cache new initial address and the remaining data length for needing to read；2nd, order generation module detects
There is change to the output of address generation module, then update the output information of address generation module into command sequence；3rd, order generation
Module detects that CPU have accessed SRAM, then re-reads SRAM, undated parameter, in writing commands sequence.
The method of raising NAND flash reading rates of the present invention, order generation module is by address from low to high suitable
Sequence, the parameter being successively read in SRAM.
The method of raising NAND flash reading rates of the present invention, when stressed module is not triggered, order generation mould
Block is read in the parameter that SRAM lowest address is deposited and writing commands sequence all the time；CPU read result again according to last time, and selection is most
Excellent parameter, updates SRAM at any time, the parameter in order generation module real-time update command sequence, is prepared to read again next time.
The method of raising NAND flash reading rates of the present invention, this method realize that automatically stressed step is：1.
CPU opens stressed function automatically in a register；
2. being currently read operation, make a mistake spilling, starts and reads again, and NAND control systems carry out warm reset, NAND control systems
All command sequences are read in from the stressed command sequence in stressed module and are performed；
3. reading module again detects that NAND control systems have accessed stressed command sequence, Article 2 parameter, renewal are read from SRAM
Command sequence；
4. the signal that address generation module transmits according to NAND control systems, recalculate the signal of output；Order generation simultaneously
Module detects the exporting change of address generation module, updates the content in command sequence；
5. order generation module detects that the residue of address generation module output needs to read data length when being 0, to reset and read
SRAM address, reads parameter from lowest address, updates command sequence, so far completes reading again for one page.Into interrupt register
Write-in, which is read again, successfully to be interrupted, reads successful parameter again；
6. during step 5 is performed, if reading order failure corresponding to first parameter again, make a mistake spilling again,
Repeat step 2-5；But when performing step 3, Article 3 parameter is read from SRAM successively, until reading the last item；
7. if all parameters do not read the page successfully in SRAM, terminate to read again, write and read again into interrupt register
Failure is interrupted, reads successful parameter again.
The method of raising NAND flash reading rates of the present invention, the operation that NAND control systems carry out warm reset include
Empty command queue, NAND controller returns to IDLE state, internal system caching empties.
The method of raising NAND flash reading rates of the present invention, when emptying command queue, if had in command queue
A plurality of order, only remove the order that currently transmitted mistake is overflowed.
The invention also discloses a kind of device of raising NAND flash reading rates, including NAND control systems, NAND controls
Correction module is provided with inside device processed, is provided with NAND control systems by the automatic register for reading enabled order again of CPU configurations, error correction
Module and the output end of register are connected to the input of logic and operation device, and the output end of logic and operation device is connected to selection
Device, in one stressed module of NAND control systems periphery addition, read again to set in module and read command sequence again, read command sequence again
Chosen device is connected to NAND controller.
The invention also discloses a kind of device of raising NAND flash reading rates, the stressed module also includes address and given birth to
Into module, order generation module and SRAM module, the input of address generation module is connected with NAND controller, for receiving
NAND controller is transmitted through the info signals come；The input of order generation module is connected with the output end of address generation module, uses
In the address parameter for receiving the output of address generation module；Read again to deposit in command sequence and read order again, and read command sequence again
Input be connected with the output end of order generation module, update the information for reading order again for receiving, read command sequence again
Output end connects NAND controller, and command sequence is read again for being exported to NAND controller；SRAM module accesses configuration weight by CPU
Parameter is read, and the output end of SRAM module is connected with order generation module, and parameter is read again for being transmitted to order generation module.
Beneficial effects of the present invention：Stressed operation is put into hardware and realized by the present invention, exceeds when there is error bit number
During ECC error correction scope, operation is read in automatic triggering again, is not required to software and is reconfigured at an order, save CPU access bottom when
Between；Secondly the present invention allows CPU to update stressed parameter, and dynamic, which adjusts, reads parameter again, improves stressed hit rate to greatest extent, firmly
Part is configured from optimal voltage parameter, is reduced and is read number again, so as to improve reading rate.The present apparatus retains original traditional software
The stressed function of control, while can also select actively to be initiated to read again by hardware；Hardware is read again automatically, eliminate the break period and
CPU handles setup time；CPU can be adjusted according to stressed result to the stressed parameter in SRAM, can also be adjusted common
Read voltage during read command, double shield, improve and read hit rate again, reduce and read number again, so as to improve flash reading rate.
Brief description of the drawings
Fig. 1 attaches most importance to the structural representation that read through model is connected with NAND flash control systems；
Fig. 2 attaches most importance to the structural representation of read through model；
When Fig. 3 is reads again automatically, the variation diagram of command sequence is read again.
Embodiment
The present invention is described further with specific embodiment below in conjunction with the accompanying drawings.
Embodiment 1
The present embodiment discloses a kind of method of raising NAND flash reading rates, is realized by following system, as shown in figure 1, should
System includes NAND control systems and stressed module, and NAND control systems include command queue, selector, NAND controller, connect
Mouth mold block and NAND flash, command queue connect NAND controller by selector, and NAND controller is connected by interface module
Meet NAND flash.In order to improve NAND flash reading rate, correction module is set, and is controlled in NAND in NAND controller
Increase register in system, reads again and reads command sequence built in module again, correction module and register are connected by logic and operation device
Selector is connected to, module is read again and NAND controller is connected to by selector.During work, by CPU configuration registers, decide whether
Enabled automatically stressed function；If do not enabled, it is not turned on reading module again；Correction module make a mistake spilling when, produce interruption,
New order is re-write to register from CPU controls whole system；If enabled automatically stressed function, make a mistake spilling
When, NAND control systems are read in from stressed module reads command sequence again, starts to read again, current page data is all read correctly or read
Failure, terminate to read process again, read module again and stressed consequent interruption position is write into register, reads successful parameter again, afterwards CPU
Whole system is controlled to carry out subsequent treatment.
Further, address generation module, the SRAM moulds of the stressed parameter of storage are additionally provided with module as shown in Fig. 2 reading again
Block and order generation module, wherein the SRAM module that parameter is read in storage again is configured by CPU, the effect of module is specific as follows.
Address generation module is connected with NAND controller, for receive by NAND controller be transmitted through come info signals, wrap
Include current page address, the data length that current page needs are read, the data length of success reading（Finger has been buffered to specified caching
The data length in area）And initial address of data buffer area etc.；Address generation module and for export operation page stressedly
Location, the new initial address of data buffer area, remaining data length for needing to read etc..
The SRAM module that parameter is read in storage again accesses configuration by CPU, in initialization, you can writes default parameters, joins
Number is deposited in the form of retry table, and every parameter is deposited by address.Parametric form is provided by flash manufacturers and is defined.SRAM is big
It is small to be determined by actual demand.CPU can update wherein content at any time.
Parameter in the output signal and SRAM of order generation module reception address generation module, refresh command sequence mould
The information such as address, parameter in block relevant position.
Read command sequence block fixation again and house reading flash orders, read flash orders with user-defined microcommand
Form is present.Page address, data length, data buffer storage initial address and read voltage parameter wherein involved by read command etc.
Information, updated by order generation module.
During work, the SRAM of parameter is read in the storage of CPU initial configurations again, command sequence is read in configuration again, configuration NAND controls
Register in system, decide whether to open stressed module.
When stressed module is triggered, the operation for reading module each several part again is：
1. it is currently that so that ECC block are a NAND flash page sector as an example, NAND is controlled when reading flash operations
System processed writes row address (row_addr), the column address (col_ of current page to address generation module
Addr), current page needs sector numbers (sec_cnt), the sector numbers of success reading read（sec_red_cnt）、
Sector sizes（sec_size）And initial address main_data_addr of data buffer area etc..
Stressed the row address and column address of address generation module output current operation page（According to reality
Border service condition calculates, and may also need to the information such as ECC check digit）, data buffer area new initial address（main_data_
addr + sec_size*sec_red_cnt）, remaining sector numbers for needing to read（sec_cnt- sec_red_cnt）Deng.
2. order generation module detects that address generation module output has change, then by the output information of address generation module
Update in command sequence.
3. order generation module detects that CPU have accessed SRAM, then SRAM, undated parameter, writing commands sequence are re-read
In row.Order generation module presses the order of address from low to high, the parameter being successively read in SRAM, therefore the parameter that priority is high
It should be stored in low address.
When stressed module is not triggered, order generation module reads parameter that SRAM lowest address is deposited simultaneously all the time
In writing commands sequence.When stressed module is not triggered, CPU can read result again according to last time, select optimized parameter, with
Shi Gengxin SRAM.Parameter in order generation module real-time update command sequence, prepared to read again next time.
In this method, realize that automatically stressed step is：
1. CPU opens stressed function automatically in a register.
2. being currently read operation, make a mistake spilling, starts and reads again.NAND control systems carry out warm reset, and operation includes
Empty command queue（If there is a plurality of order in command queue, the order of the current spilling that makes a mistake only is removed）, NAND control
Device returns to IDLE state, internal system caching empties.NAND control systems read in institute from the command sequence in stressed module
There is command sequence and perform.
3. reading module again detects that NAND control systems have accessed stressed command sequence, Article 2 parameter is read from SRAM,
Update command sequence.
4. the signal that address generation module transmits according to NAND control systems, recalculate the signal of output.Order simultaneously
Generation module detects the exporting change of address generation module, updates the content in command sequence.
5. order generation module detects that the residue of address generation module output needs to read data length when being 0, to reset
SRAM address is read, parameter is read from lowest address, updates command sequence.So far reading again for one page is completed.To interrupt register
Middle write-in, which is read again, successfully to be interrupted, reads successful parameter again.
6. during step 5 is performed, if reading order failure corresponding to first parameter again, make a mistake again
Overflow, repeat step 2-5.Only step 3, Article 3 parameter is read from SRAM successively, until reading the last item.
7. if all parameters do not read the page successfully in SRAM, terminate to read again.Write into interrupt register
Read again and unsuccessfully interrupt, read successful parameter again（Should at when it is invalid）.
When Fig. 3 is reads again automatically, the Parameters variation moment in command sequence.Each NAND control systems, which are read, reads order sequence again
After row, parameter is read in command sequence renewal again, is prepared to read again next time（Or the stressed operation of current page）.Address, reading
Taking the information such as data length is just refreshed after each ECC block are read successfully.At the end of reading again, in command sequence
Stressed parameter writes back optimal value, waits the stressed triggering of lower one page.
Embodiment 2
A kind of device of raising NAND flash reading rates disclosed in the present embodiment, including NAND control systems, NAND controller
Inside is provided with correction module, is provided with NAND control systems by the automatic register for reading enabled order again of CPU configurations, correction module
The input of logic and operation device is connected to the output end of register, the output end of logic and operation device is connected to selector,
In one stressed module of NAND control systems periphery addition, read again to set in module and read command sequence again, read command sequence warp again
Selector is connected to NAND controller.
Further, the stressed module also includes address generation module, order generation module and SRAM module, address life
Input into module is connected with NAND controller, the info signals come for receiving NAND controller to be transmitted through；Order generation mould
The input of block is connected with the output end of address generation module, for receiving the address parameter of address generation module output；Read again
Deposited in command sequence and read order again, and the input for reading command sequence again is connected with the output end of order generation module, uses
The information for reading order again is updated in receiving, the output end connection NAND controller of command sequence is read again, for NAND controller
Command sequence is read in output again；SRAM module accesses configuration by CPU and reads parameter again, and the output end of SRAM module generates with order
Module is connected, and parameter is read again for being transmitted to order generation module.
Described above is only that the general principle of the present invention and preferred embodiment, those skilled in the art do according to the present invention
The improvement and replacement gone out, belongs to protection scope of the present invention.
Claims (10)
- A kind of 1. method of raising NAND flash reading rates, it is characterised in that：Realized by following system, the system includes NAND control systems and stressed module, NAND control systems include NAND controller and register, set and entangle in NAND controller Mismatch block, to read again and read command sequence built in module again, correction module and register are connected to selector by logic and operation device, Read module again and NAND controller is connected to by selector；During work, by CPU configuration registers, decide whether enabled automatic weight Read function；If do not enabled, it is not turned on reading module again；Correction module make a mistake spilling when, produce interruption, controlled by CPU Whole system re-writes new order to register；If enabled automatically stressed function, during the spilling that makes a mistake, NAND controls System is read in from stressed module reads command sequence again, starts to read again, and current page data is all read correctly or reading failure, terminates weight Read procedure, read module again and stressed consequent interruption position is write into register, reads successful parameter again, the whole system of CPU controls afterwards System carries out subsequent treatment.
- 2. the method for raising NAND flash reading rates according to claim 1, it is characterised in that：The stressed module is also Including address generation module, order generation module and SRAM module, the input of address generation module is connected with NAND controller, The info signals come for receiving NAND controller to be transmitted through；The input of order generation module and the output end of address generation module It is connected, for receiving the address parameter of address generation module output；Read again to deposit in command sequence and read order again, and read life again Make the input of sequence be connected with the output end of order generation module, update the information for reading order again for receiving, read order again The output end connection NAND controller of sequence, command sequence is read again for being exported to NAND controller；SRAM module is accessed by CPU Parameter is read in configuration again, and the output end of SRAM module is connected with order generation module, for transmitting weight to order generation module Read parameter.
- 3. the method for raising NAND flash reading rates according to claim 2, it is characterised in that：During work, CPU is initial Change configuration storage to read the SRAM of parameter again, configure the register read again in command sequence, configuration NAND control systems, decide whether Open and read module again；When stressed module is opened, the operation for reading module each several part again is：1st, address generation module receives NAND controls Current page address, the current page of device write-in processed need data length, the data length and data buffer storage of success reading read The initial address in area；Then the stressed address of address generation module output current operation page, the new initial address of address cache The data length read with remaining needs；2nd, order generation module detects that address generation module output has change, then gives birth to address Output information into module is updated into command sequence；3rd, order generation module detects that CPU have accessed SRAM, then re-reads SRAM, undated parameter, in writing commands sequence.
- 4. the method for raising NAND flash reading rates according to claim 3, it is characterised in that：Order generation module is pressed The order of address from low to high, the parameter being successively read in SRAM.
- 5. the method for raising NAND flash reading rates according to claim 3, it is characterised in that：Stressed module is not opened Qi Shi, order generation module are read in the parameter that SRAM lowest address is deposited and writing commands sequence all the time；CPU was according to last time Read result again, select optimized parameter, update SRAM at any time, the parameter in order generation module real-time update command sequence, under Secondary read again is prepared.
- 6. the method for raising NAND flash reading rates according to claim 2, it is characterised in that：This method is realized automatic Stressed step is：1st, CPU opens stressed function automatically in a register；2nd, it is currently read operation, make a mistake spilling, starts and reads again, and NAND control systems carry out warm reset, NAND control systems All command sequences are read in from the stressed command sequence in stressed module and are performed；3rd, read module again and detect that NAND control systems have accessed stressed command sequence, Article 2 parameter, renewal are read from SRAM Command sequence；4th, the signal that address generation module transmits according to NAND control systems, the signal of output is recalculated；Order generation simultaneously Module detects the exporting change of address generation module, updates the content in command sequence；5th, order generation module detects that the residue of address generation module output needs to read data length when being 0, to reset and read SRAM address, reads parameter from lowest address, updates command sequence, reading again for one page is so far completed, into interrupt register Write-in, which is read again, successfully to be interrupted, reads successful parameter again；6th, during step 5 is performed, if reading order failure corresponding to first parameter again, make a mistake spilling again, Repeat step 2-5；But when performing step 3, Article 3 parameter is read from SRAM successively, until reading the last item；If the 7, all parameters do not read the page successfully in SRAM, terminate to read again, write and read again into interrupt register Failure is interrupted, reads successful parameter again.
- 7. the method for raising NAND flash reading rates according to claim 6, it is characterised in that：NAND control systems are entered The operation of row warm reset is including emptying command queue, NAND controller returns to IDLE state, internal system caching empties.
- 8. the method for raising NAND flash reading rates according to claim 7, it is characterised in that：Empty command queue When, if there is a plurality of order in command queue, only remove the order that currently transmitted mistake is overflowed.
- A kind of 9. device of raising NAND flash reading rates, it is characterised in that：Including NAND control systems, NAND controller Inside is provided with correction module, is provided with NAND control systems by the automatic register for reading enabled order again of CPU configurations, correction module The input of logic and operation device is connected to the output end of register, the output end of logic and operation device is connected to selector, In one stressed module of NAND control systems periphery addition, read again to set in module and read command sequence again, read command sequence warp again Selector is connected to NAND controller.
- 10. the device of raising NAND flash reading rates according to claim 9, it is characterised in that：The stressed module Also include address generation module, order generation module and SRAM module, input and the NAND controller phase of address generation module Even, the info signals come for receiving NAND controller to be transmitted through；The input of order generation module is defeated with address generation module Go out end to be connected, for receiving the address parameter of address generation module output；Read again to deposit in command sequence and read order again, and again The input of read command sequence is connected with the output end of order generation module, updates the information for reading order again for receiving, reads again The output end connection NAND controller of command sequence, command sequence is read again for being exported to NAND controller；SRAM module is by CPU Access configuration and read parameter again, and the output end of SRAM module is connected with order generation module, for being passed to order generation module Defeated stressed parameter.
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| CN111625194A (en) * | 2020-05-26 | 2020-09-04 | 合肥康芯威存储技术有限公司 | Data reading method of storage medium, storage system and storage device |
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