CN111104050A - OTP (one time programmable) optimized storage structure, storage method, reading method and control chip - Google Patents
OTP (one time programmable) optimized storage structure, storage method, reading method and control chip Download PDFInfo
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- CN111104050A CN111104050A CN201811260946.6A CN201811260946A CN111104050A CN 111104050 A CN111104050 A CN 111104050A CN 201811260946 A CN201811260946 A CN 201811260946A CN 111104050 A CN111104050 A CN 111104050A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
Abstract
The invention discloses an OTP (one time programmable) optimized storage structure, a storage method, a reading method and a control chip, which comprise a storage block, wherein the storage block comprises a data storage block and an address storage block, the data storage block is used for storing an OTP value, the address storage block is used for storing the address of the OTP value needing to be programmed again in the data storage block, and a programming enable bit is set for indicating whether the storage block is programmed or not.
Description
Technical Field
The invention relates to the technical field of OTP (one time programmable) and particularly relates to an OTP optimized storage structure, a storage method, a reading method and a control chip.
Background
OTP (one Time programming) is a type of storage structure of IC, and only supports one-Time programming, once the programming is successful, it cannot be changed and cleared again, and in some cases, if the OTP programming value is burned incorrectly, or the OTP value needs to be updated, the originally programmed IC can only be scrapped, which causes waste. Some ICs adopt 2 times space of OTP memory space, half is used for spare, although can solve the problem like this, reserve one time space, too extravagant, increase cost, and can only satisfy the requirement of writing by burning twice. In most cases, the number of OTP values which need to be modified for burn-in and upgrade is not large, and the problem can be solved by reserving less OTP memory space.
Disclosure of Invention
The invention aims to solve the technical problems of IC scrap waste and high cost caused by two or more times of programming of OTP in the prior art, and provides an OTP optimized storage structure, a storage method, a reading method and a control chip.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows: an OTP optimized memory structure comprises a memory block, wherein the memory block comprises a data memory block and an address memory block, the data memory block is used for storing OTP values, the address memory block is used for storing addresses of the OTP values needing to be burned again in the data memory block, and a burning enable bit is set and used for indicating whether the memory block is burned or not.
Further, the last bit of the address memory block is set as a write enable bit.
Furthermore, the storage space of the data storage block and the storage space of the address storage block are set according to user requirements.
Further, the storage space of the data storage block is larger than that of the address storage block.
A control chip comprises the OTP optimization storage structure, and the control chip comprises an IC chip.
An OTP optimization storage method controls the OTP optimization storage structure, and the method comprises the following steps:
determining the size of the storage space of the OTP storage block, dividing a data storage block and an address storage block according to the size of the storage space, wherein the data storage block stores the OTP value, the address storage block stores the address of the OTP value needing to be programmed again in the data storage block, and a programming enable bit is set,
checking whether the OTP value of the data storage block needs to be programmed again, recording an address corresponding to the OTP value needing to be programmed again, programming the address corresponding to the OTP value needing to be programmed again in the address storage block, and programming the OTP value again in the data storage block;
the value of the write enable bit is changed.
Further, the programming is carried out on the storage area blocks in sequence according to the sequence of the re-programming required.
An OTP storage and reading method controls the OTP optimized storage structure, and the method comprises the following steps:
reading the value of the programming enable bit and judging whether the value is changed;
when the OTP value is changed, reading the address stored in the address memory block and the OTP value stored in the data memory block corresponding to the address;
and replacing the original OTP value of the address with the rewritten OTP value.
Furthermore, the burning enabling bit is sequentially read from the memory block, and when the burning enabling bit is not changed, the reading is stopped.
As can be seen from the above description of the present invention, compared with the prior art, the OTP optimized memory structure, the memory method, the reading method, and the control chip provided in the present invention divide the memory block into the data memory block and the address memory block, where the data memory block stores the OTP value, the address memory block stores the address of the OTP value that needs to be rewritten in the data memory block, and sets the write enable bit to indicate whether the memory block is written, so as to optimize OTP memory, which is simple to implement, improve OTP memory validity, meet the requirement of two or more writes, avoid the IC rejection due to error burning and upgrade to the greatest extent, save OTP memory cost, and reduce IC rejection rate.
Drawings
FIG. 1 is a diagram of a 4Kbit memory architecture;
FIG. 2 is a diagram of an OTP optimized memory architecture of the present invention;
FIG. 3 is a schematic diagram of programming an OTP.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments.
As shown in fig. 1, it is assumed that the IC needs 4Kbit OTP memory space, and the 4Kbit is divided into 128 × 32bit memory structures, and before writing, the OTP values are all 1.
As shown in fig. 2, an OTP optimized memory structure is designed, which includes a memory block, where the memory block includes a data memory block 1 and an address memory block 2, where the data memory block 1 is used to store an OTP value, the address memory block 2 is used to store an address of the OTP value that needs to be rewritten in the data memory block, and a write enable bit is set to indicate whether the memory block is burned, the data memory block is divided into (M × N) bit digital bits, the address memory block is divided into (M × L) bit address memory bits, and a last bit of the address memory bits is set as the write enable bit, in most cases, the number of burned errors and updated OTP values that need to be modified is not large, and it can be considered that less OTP memory space is reserved, therefore, after optimization, the memory space of the data memory block is larger than the memory space of the address memory block, specifically, in order to meet the requirement of secondary or multiple burning, 1Kbit is added as a reserved OTP memory space, namely an optimization mode is used, the OTP memory space is 5Kbit, the OTP memory space of 4Kbit is used as a data memory block, the OTP memory space of 1Kbit is used as an address memory block, each row is 40 bits, wherein bit [39] is burning enabling and represents whether the 40 bits are burned or not, bit [38:32] is an address part, and bit [31:0] is a data part.
A control chip comprises the OTP optimization storage structure, and the control chip comprises an IC chip.
An OTP (one time programmable) optimized storage method for controlling the OTP optimized storage structure comprises the following steps:
s1: determining the size of the storage space of the OTP storage block, dividing a data storage block and an address storage block according to the size of the storage space, wherein the data storage block stores the OTP value, the address storage block stores the address of the OTP value needing to be programmed again in the data storage block, and a programming enable bit is set,
s2: checking whether the OTP value of the data storage block needs to be rewritten, recording an address corresponding to the OTP value needs to be rewritten, rewriting the address corresponding to the OTP value in the address storage block, and rewriting the OTP value in the data storage block, specifically, as shown in fig. 3, assuming that OTP values of 3 addresses, namely 0x00, 0x03, and 0x7E, need to be rewritten for a first programming error or upgrading, and the programming values are 0x55, 0xAA, and 0x5A, respectively. At this time, the first 3 40-bit OTP memory blocks can be programmed in the 1Kbit address memory block, bit [39] writes 0, then [38:32] is the address, which is 0x00, 0x03 and 0x7E respectively, and finally the data is programmed, which is 0x55, 0xAA and 0x5A respectively, assuming that the address is 0x7E and needs the third programming, and the programming value is 0x 3F. At this time, the 4 th 40-bit memory block is used for programming, if the programming needs to be continued, the programming is continued, and the programming of the 40-bit OTP memory block is completed.
An OTP storage reading method for controlling the OTP optimized storage structure comprises the following steps:
s1: reading the value of the programming enable bit, judging whether the value is changed, specifically, scanning a reserved OTP memory block of 1Kbit, checking whether the bit [39] programming enable of every 40 bits is 0, wherein if the bit [39] programming enable is 0, the programming is indicated, and if the bit [39] programming enable is 1, the programming is not indicated;
s2: when the OTP value is changed, reading the address stored in the address memory block and the OTP value stored in the data memory block corresponding to the address;
s3: the original OTP value of the address is replaced by the rewritten OTP value, particularly for the address 0x7E, two and three times of programming are carried out, the data value of the address needs to be replaced twice and must be replaced in sequence, and finally the OTP value of the read address 0x7E is 0x3F, because the programming is carried out in sequence in the 1Kbit address memory block, the scanning can be stopped when the programming enable of bit 39 of 40 bits is scanned to be 1.
As can be seen from the above description of the present invention, compared with the prior art, the OTP optimized memory structure, the memory method, the reading method, and the control chip provided in the present invention divide the memory block into the data memory block and the address memory block, where the data memory block stores the OTP value, the address memory block stores the address of the OTP value that needs to be rewritten in the data memory block, and sets the write enable bit to indicate whether the memory block is written, so as to optimize OTP memory, which is simple to implement, improve OTP memory validity, meet the requirement of two or more writes, avoid the IC rejection due to error burning and upgrade to the greatest extent, save OTP memory cost, and reduce IC rejection rate.
The above description is only a few specific embodiments of the present invention, but the design concept of the present invention is not limited thereto, and any insubstantial modifications made by the design concept should fall within the scope of the present invention.
Claims (9)
1. An OTP optimized memory structure comprising a memory block, characterized in that: the memory blocks comprise a data memory block and an address memory block, the data memory block is used for storing the OTP value, the address memory block is used for storing the address of the OTP value needing to be programmed again in the data memory block, and a programming enable bit is set and used for indicating whether the memory block is programmed or not.
2. An OTP optimized memory architecture according to claim 1, wherein: the last bit of the address memory block is set to the write enable bit.
3. An OTP optimized memory architecture according to claim 1, wherein: and the storage space of the data storage block and the storage space of the address storage block are set by users.
4. An OTP optimized memory architecture according to claim 3, wherein: the storage space of the data storage block is larger than that of the address storage block.
5. A control chip, characterized in that: an OTP optimized memory structure including the structure as claimed in any one of claims 1-4, wherein said control chip includes an IC chip.
6. An OTP optimized memory method for controlling the OTP optimized memory structure of any of claims 1-4, the method comprising:
determining the size of the storage space of the OTP storage block, dividing a data storage block and an address storage block according to the size of the storage space, wherein the data storage block stores the OTP value, the address storage block stores the address of the OTP value needing to be programmed again in the data storage block, and a programming enable bit is set,
checking whether the OTP value of the data storage block needs to be programmed again, recording an address corresponding to the OTP value needing to be programmed again, programming the address corresponding to the OTP value needing to be programmed again in the address storage block, and programming the OTP value again in the data storage block;
the value of the write enable bit is changed.
7. The OTP optimized storage method of claim 6, wherein: and sequentially programming on the storage area blocks according to the sequence of rewriting programming required.
8. An OTP memory read method for controlling the OTP optimized memory structure of any of claims 1-4, the method comprising:
reading the value of the programming enable bit and judging whether the value is changed;
when the OTP value is changed, reading the address stored in the address memory block and the OTP value stored in the data memory block corresponding to the address;
and replacing the original OTP value of the address with the rewritten OTP value.
9. An OTP memory read method according to claim 8, wherein: and sequentially reading the programming enable bit on the memory block, and stopping reading when the programming enable bit is not changed.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117573155A (en) * | 2024-01-16 | 2024-02-20 | 成都电科星拓科技有限公司 | Product information processing method and chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102486937A (en) * | 2010-12-06 | 2012-06-06 | 慧荣科技股份有限公司 | Datum programming circuit for one-time programmable memory and method thereof |
| CN102508732A (en) * | 2011-10-25 | 2012-06-20 | 深圳芯邦科技股份有限公司 | Method and device for improving one-time programmable memory use performance |
| CN104200844A (en) * | 2014-08-27 | 2014-12-10 | 杭州国芯科技股份有限公司 | Method for programming and reading OTP ROM (One Time Programmable Read-Only Memory) with password |
| CN106650510A (en) * | 2016-12-26 | 2017-05-10 | 湖南国科微电子股份有限公司 | OTP memory data protection method and system and OTP controller |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102486937A (en) * | 2010-12-06 | 2012-06-06 | 慧荣科技股份有限公司 | Datum programming circuit for one-time programmable memory and method thereof |
| CN102508732A (en) * | 2011-10-25 | 2012-06-20 | 深圳芯邦科技股份有限公司 | Method and device for improving one-time programmable memory use performance |
| CN104200844A (en) * | 2014-08-27 | 2014-12-10 | 杭州国芯科技股份有限公司 | Method for programming and reading OTP ROM (One Time Programmable Read-Only Memory) with password |
| CN106650510A (en) * | 2016-12-26 | 2017-05-10 | 湖南国科微电子股份有限公司 | OTP memory data protection method and system and OTP controller |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117573155A (en) * | 2024-01-16 | 2024-02-20 | 成都电科星拓科技有限公司 | Product information processing method and chip |
| CN117573155B (en) * | 2024-01-16 | 2024-04-09 | 成都电科星拓科技有限公司 | Product information processing method and chip |
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Effective date of registration: 20201202 Address after: 519070 Guangdong city of Zhuhai Province Qianshan Applicant after: GREE ELECTRIC APPLIANCES Inc. OF ZHUHAI Applicant after: Zhuhai Zero Boundary Integrated Circuit Co.,Ltd. Address before: 519070 Guangdong city of Zhuhai Province Qianshan Applicant before: GREE ELECTRIC APPLIANCES Inc. OF ZHUHAI |
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Application publication date: 20200505 |