CN107404305A - Semiconductor circuit - Google Patents
Semiconductor circuit Download PDFInfo
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- CN107404305A CN107404305A CN201710294806.XA CN201710294806A CN107404305A CN 107404305 A CN107404305 A CN 107404305A CN 201710294806 A CN201710294806 A CN 201710294806A CN 107404305 A CN107404305 A CN 107404305A
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- node
- transistor
- voltage level
- logic level
- clock signal
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
- H03K3/356139—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356026—Bistable circuits using additional transistors in the input circuit with synchronous operation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
A kind of semiconductor circuit includes the first circuit, second circuit, tertiary circuit and the 4th circuit.Voltage level of first circuit based on clock signal, the voltage level of enable signal or the voltage level of scan enable signal determine the value of first node.Voltage level of the second circuit based on first node and clock signal determines the value of section point.Voltage level of the tertiary circuit based on section point determines the value of the 3rd node.4th voltage level of the circuit based on section point and clock signal determines the value of fourth node.Tertiary circuit includes the first transistor and second transistor, and it is serially connected and is strobed into the voltage level of section point to determine the value of the 3rd node.4th circuit includes third transistor, and it is strobed into the voltage level of clock signal to electrically connect the 3rd node and fourth node.
Description
The cross reference of related application
The application of this U.S. Non-provisional Patent requires to be submitted to Korean Intellectual on April 28th, 2016 under 35U.S.C. § 119
The priority of the korean patent application of No. 10-2016-0052148 of property right office, the disclosure of which merge by reference of text
In this.
Technical field
This disclosure relates to semiconductor circuit.
Background technology
It is integrated on a single chip that the miniaturization of technique already leads to more logic circuits.The work(of chip per unit area
Consumption correspondingly gradually increase.Therefore, have become important ask in the electronic equipment using this chip, the problem of heating
Topic.
The trigger of operating circuit is considered the typical element for consuming a large amount of power in the electronic device, even if working as
It is also such during by clock gate to operation circuit offer signal clock.Reduce this element and the overall work being integrated on chip
Making the power consumption of circuit has become extremely important.
The content of the invention
According to an aspect of this disclosure, there is provided a kind of semiconductor circuit, wherein improving reliability, speed is improved,
Reduce power consumption simultaneously.
According to another aspect of the present disclosure, a kind of semiconductor circuit includes the first circuit, second circuit, tertiary circuit and the
Four circuits.The voltage level of voltage level and enable signal of first circuit based on clock signal or scan enable signal
Voltage level, determine the value of first node.Voltage level of the second circuit based on first node and clock signal determines the second section
The value of point.Voltage level of the tertiary circuit based on section point determines the value of the 3rd node.4th circuit be based on section point and
The voltage level of clock signal determines the value of fourth node.Tertiary circuit includes being serially connected and being strobed into section point
Voltage level to determine the first transistor and second transistor of the value of the 3rd node.4th circuit includes being strobed into clock
The voltage level of signal is to electrically connect the third transistor (N6) of the 3rd node and fourth node.
According to another aspect of the present disclosure, a kind of semiconductor circuit includes first node, section point, the 3rd node and the
Four nodes.When clock signal is in the first logic level, first node have make with the logic level of enable signal or scanning
Can signal the different logic level values of logic level.In section point, when clock signal is in the first logic level, by
The logic level of first node determines the value of section point, and when clock signal is in the second logic level, second section
The value of point is maintained by the logic level of the 3rd node.In the 3rd node, the 3rd node is determined by the logic level of section point
Value.In fourth node, when clock signal is in the second logic level, Section four is determined by the logic level of section point
The value of point.Fourth node is discharged by the first transistor and second transistor, and the first transistor is strobed into section point
Voltage level to provide ground voltage to fourth node, the second transistor is strobed into the voltage level of clock signal, with
Electrically connect the 3rd node and fourth node.
According to another aspect of the present disclosure, a kind of semiconductor circuit includes the first gate, the second gate, first crystal
Pipe and second transistor and the 3rd gate.First gate receives clock signal and enable signal or the enabled letter of scanning
Number input, and perform the first logical operation so that the first output signal is output into first node.Second gate receives the
The input of the signal of first output signal of one gate, clock signal and the 3rd node, and perform the second logical operation with
Second output signal is output to section point.It is second defeated to be strobed into the second gate for the first transistor and second transistor
Go out the voltage level of signal, and be serially connected to determine the value of the 3rd node.3rd gate receives the second gate
The second output signal and clock signal input, and perform the 3rd logical operation so that the 3rd output signal is output into Section four
Point.Third transistor is strobed into the voltage level of clock signal, to electrically connect the 3rd node and fourth node.
However, aspect described in this paper is not limited in terms of the disclosure.By reference to detailed description given below, sheet
It is will be apparent in terms of disclosed above and other for disclosure those of ordinary skill in the art.
Brief description of the drawings
The exemplary embodiment of the disclosure, the above and other aspect and feature of the disclosure are described in detail by referring to accompanying drawing
It will be apparent, in accompanying drawing：
Fig. 1 is the circuit diagram for illustrating semiconductor circuit in accordance with an embodiment of the present disclosure；
Fig. 2 and Fig. 3 is the timing diagram for illustrating the operation of semiconductor circuit in accordance with an embodiment of the present disclosure；
Fig. 4 to Fig. 7 is the circuit diagram for illustrating the operation of semiconductor circuit in accordance with an embodiment of the present disclosure；
Fig. 8 is the circuit diagram for illustrating the semiconductor circuit of another embodiment of the present invention.
Fig. 9 to Figure 12 is the circuit diagram for illustrating the operation of the semiconductor circuit according to another embodiment of the present disclosure；
Figure 13 is the block diagram for including the SoC systems including semiconductor circuit in accordance with an embodiment of the present disclosure；
Figure 14 is the block diagram for including the electronic system including semiconductor circuit in accordance with an embodiment of the present disclosure；And
Figure 15 to Figure 17 is the exemplary semiconductor being applied to according to the semiconductor circuit of some embodiments of the present disclosure
System.
Embodiment
Embodiment will be described in detail with reference to the attached drawings.However, concept described herein can be implemented in the form of a variety of,
And it should not be construed as limited to shown embodiment.Conversely, there is provided these embodiments will be as an example, so that the disclosure will be
It is thoroughly and complete, and will fully pass on concepts described herein to those skilled in the art.Accordingly, with respect to the disclosure
Some embodiments, known processing, element and technology are not described.Unless otherwise indicated, in all drawing and description,
Identical reference represents identical element, therefore is not repeated to describe.In the accompanying drawings, for the sake of clarity, layer and region
Size and relative size may be exaggerated.
It will be understood that although term " first ", " second ", " the 3rd " etc. may be used herein describe various elements, component,
Region, layer and/or part, but these elements, component, region, layer and/or part should not be limited by these terms.These
Term is only used for distinguishing an element, component, region, layer or part and another region, layer or part.Therefore, not
In the case of the teaching for departing from the disclosure, the first element, component, region, layer or part discussed below can be referred to as second
Element, component, region, layer or part.
Herein can use " following ", " under ", " being less than ", " following ", " above ", " more than " etc. space phase
To term, in order to describe an element as depicted or feature and another element or the relation of feature.It will be understood that space
Relative terms be intended to including the use of or operation in device the different azimuth in addition to the orientation shown in figure.For example, such as
In fruit figure device upset, then be described as be in other elements or feature " following " or " under " or " following " element thus general
It is oriented in other elements or feature " top ".Therefore, exemplary term " following " and " under " can include above
With following orientation.Device can in addition be oriented and (be rotated by 90 ° or in other orientations), and correspondingly explain used herein
Space relative descriptors.In addition, it will also be understood that when layer be referred to as two layers " between " when, it can be between two layers
Sole layer, or there may also be one or more intermediate layers.
Term as used herein is only used for describing the purpose of specific embodiment, and it is described herein to be not intended to limitation
Concept.As it is used herein, singulative " one ", "one" and "the" are intended to also include plural form, unless context is another
Clearly dictate otherwise.It will also be understood that term " including (comprises) " and/or " including (comprising) " are when in this specification
In in use, specify the feature, entirety, step, operation, the presence of element and/or component, but be not excluded for it is one or more its
Its feature, entirety, step, operation, element, component and/or its presence or addition for combining.As it is used herein, term
"and/or" includes any and all combination of one or more related Listed Items.In addition, term " exemplary " is intended to indicate that and shown
Example or explanation.
It will be understood that when element or layer be referred to as another element or layer " on ", " being connected to ", " being coupled to " or " neighbouring " is another
When one element or layer, it can be connected, couple or adjacent to another element or layer, or can deposit directly on another element or layer
In intermediary element or layer.On the contrary, when element is referred to as " directly on another element or layer ", " being directly connected to ", " direct-coupling
To " or when " close to " another element or layer, in the absence of intermediary element or layer.
Unless otherwise defined, all terms (including technology and scientific terminology) used herein have with the disclosure belonging to neck
The identical implication that the those of ordinary skill in domain is generally understood that.It is also understood that such as defined in usually used dictionary
Those terms should be interpreted as having contain consistent with their implications in the context of correlation technique and/or this specification
Justice, and idealization or excessively formal meaning will not be interpreted, unless clearly so definition herein.
By reference to the features as discussed above of preferred embodiment, the advantages of disclosure can be more easily understood and
Feature and realize disclosed method.
Fig. 1 is the circuit diagram for illustrating semiconductor circuit in accordance with an embodiment of the present disclosure.
With reference to figure 1, semiconductor circuit 1 in accordance with an embodiment of the present disclosure includes the first circuit 10, second circuit the 20, the 3rd
The circuit 40 of circuit 30 and the 4th.In some embodiments of the present disclosure, semiconductor circuit 1 can also include output circuit 50.
The voltage level of voltage level and enable signal E of first circuit 10 based on clock signal CK or scanning are enabled
Signal SE voltage level, determine first node EN value.
Specifically, the first circuit 10 includes transistor P0, P1 and P2.Transistor P0 is strobed into clock signal CK voltage
Level, to provide supply voltage to transistor P1.Transistor P1 is connected in series with transistor P0, and is strobed into the enabled letter of scanning
Number SE voltage level, to provide supply voltage to transistor P2.Transistor P2 is connected in series with transistor P1, and is strobed
To enable signal E voltage level, to provide supply voltage to first node EN.
In addition, the first circuit 10 includes transistor N0 and N1.Transistor N0 is strobed into scan enable signal SE voltage
Level, to provide ground voltage to first node EN.Transistor N1 is strobed into enable signal E voltage level, with to first
Node EN provides ground voltage.
In the present embodiment, transistor P0, P1 and P2 is P-type transistor, and transistor N0 and N1 can be N-type crystal
Pipe.
In the present embodiment, although the first circuit 10 is illustrated as receiving enable signal E and scan enable signal SE input,
But the first circuit 10 can be modified to only receive enable signal E as input or only reception scan enable signal SE as defeated
Enter.Therefore, the first circuit 10 may be provided in the transistor P1 and N0 for the input for only including only receiving scan enable signal SE
(that is, not being P2 or N1) so that transistor P1 is directly connected to first node EN.Or the first circuit 10 can be provided with only
Including the transistor P2 and N1 (that is, not being P1 or N0) of the input for only receiving enable signal E so that transistor P2 is directly connected to
Transistor P0.Such modification is in the limit of power of those of ordinary skill in the art.
Second circuit 20 determines section point FB0 value based on first node EN and clock signal CK voltage level.
Specifically, second circuit 20 includes transistor P3, P4 and P5.Transistor P3 is strobed into clock signal CK voltage
Level, to provide supply voltage to transistor P4.Transistor P5 is connected in parallel with transistor P3, and is strobed into the 3rd node
FB1 voltage level, to provide supply voltage to transistor P4.Transistor P4 and transistor P3 and N2 (explanation below) company of series connection
Connect, and be strobed into first node EN voltage level, to provide supply voltage to section point FB0.
In addition, second circuit 20 includes transistor N2, N3 and N4.Transistor N2 is strobed into first node EN voltage electricity
It is flat, to provide ground voltage to section point FB0.Transistor N4 is strobed into the 3rd node FB1 voltage level, with to transistor
N3 provides ground voltage.Transistor N3 is connected in series with transistor N4, and is strobed into clock signal CK voltage level, with to
Section point FB0 provides ground voltage.
In the present embodiment, transistor P3, P4 and P5 is P-type transistor, and transistor N2, N3 and N4 can be N-types
Transistor.
Voltage level of the tertiary circuit 30 based on section point FB0 determines the 3rd node FB1 value.
Specifically, tertiary circuit 30 includes transistor P6 and N5.Transistor P6 is strobed into section point FB0 voltage electricity
It is flat, to provide supply voltage to the 3rd node FB1.Transistor N5 is also strobed into section point FB0 voltage level, but to
3rd node FB1 provides ground voltage.That is, transistor P6 and N5 are serially connected, with the electricity according to section point FB0
Voltage level determines the 3rd node FB1 value.
In the present embodiment, transistor P6 is P-type transistor, and transistor N5 can be N-type transistor.
4th circuit 40 determines fourth node NECK's based on section point FB0 and clock signal CK voltage level
Value.
Specifically, the 4th circuit 40 includes transistor P7 and P8.Transistor P7 is strobed into section point FB0 voltage electricity
It is flat, to provide supply voltage to fourth node NECK.Transistor P8 is connected in parallel with transistor P7, and is strobed into clock letter
Number CK voltage level, also provide supply voltage to fourth node NECK.
In addition, the 4th circuit 40 includes transistor N6, N7 and N8.Transistor N6 is strobed into clock signal CK voltage electricity
It is flat, to electrically connect the 3rd node FB1 and fourth node NECK.Transistor N8 is strobed into section point FB0 voltage level, with
Ground voltage is provided to transistor N7.Transistor N7 is connected in series with transistor N8, to provide ground voltage to fourth node NECK.
In the present embodiment, transistor P7 and P8 is P-type transistor, and transistor N6, N7 and N8 can be N-type crystal
Pipe.
Depending on the purpose of the semiconductor circuit 1 of the various embodiments for the disclosure, output can be designed as needed
Circuit 50.In the present embodiment, output circuit 50 can include phase inverter G0.Phase inverter G0 receives fourth node NECK voltage
The input of level, and export anti-phase voltage level.
Hereinafter, the logic electricity of the signal specific sent from the semiconductor circuit 1 of the various embodiments according to the disclosure
It is flat to be represented by the first logic level L and/or the second logic level H, or simply represented by L and H.Ordinary skill
Personnel are it will be recognized that the value of the first logic level and the second logic level is not limited to particular value, and can depend on being used for this
The purpose of the semiconductor circuit 1 of disclosed various embodiments and change.That is, the purpose depending on circuit, the first logic
The value of level and the second logic level can be with each in logic low L and logically high H value.First logic level and
The value of two logic levels can also be with each in logically high H and logic low L value.
Fig. 2 and Fig. 3 is the timing diagram for illustrating the operation of semiconductor circuit in accordance with an embodiment of the present disclosure.
With reference to figure 2, semiconductor circuit 1 in accordance with an embodiment of the present disclosure receives clock signal CK input, and depends on
In the clock signal ECK of enable signal E value output gating.
Fig. 2, which is shown, assumes that scan enable signal SE keeps constant, enable signal E value from the in the first logic level L
One logic level L changes into the operation of logic level H semiconductor circuit 1.However, when scan enable signal SE value changes
When, the description of the present embodiment can also be applied similarly to the operation of semiconductor circuit 1.That is, the description of the present embodiment
It can also be applied similarly to assume that enable signal E keeps constant, scan enable signal SE value from the in the first logic level L
One logic level L changes the situation to the second logic level H.Hereinafter, for convenience of description, enable signal will be described mainly
The operation for the semiconductor circuit 1 that E value changes.Will not provide according to similarly operated with enable signal E, depending on scanning make
The repeated description of the operation of the semiconductor circuit 1 of the change of energy signal SE value.
In time T1 and T2, enable signal E corresponds to the first logic level L.First node EN, section point FB0, the 3rd
Node FB1 and fourth node NECK logic level can be each in H, L, H and H respectively.
In time T3 and T4, enable signal E corresponds to the second logic level H.First node EN, section point FB0 and
Three node FB1 logic level can be each in L, H and L respectively.Fourth node NECK logic level can be changed into
It is opposite with clock signal CK logic level.
That is, when enable signal E corresponds to the first logic level L, according to the half of the various embodiments of the disclosure
Conductor circuit 1 by fourth node NECK logic level by maintaining the second logic level H, by the clock signal ECK of gating
Maintain the first logic level L.
When enable signal E corresponds to the second logic level H, when clock signal CK logic level is the first logic level
During L, fourth node NECK logic level is remained within second according to the semiconductor circuit 1 of each embodiment of the disclosure
Logic level H.When enable signal E corresponds to the second logic level H, when clock signal CK logic level is changed into the second logic
During level H, semiconductor circuit 1 by by fourth node NECK logic level transition to the first logic level L, make gating when
Clock signal ECK follows clock signal CK waveform.
With reference to figure 3, semiconductor circuit 1 in accordance with an embodiment of the present disclosure can perform stable clock-gating operation, and
The very big influence for the time that will not be changed by the value of enable signal E during operation.
Fig. 3, which is shown, assumes that scan enable signal SE keeps constant, enable signal E value from the in the first logic level L
One logic level L is changed into the operation of the second logic level H semiconductor circuit 1.However, as above in conjunction with Figure 2, this implementation
Example description can also be applied similarly to assume enable signal E the first logic level L keep it is constant, work as scan enable signal
SE value from the first logic level L be changed into the second logic level H when semiconductor circuit 1 operation.
Reference time T5, when clock signal CK maintains the second logic level H, enable signal E is from the first logic level L
It is converted to the second logic level H.
In this case, the transistor N1 gated by enable signal E voltage level is turned on, and first node EN
Logic level transition be L.
Now, clock signal CK voltage level corresponds to the second logic level H, the 3rd node FB1 voltage level pair
Should be in the second logic level H, and section point FB0 voltage level corresponds to the first logic level L.Made by transistor N3
Turned on to be strobed into the result of clock signal CK voltage level (H), and be used as by transistor N4 and be strobed into
The result of three node FB1 voltage level (H) and turn on, section point FB0 still discharges.As a result, by being strobed into the second section
The transistor P7 of point FB0 voltage level (L), fourth node NECK logic level continuously maintain the second logic level H.
In time T6, when clock signal CK maintains the second logic level H, enable signal E turns from the second logic level H
Change to the first logic level L.
In this case, although the crystal gated by enable signal E voltage level (corresponding to the first logic level L)
Pipe P2 is turned on, but because clock signal CK has the second logic level H value, so transistor P0 is not turned on.Therefore, up to
Before the first logic level L time being converted to clock signal CK from the second logic level H, first node EN logic level
Maintain the first logic level L.
Therefore, the crystalline substance of the conducting of the voltage level (corresponding to the first logic level L) that is strobed into the 3rd node FB1 is passed through
Body pipe P5 and be strobed into first node EN corresponding to the first logic level L voltage level conducting transistor P4,
Section point FB0 still maintains charged state.Second logic level (is corresponded to by the voltage level for being strobed into section point FB0
H transistor N8) and be strobed into clock signal CK voltage level (corresponding to the second logic level L) transistor N7,
Four node NECK logic level remains within the first logic level L.
Stable clock gate can be performed in the foregoing manner according to the semiconductor circuit 1 of each embodiment of the disclosure to grasp
Make.
Hereinafter, the concrete operations of semiconductor circuit 1 will be described with reference to figure 4 to Fig. 7.
Fig. 4 to Fig. 7 is the circuit diagram for illustrating the operation of semiconductor circuit in accordance with an embodiment of the present disclosure.
With reference to figure 4, the first circuit 10 receives clock signal CK, enable signal E or scan enable signal SE (corresponds to first
Logic level L) in the input of each.Hereinafter, Fig. 4 to Fig. 7 mainly describes enable signal E change, for such as Fig. 2 and figure
3 are equally easy to illustrate, it is assumed that scan enable signal SE keeps constant in the first logic level L.
With reference to the first circuit 10, because all transistor P0, P1 and P2 are turned on and transistor N0 and N1 end, institute
There is the second logic level H value with first node EN.
With reference to second circuit 20, because the voltage level that transistor N2 is strobed into first node EN (is patrolled corresponding to second
Collect level H) and turn on, so section point FB0 has the first logic level L value.
With reference to tertiary circuit 30, because the voltage level that transistor P6 is strobed into section point FB0 (is patrolled corresponding to first
Collect level L) and turn on, so the 3rd node FB1 has the second logic level H value.
With reference to the 4th circuit 40, the voltage level that transistor P7 is strobed into section point FB0 (corresponds to the first logic electricity
Flat L) and turn on.Transistor P8 is strobed into clock signal CK voltage level (corresponding to the first logic level L) and led
It is logical.Therefore, fourth node NECK has the second logic level H value.
Next, with reference to figure 5, when enable signal E is in the first logic level L, clock signal CK is electric from the first logic
Flat L is converted to the second logic level H.
With reference to the first circuit 10, both transistor P1 and P2 are still within conducting state, and both transistor N0 and N1
Cut-off state is still within, but transistor P0 ends.Therefore, first node EN is in floating state.
With reference to second circuit 20, transistor N3 is strobed into clock signal CK voltage level, changes now and is patrolled to second
Collect level H and turn on.Transistor N4 is strobed into the voltage electricity of the 3rd node FB1 with the second logic level H in Fig. 4
Put down and turn on.Therefore, section point FB0 maintains the first logic level L value.
With reference to tertiary circuit 30, because the voltage level that transistor P6 is strobed into section point FB0 (is patrolled corresponding to first
Collect level L) and conducting state is maintained, so the 3rd node FB1 maintains the second logic level H value.
That is, as shown in figure 4, when clock signal CK is in the first logic level L, section point FB0 value by
It is strobed into voltage level (that is, the level of the ground voltage) determination that the transistor N2 of first node EN voltage level is provided.3rd
Node FB1 value can be determined by section point FB0 voltage level.In other words, when clock signal CK is in the first logic
During level L, section point FB0 value is determined by first node EN voltage level, and the 3rd node FB1 value can be by
Two node FB0 voltage level determines.When clock signal CK is converted to the second logic level H from the first logic level L, second
Node FB0 value is remained unchanged by the 3rd node FB1 level voltage.3rd node FB1 value can pass through section point
FB0 voltage level remains unchanged.
With reference to the 4th circuit 40, because the voltage level that transistor P7 is strobed into section point FB0 (is patrolled corresponding to first
Collect level L) and conducting state is maintained, so fourth node NECK maintains the second logic level H value.
Next, with reference to figure 6, the first circuit 10 receives clock signal CK (corresponding to the first logic level L) and enabled letter
Number E (corresponding to the second logic level H) input.
With reference to the first circuit 10, because transistor P2 ends and transistor N1 is turned on, first node EN passes through crystalline substance
Body pipe N1 discharges, and the value with the first logic level L.
With reference to second circuit 20, the voltage level that transistor P3 is strobed into clock signal CK (corresponds to the first logic electricity
Flat L) and turn on.Transistor P4 is strobed into first node EN voltage level (corresponding to the first logic level L) and led
It is logical.Therefore, section point FB0 has the second logic level H value.
With reference to tertiary circuit 30, because the voltage level that transistor N5 is strobed into section point FB0 (is patrolled corresponding to second
Collect level H) and turn on, so the 3rd node FB1 is discharged by transistor N5 and transistor N1, and with the first logic electricity
Flat L value.
With reference to the 4th circuit 40, the voltage level that transistor P8 is strobed into clock signal CK (corresponds to the first logic electricity
Flat L) and turn on, fourth node NECK has the second logic level H value.
Next, with reference to figure 7, when enable signal E is in the second logic level H, clock signal CK is electric from the first logic
Flat L is converted to the second logic level H.
With reference to the first circuit 10, because transistor P2 is still within cut-off state and transistor N1 is still within turning on shape
State, so first node EN is discharged by transistor N1, and the value with the first logic level L.
With reference to second circuit 20, transistor P5 has the first logic level L the 3rd node by being strobed into Fig. 6
FB1 voltage level and turn on.Transistor P4 (corresponds to the first logic electricity by being strobed into first node EN voltage level
Flat L) and turn on.Therefore, section point FB0 maintains the second logic level H value.
With reference to tertiary circuit 30, because the voltage level that transistor N5 is strobed into section point FB0 (is patrolled corresponding to second
Collect level H) and conducting state is maintained, so the 3rd node FB1 is discharged by transistor N5 and transistor N1, and maintain first to patrol
Collect level L value.
That is, as shown in fig. 6, when clock signal CK is in the first logic level L, section point FB0 value by
(being strobed into clock signal CK voltage level) transistor P3 and (being strobed into first node EN voltage level) transistor
The voltage level (that is, the level of supply voltage) that P4 is provided determines.3rd node FB1 value can be by section point FB0 electricity
Voltage level determines.In other words, when clock signal CK is in the first logic level L, section point FB0 value is by first node
EN voltage level is determined, and the 3rd node FB1 value can be determined by section point FB0 voltage level.Now, at that time
Clock signal CK from the first logic level L be converted to the second logic level H when, section point FB0 value by the 3rd node FB1 electricity
Voltage level is remained unchanged, and the 3rd node FB1 value can be remained unchanged by section point FB0 voltage level.
With reference to the 4th circuit 40, the voltage level that transistor N8 is strobed into section point FB0 (corresponds to the second logic electricity
Flat H) and turn on.Transistor N7 is strobed into clock signal CK voltage level (corresponding to the second logic level H) and led
It is logical.Therefore, fourth node NECK is discharged by transistor N7 and N8, and the value with the first logic level L.
Here, it is noted that fourth node NECK discharges also by transistor N6, transistor N5 and transistor N1.Reason is brilliant
Body pipe N6 is strobed into clock signal CK voltage level (corresponding to the second logic level H) and turned on, with electrical connection the 3rd
Node FB1 and fourth node NECK.In other words, fourth node NECK can also pass through the 3rd node FB1 and first node EN
Electric discharge.
When fourth node NECK is discharged by two paths, the service speed of semiconductor circuit 1 can be significantly improved.Change
Sentence is talked about, fourth node NECK by the 3rd node FB1 and first node the EN path discharged be changed into allowing enable signal E (or
Scan enable signal SE) input data via first node EN, the 3rd node FB1 and fourth node NECK fast propagations to section
Point ECK path.
In addition, it is also noted that fourth node NECK electric discharge after, when enable signal E is changed into from the second logic level H
During the first logic level L, fourth node NECK does not influence the operation of semiconductor circuit 1.After fourth node NECK electric discharges, i.e.,
Make enable signal E be converted to the first logic level L and transistor N1 from the second logic level H to end, first node EN also may be used
To maintain the state discharged by the path formed by transistor N5, N6, N7 and N8, transistor N5, N6, N7 and N8 are turned on simultaneously
And it is electrically connected to each other.
Fig. 8 is the circuit diagram for illustrating the semiconductor circuit according to another embodiment of the present disclosure.
With reference to figure 8, the first gate G1, the second logic are included according to the semiconductor circuit 2 of another embodiment of the present disclosure
Door G2, the 3rd gate G3 and transistor P6, N5 and N6.In some embodiments of the present disclosure, semiconductor circuit 2 can be with
Including phase inverter G0, it receives the input of fourth node NECK voltage level, and exports anti-phase voltage level.
First gate G1 receives clock signal CK, enable signal E or scan enable signal SE input.First gate
G1 performs the first logical operation so that output signal is output into first node EN.
Although the first gate G1 is represented by 3 input NOR gates in fig. 8, the scope of the present disclosure not limited to this.
Clock signal CK, enable signal E or scan enable signal SE are performed that is, the first gate G1 may be provided in
Any type of gate of NOR logical operations.
Second gate G2 receives the first gate G1 the first output signal, clock signal CK and the 3rd node FB1's
The input of signal, and the second logical operation is performed so that the second output signal is output into section point FB0.
Specifically, the second gate G2 includes AND-NOR compound logic doors.Second logical operation can include believing clock
The AND logical operations of number CK and the 3rd node FB1 signal and the first output signal and the result of AND logical operations are believed
Number NOR logical operations.
3rd gate G3 receives the second gate G2 the second output signal and clock signal CK input.3rd logic
Door G3 performs the 3rd logical operation so that output signal is output into fourth node NECK.
Specifically, the 3rd gate G3 includes NAND gate.3rd logical operation can include the second output signal and
Clock signal CK NAND logic computing.
Transistor P6 is strobed into the voltage level of the second output signal, and supply voltage is supplied into the 3rd node FB1.
Transistor N5 is strobed into the voltage level of the second output signal, to provide ground voltage to the 3rd node FB1.It is that is, brilliant
Body pipe P6 and N5 are serially connected, to determine the 3rd node FB1 value according to the voltage level of the second output signal.
Transistor N6 is strobed into clock signal CK voltage level, to electrically connect the 3rd node FB1 and fourth node
NECK。
In the present embodiment, transistor P6 is P-type transistor, and transistor N5 and N6 can be N-type transistors.
Hereinafter, reference picture 9 to Figure 12 is described to the concrete operations of semiconductor circuit 2.
Fig. 9 to Figure 12 is the circuit diagram for illustrating the operation of the semiconductor circuit according to another embodiment of the present disclosure.
First gate G1 receives clock signal CK, enable signal E or scan enable signal SE (corresponds to the first logic electricity
Flat L) in the input of each.Hereinafter, Fig. 9 to 12 mainly describes enable signal E change, false with Fig. 2 and Fig. 3
If scan enable signal SE is in the first constant logic level L, to facilitate explanation.
In fig.9, the first gate G1 is in clock signal CK and enable signal E (corresponding to the first logic level L)
Each performs NOR logical operations.First output signal (corresponding to the second logic level H) is output to by the first gate G1
One node EN.Therefore, first node EN has the second logic level H value.
Second gate G2 performs AND logics to the first logic level L clock signal CK and the 3rd node FB1 signal
Computing.Second gate G2 performs NOR logical operations to the consequential signal of AND logical operations and the first output signal.However, by
There is second logic level H value in the first output signal, so no matter the logic level of the consequential signal of AND logical operations
How is value, and the second gate G2 exports the second output signal (corresponding to the first logic level L) and arrives section point FB0.Therefore,
Two node FB0 have the first logic level L value.
Transistor N5 and P6 can correspond to the tertiary circuit 30 of preceding embodiment.Because tertiary circuit 30 is strobed into
Two node FB0 voltage level (corresponding to the first logic level L) and turn on, so the 3rd node FB1 has the second logic
Level H value.
3rd gate G3 can be believed the first logic level L the second output signal and the first logic level L clock
Number CK performs NAND operations.3rd gate G3 exports the 3rd output signal (corresponding to the second logic level H) and arrives fourth node
NECK.Therefore, fourth node NECK has the second logic level H value.
Next, with reference to figure 10, when enable signal E is in the first logic level L, clock signal CK is electric from the first logic
Flat L is converted to the second logic level H.
First gate G1 (patrols clock signal CK (corresponding to the second logic level H) and enable signal E corresponding to first
Collect level L) perform NOR logical operations.First output signal (corresponding to the first logic level L) is output to by the first gate G1
First node EN.Therefore, first node EN has the first logic level L value.
Second gate G2 to the second logic level H clock signal CK and in fig.9 with the second logic level H the
Three node FB1 signal performs AND logical operations.Second gate G2 exports to the consequential signal of AND logical operations and first
Signal (corresponding to the first logic level L) performs NOR logical operations.As a result, the second gate G2 is (corresponding by the second output signal
In the first logic level L) it is output to section point FB0.Therefore, section point FB0 maintains the first logic level L value.
Transistor N5 and P6 can correspond to the tertiary circuit 30 of preceding embodiment.With reference to tertiary circuit 30, due to the 3rd
The transistor P6 of circuit 30 is strobed into section point FB0 voltage level (corresponding to the first logic level L) and maintains to turn on
State, so the 3rd node FB1 maintains the value of the second logic level.
That is, when clock signal CK is converted to the second logic level H from the first logic level L, section point FB0
Value remained unchanged by the 3rd node FB1 voltage level.3rd node FB1 value can be by section point FB0 voltage electricity
It is flat to remain unchanged.
3rd gate G3 is to the first logic level L the second output signal and the second logic level H clock signal CK
Perform NAND operation.3rd gate G3 exports the 3rd output signal (corresponding to the second logic level H) and arrives fourth node NECK.
Therefore, fourth node NECK maintains the second logic level H value.
Next, with reference to figure 11, the first gate G1 receives clock signal CK (corresponding to the first logic level L) and enabled
Signal E (corresponding to the second logic level H) input.
First gate G1 (patrols enable signal E (corresponding to the second logic level H) and clock signal CK corresponding to first
Collect level L) perform NOR logical operations.First output signal (corresponding to the first logic level L) is output to by the first gate G1
First node EN.Therefore, first node EN has the first logic level L value.
Second gate G2 performs AND logics to the first logic level L clock signal CK and the 3rd node FB1 signal
Computing.Second gate G2 performs NOR logical operations to the consequential signal of AND logical operations and the first output signal.However, by
There is the first logic level L value in clock signal CK, therefore the consequential signal of AND logical operations has the first logic level L
Value.Therefore, the second gate G2 exports the second output signal (corresponding to the second logic level H) to section point FB0.Cause
This, section point FB0 has the second logic level H value.
As described above, transistor N5 and P6 can correspond to the tertiary circuit 30 of more early embodiment.With reference to tertiary circuit 30,
Because the transistor N5 of tertiary circuit 30 is strobed into section point FB0 voltage level (corresponding to the second logic level H) simultaneously
And turn on, so the 3rd node FB1 has the first logic level L value.
3rd gate G3 is to the second logic level H the second output signal and the first logic level L clock signal CK
Perform NAND operation.3rd gate G3 exports the 3rd output signal (corresponding to the second logic level H) and arrives fourth node NECK.
Therefore, fourth node NECK has the second logic level H value.
Next, with reference to figure 12, when enable signal E is in the second logic level H, clock signal CK is electric from the first logic
Flat L is converted to the second logic level H.
First gate G1 (patrols clock signal CK (corresponding to the second logic level H) and enable signal E corresponding to second
Volume level H) in each perform NOR logical operations.First output signal (is corresponded to the first logic electricity by the first gate G1
Flat L) it is output to first node EN.Therefore, first node EN has the first logic level L value.
Second gate G2 has had first to patrol to clock signal CK (corresponding to the second logic level H) and in fig. 11
The signal for collecting level L the 3rd node FB1 performs AND logical operations.Consequential signals of the second gate G2 to AND logical operations
NOR logical operations are performed with the first output signal (corresponding to the first logic level L).As a result, the second gate G2 is defeated by second
Go out signal (corresponding to the second logic level H) and be output to section point FB0.Therefore, section point FB0 maintains the second logic level
H value.
As described above, transistor N5 and P6 can correspond to the tertiary circuit 30 of more early embodiment.With reference to tertiary circuit 30,
Because the transistor N5 of tertiary circuit 30 is strobed into section point FB0 voltage level (corresponding to the second logic level H) simultaneously
Conducting state is maintained, so the 3rd node FB1 maintains the first logic level L value.
That is, when clock signal CK is converted to the second logic level H from the first logic level L, section point FB0
Value remained unchanged by the 3rd node FB1 voltage level.3rd node FB1 value can be by section point FB0 voltage electricity
It is flat to remain unchanged.
3rd gate G3 is to the second logic level H the second output signal and the second logic level H clock signal CK
Perform NAND operation.3rd gate G3 exports the 3rd output signal (corresponding to the first logic level L) and arrives fourth node NECK.
Therefore, fourth node NECK has the first logic level L value.
Here, it is noted that fourth node NECK discharges also by transistor N6 and transistor N5.Reason is that transistor N6 is chosen
Lead to clock signal CK voltage level (corresponding to the second logic level H), and be switched on electrically connect the 3rd node FB1 and
Fourth node NECK.In other words, fourth node NECK can also be discharged by the 3rd node FB1 and first node EN.
, can be with the significant each embodiment improved according to the disclosure when fourth node NECK is discharged by the two paths
Semiconductor circuit 2 service speed.In other words, fourth node NECK is discharged by the 3rd node FB1 and first node EN
Path be changed into allow enable signal E (or scan enable signal SE) input data via first node EN, the 3rd node FB1
With fourth node NECK fast propagations to node ECK path.
Above-mentioned semiconductor circuit 1 and 2 can also be described as including with lower node.
Semiconductor circuit 1 and 2 includes first node EN, section point FB0, the 3rd node FB1 and fourth node NECK.When
When clock signal CK is in the first logic level L, first node EN has the logic with enable signal E or scan enable signal SE
The different logic level values of level.Section point FB0 has when clock signal CK is in the first logic level L by first node
EN logic level is determined and determined when clock signal CK is in the second logic level H by the 3rd node FB1 logic level
Value.3rd node FB1 has the value determined by section point FB0 logic level.When clock signal CK is in the second logic
During level H, fourth node NECK has the value determined by section point FB0 logic level.
Here, fourth node NECK can be discharged by transistor N5 and transistor N6.Transistor N5 is strobed into second
Node FB0 voltage level, to provide ground voltage to fourth node NECK.Transistor N6 is strobed into clock signal CK voltage
Level, to electrically connect the 3rd node FB1 and fourth node NECK.
When enable signal E or scan enable signal SE is in the first logic level L, section point FB0 can have the
One logic level L, and the 3rd node FB1 can have the second logic level H.In addition, fourth node NECK can have the
Two logic level H.This is described in such as Fig. 9 and Figure 10 embodiment.
When enable signal E or scan enable signal SE is in the second logic level H, section point FB0 can have the
Two logic level H, and the 3rd node FB1 can have the first logic level L.Here, the 3rd node FB1 can pass through first
Node EN discharges.In addition, as shown in Figure 11 embodiment, when clock signal CK is in the first logic level L, fourth node
NECK can have the second logic level H.As shown in the embodiment of fig. 12, when clock signal CK is in the second logic level H,
Fourth node NECK can have the first logic level L.Here, when clock signal CK is in the second logic level H, Section four
Point NECK can be discharged by transistor N6, the 3rd node FB1 and first node EN.
Figure 13 is the block diagram of the system for the on-chip system (SoC) for including semiconductor circuit in accordance with an embodiment of the present disclosure.
With reference to figure 13, SoC systems 1000 include application processor 1001 and DRAM 1060.
Application processor 1001 can include CPU 1010, multimedia system 1020, bus 1030, memory
System 1040 and peripheral circuit 1050.
CPU 1010 can perform the operation needed for driving SoC systems 1000.In some implementations of the disclosure
In example, CPU 1010 can be configured as the multi-core environment for including multiple cores.
Multimedia system 1020 can be used in SoC systems 1000 performing various multimedia functions.Multimedia system
1020 can include 3D engine modules, Video Codec, display system, camera system, preprocessor etc..
Bus 1030 can be used for CPU 1010, multimedia system 1020, accumulator system 1040 and periphery
Data communication between circuit 1050.In some embodiments of the present disclosure, bus 1030 can have sandwich construction.Specifically
Ground, bus 1030 can be but not limited to multilayer Advanced High-Performance Bus (AHB) or multilayer Advanced extensible Interface (AXI).
Accumulator system 1040 can provide application processor 1001 and be connected to external memory storage (for example, DRAM 1060)
And the environment needed for high speed operation.In some embodiments of the present disclosure, it is outside that accumulator system 1040 can include control
Single controller (for example, dram controller) needed for memory (for example, DRAM 1060).
Peripheral circuit 1050 can provide SoC systems 1000 and be smoothly connected to ring needed for external equipment (for example, mainboard)
Border.Therefore, peripheral circuit 1050 can include enabling the external equipment and SoC systems 1000 that are connected to SoC systems 1000
Compatible various interfaces.
DRAM 1060 may be used as the operation memory needed for the operation of application processor 1001.In some of the disclosure
In embodiment, DRAM 1060 can be placed on outside application processor 1001.Specifically, DRAM 1060 can be handled with application
Device 1001 encapsulates in the form of packaging body lamination (package on package, PoP).
Any one in semiconductor circuit according to above-described embodiment of the disclosure can be provided as SoC systems 1000
It is at least one in element.
Figure 14 is the block diagram for the electronic system for showing to include semiconductor circuit in accordance with an embodiment of the present disclosure.
With reference to figure 14, electronic system 1100 in accordance with an embodiment of the present disclosure can include controller 1110, input/output
(I/O) equipment 1120, memory devices 1130, interface 1140 and bus 1150.Controller 1110, I/O equipment 1120, memory
Equipment 1130 and/or interface 1140 can be connected to each other by bus 1150.Bus 1150 is used as being used for the path for sending data.
Controller 1110 can include microprocessor, digital signal processor, microcontroller and be able to carry out and microprocessor
It is at least one in the logical device of device, the digital signal processor function similar with microcontroller.I/O equipment 1120 can wrap
Include keypad, keyboard and display device.Memory devices 1130 can be with data storage and/or order.Interface 1140 can be used for
Communication network sends data or receives data from communication network.Interface 1140 can be wired or wireless interface.In this example, connect
Mouth 1140 can include antenna or wired or wireless transceiver.
Although not shown in figure, electronic system 1100 can be the operation for improving the operation of controller 1110
Memory, and high-speed DRAM or SRAM can also be included.
Electronic system 1100 can be applied to personal digital assistant (PDA), portable computer, web tablet, wireless
Phone, mobile phone, digital music player, storage card can be sent or receive information is all types of in wireless environments
Electronic product.
At least one in the element of electronic system 1100 can use according to above-described embodiment of the disclosure half
It is at least one in conductor circuit.
Figure 15 to Figure 17 is the semiconductor system for showing to apply the semiconductor circuit according to some embodiments of the present disclosure
The figure of the example of system.
Figure 15 shows tablet PC 1200, and Figure 16 shows notebook 1300, and Figure 17 shows smart phone
1400.In semiconductor circuit in accordance with an embodiment of the present disclosure it is at least one can be used in tablet PC 1200, notebook calculate
In machine 1300 and smart phone 1400.
In addition, it would be recognized by those skilled in the art that the semiconductor circuit of some embodiments of the present disclosure can also be applied
In except other IC devices set forth herein in addition to those.Although that is, it is described above as according to this reality
Tablet PC 1200, notebook 1300 and the smart phone 1400 of the example of the semiconductor system of example are applied, but according to this
The example of the semiconductor system of embodiment is not limited to tablet PC 1200, notebook 1300 and smart phone 1400.At this
In some disclosed embodiments, semiconductor system may be provided in computer, super mobile PC (UMPC), work station, net book meter
Calculation machine, personal digital assistant (PDA), portable computer, radio telephone, mobile phone, e-book, portable multimedia broadcasting are put
Device (PMP), portable game machine, navigation equipment, black box, digital camera, three-dimensional television, digital audio recorder, numeral
Audio player, digital image recorder, digital image player, digital video recorder, video frequency player etc..
Although specifically illustrating and describing semiconductor circuit described herein with reference to the exemplary embodiment of the present invention,
But it will be appreciated by the skilled addressee that spirit and scope of the present disclosure are not defined by the appended claims being departed from
In the case of, various changes can be carried out in form and details.Exemplary embodiment should be to be considered merely as descriptive, without
It is the purpose for limitation.
Claims (20)
1. a kind of semiconductor circuit, including：
First circuit, the voltage level of its voltage level and enable signal based on clock signal or scan enable signal
Voltage level, determine the value of first node；
The voltage level of second circuit, its voltage level based on the first node and the clock signal determines section point
Value；
Tertiary circuit, its voltage level based on the section point determine the value of the 3rd node；And
4th circuit, its voltage level based on the section point and the clock signal determine the value of fourth node,
Wherein, the tertiary circuit includes the first transistor and second transistor, the first transistor and second transistor that
This is connected in series and is strobed into the voltage level of the section point, to determine the value of the 3rd node, and
Wherein, the 4th circuit includes third transistor, and it is strobed into the voltage level of the clock signal, with electrical connection
3rd node and the fourth node.
2. semiconductor circuit according to claim 1,
Wherein, first circuit includes the 4th transistor, the 5th transistor and the 6th transistor, the 4th transistor
The voltage level of the clock signal is strobed into provide supply voltage, the 4th strings of transistors described in the 5th transistor AND gate
Connection is connected and is strobed into the voltage level of the enable signal, and supply voltage is supplied into first node, and the described 6th
Transistor is strobed into the voltage level of enable signal, to provide ground voltage to first node.
3. semiconductor circuit according to claim 1,
Wherein, first circuit also includes the 4th transistor, the 5th transistor and the 6th transistor, the 4th crystal
Pipe is strobed into the voltage level of the clock signal to provide supply voltage, the 4th transistor described in the 5th transistor AND gate
It is connected in series and is strobed into the voltage level of the scan enable signal, provides the power supply electricity to the first node
Pressure, the 6th transistor are strobed into the voltage level of the scan enable signal, to provide ground electricity to the first node
Pressure.
4. semiconductor circuit according to claim 1,
Wherein, the second circuit includes：4th transistor, it is strobed into the voltage level of the clock signal to provide electricity
Source voltage；5th transistor, it is connected with the 4th coupled in parallel and is strobed into the voltage electricity of the 3rd node
It is flat, to provide the supply voltage；6th transistor, it is connected in series with the 4th transistor and the 5th transistor,
And the voltage level of the first node is strobed into, to provide supply voltage to the section point；7th transistor, its
The voltage level of the first node is strobed into provide ground voltage to the section point；8th transistor, it is strobed
To the voltage level of the 3rd node to provide the ground voltage；And the 9th transistor, itself and the 8th strings of transistors
Connection connects and is strobed into the voltage level of the clock signal, to provide the ground voltage to the section point.
5. semiconductor circuit according to claim 4,
Wherein, when the voltage level of the clock signal is the first logic level, the value of the section point is by the described 4th
The voltage level determination of transistor, the 6th transistor and at least one offer in the 7th transistor, and the 3rd
Nodal value is determined by the voltage level of section point.
6. semiconductor circuit according to claim 5,
Wherein, when the clock signal voltage level from first logic level transition be the second logic level when, it is described
The value of section point is maintained by the voltage level of the 3rd node, and the value of the 3rd node is by the section point
Voltage level maintains.
7. semiconductor circuit according to claim 1,
Wherein, the 4th circuit includes：4th transistor, it is strobed into the voltage level of the section point, with to institute
State fourth node and supply voltage is provided；5th transistor, it is parallel-connected to the 4th transistor and is strobed into described
The voltage level of clock signal, to provide the supply voltage to the fourth node；6th transistor, it is strobed into described
The voltage level of section point is to provide ground voltage；And the 7th transistor, it is connected in series with the 6th transistor, with to
The fourth node provides the ground voltage.
8. a kind of semiconductor circuit, including：
First node, when clock signal is in the first logic level, its have make with the logic level of enable signal or scanning
Can signal the different logic level values of logic level；
Section point, wherein when the clock signal is in first logic level, by the logic electricity of the first node
The flat value for determining section point, and when the clock signal is in the second logic level, the value of the section point is by the
The logic level of three nodes maintains；
3rd node, wherein the value of the 3rd node is determined by the logic level of the section point；And
Fourth node, wherein determining fourth node by the logic level of section point when clock signal is in the second logic level
Value,
Wherein, the fourth node is discharged by the first transistor and second transistor, and the first transistor is strobed into institute
The voltage level of section point is stated to provide ground voltage to the fourth node, the second transistor is strobed into the clock
The voltage level of signal, to electrically connect the 3rd node and fourth node.
9. semiconductor circuit according to claim 8,
Wherein, when the enable signal or the scan enable signal are in first logic level, the section point
With first logic level, and the 3rd node has second logic level.
10. semiconductor circuit according to claim 9,
Wherein, the fourth node has second logic level.
11. semiconductor circuit according to claim 8,
Wherein, when the enable signal or the scan enable signal are in second logic level, the section point
With second logic level, and the 3rd node has first logic level.
12. semiconductor circuit according to claim 11,
Wherein, the 3rd node is discharged by the first node.
13. semiconductor circuit according to claim 11,
Wherein, when the clock signal is in first logic level, the fourth node has the second logic electricity
Flat, when the clock signal is in second logic level, the fourth node has first logic level.
14. semiconductor circuit according to claim 13,
Wherein, when the clock signal is in second logic level, the fourth node by the second transistor,
3rd node and first node electric discharge.
15. a kind of semiconductor circuit, including：
First gate, the input of clock signal, enable signal or scan enable signal is received, and perform the first logical operation
So that the first output signal is output into first node；
Second gate, receive the signal of the first output signal of first gate, the clock signal and the 3rd node
Input, and perform the second logical operation so that the second output signal is output into section point；
The first transistor and second transistor, it is strobed into the voltage level and each other of the second output signal of the second gate
It is connected in series to determine the value of the 3rd node；
3rd gate, it receives the input of the second output signal and the clock signal of second gate, and performs
3rd logical operation by the 3rd output signal to be output to fourth node；And
Third transistor, it is strobed into the voltage level of the clock signal, to electrically connect the 3rd node and described
Four nodes.
16. semiconductor circuit according to claim 15,
Wherein, first logical operation is included to the clock signal, the enable signal or the scan enable signal
NOR logical operations.
17. semiconductor circuit according to claim 15,
Wherein, second gate includes AND-NOR compound logic doors,
Wherein, second logical operation includes the AND logical operations to the clock signal and the signal of the 3rd node,
And the NOR logical operations to first output signal and the consequential signal of the AND logical operations.
18. semiconductor circuit according to claim 15,
Wherein, the 3rd gate includes NAND gate,
Wherein, the 3rd logical operation includes the NAND logic computing to second output signal and the clock signal.
19. semiconductor circuit according to claim 15,
Wherein, when the voltage level of the clock signal is in the first logic level, the value of the section point is by described
The voltage level of one node is determined, and the value of the 3rd node is determined by the voltage level of the section point.
20. semiconductor circuit according to claim 19,
Wherein, when the clock signal voltage level from first logic level transition be second logic level when,
The value of the section point is maintained by the voltage level of the 3rd node, and the value of the 3rd node is saved by described second
The voltage level of point maintains.
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| KR1020160052148A KR102465497B1 (en) | 2016-04-28 | 2016-04-28 | Semiconductor circuit |
| KR10-2016-0052148 | 2016-04-28 |
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Also Published As
| Publication number | Publication date |
|---|---|
| KR102465497B1 (en) | 2022-11-09 |
| US9876500B2 (en) | 2018-01-23 |
| US20170317676A1 (en) | 2017-11-02 |
| CN107404305B (en) | 2021-03-12 |
| KR20170123031A (en) | 2017-11-07 |
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