KR20160127621A - Semiconductor circuit - Google Patents

Abstract

A semiconductor circuit is provided. The semiconductor circuit comprises: a first circuit (103) which transfers a value of a first node (EN) to a second node (FB) based on a voltage level of a clock signal (CK); a second circuit (104) which a value of the second node (FB) to a third node (ZZ1) based on the voltage level of the clock signal (CK); and a third circuit (105) which determines a value of the third node (ZZ1) based on a voltage level of the second node (FB) and the voltage level of the clock signal (CK). The first circuit (103) comprises: a first transistor (N1) which is gated in a voltage level of the first node (EN); a second transistor (N2) which is connected to the first transistor (N1) in series, and is gated in a voltage level of the third node (ZZ1); and a third transistor (P0) which is connected to the first transistor (N1) and the second transistor (N2), which are connected in series to each other, in parallel or series, and is gated in a reversed voltage level of the clock signal (CK). The second circuit (104) includes a fourth transistor (N0) gated in the voltage level of the clock signal (CK).

Description

[0001] DESCRIPTION [0002] SEMICONDUCTOR CIRCUIT [

The present invention relates to a semiconductor circuit.

As the process becomes finer, more logic circuits are integrated on a single chip. As a result, the power consumption per unit area of the chip is gradually increasing. For this reason, the problem of heat generation is becoming an important issue even in electronic devices using such chips.

A clock gate that supplies a clock signal to an operation circuit including a flip-flop can be regarded as a typical device that consumes the most power in an electronic device. Therefore, it has become very important to reduce the power consumption of such devices.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor circuit in which product reliability is improved and consumed power is reduced.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems which are not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor circuit comprising a first node (ENB) for propagating a value of a first node (EN) to a second node (FB) based on a voltage level of a clock signal Circuit 103; A second circuit 104 for propagating the value of the second node FB to the third node ZZ1 based on the voltage level of the clock signal CK; And a third circuit (105) for determining the value of the third node (ZZ1) based on the voltage level of the second node (FB) and the voltage level of the clock signal (CK), and the first circuit A first transistor N1 gated to the voltage level of the first node EN, a second transistor N2 connected in series with the first transistor N1 and gating to the voltage level of the third node ZZ1, (EN) is connected in parallel with the first transistor (N1) and the second transistor (N2) connected to the first node (N1) and gated to the inverted voltage level of the clock signal (CK) And a third transistor P0.

In some embodiments of the present invention, the third circuit 105 is coupled to a fifth transistor (P2) that is gated to the inverted voltage level of the second node (FB) to provide a power supply voltage to the third node And a sixth transistor connected in parallel with the fifth transistor P2 and gating to an inverted voltage level of the clock signal CK to provide a power supply voltage to the third node ZZ1.

In some embodiments of the present invention, the second circuit 104 is coupled to an eighth transistor (P1) that is gated to an inverted voltage level of the third node ZZ1 to provide a supply voltage to the second node FB A fourth transistor N0 gated to the voltage level of the clock signal CK and a second node N2 gated to the inverted voltage level of the second node FB to provide a ground voltage to the second node FB, 9 < / RTI > transistor N3.

In some embodiments of the present invention, the second circuit 104 further includes a tenth transistor N4 coupled in series with the ninth transistor N3 and gated to the voltage level of the clock signal CK can do.

In some embodiments of the present invention, the drain of the tenth transistor N4 may be coupled to the second node FB.

In some embodiments of the present invention, the drain of the tenth transistor N4 may be coupled between the first transistor N1 and the second transistor N2.

In some embodiments of the present invention, the third circuit (105) further comprises a seventh transistor gated to a voltage level of the second node (FB), and the source of the seventh transistor and the ninth transistor N3 may be connected to the drain of the fourth transistor N0.

In some embodiments of the present invention, the drain of the ninth transistor (N3) may be connected to the second node (FB).

In some embodiments of the present invention, the drain of the ninth transistor (N3) may be connected between the first transistor (N1) and the second transistor (N2).

In some embodiments of the present invention, the second circuit 104 is coupled to an eighth transistor (P1) that is gated to an inverted voltage level of the third node ZZ1 to provide a supply voltage to the second node FB And a ninth transistor N3 gated to an inverted voltage level of the second node FB to provide a ground voltage, and the third circuit 105 generates a voltage level of the clock signal CK And a NAND gate 108 having a first input and a voltage level of the second node FB as a second input.

In some embodiments of the present invention, the drain of the tenth transistor N4 may be coupled to the second node FB.

In some embodiments of the present invention, the drain of the tenth transistor N4 may be coupled between the first transistor N1 and the second transistor N2.

In some embodiments of the invention, the semiconductor circuit further comprises an output circuit (102) for determining a voltage level of a node (ECK) based on a voltage level of a third node (ZZ1), wherein the output circuit May include a latch circuit.

According to another aspect of the present invention, there is provided a semiconductor circuit including a first node (FB) that propagates a value of a first node (EN) to a second node (FB) based on a voltage level of a clock signal Circuit 103; A second circuit 104 for propagating the value of the second node FB to the third node ZZ1 based on the voltage level of the clock signal CK; And a third circuit (105) for determining the value of the third node (ZZ1) based on the voltage level of the second node (FB) and the voltage level of the clock signal (CK), and the first circuit A first transistor N1 gated to the voltage level of the first node EN, a second transistor N2 connected in series to the first transistor N1 and gating to the voltage level of the third node ZZ1, And a third transistor (P0) gated to the inverted voltage level of the signal (CK) to provide a value of the first node (EN) to the second node (FB), and the second circuit (104) And a fourth transistor N0 gated to the voltage level of the clock signal CK to transfer the output value of the inverter to the third node ZZ1, and the third circuit 105 Is connected in parallel with the fifth transistor P2 and the fifth transistor P2 gating to the inverted voltage level of the second node FB and providing the power supply voltage to the third node ZZ1. And is gated to the voltage level of the inverted clock signal (CK) may include a sixth transistor for providing a power supply voltage to the third node (ZZ1).

In some embodiments of the present invention, the third transistor (P0) may be connected in parallel with the first transistor (N1) and the second transistor (N2) coupled in series.

In some embodiments of the present invention, the third transistor (P0) may be connected in series with the first transistor (N1) and the second transistor (N2) connected in series.

In some embodiments of the present invention, the first circuit 103 is gated to an inverted voltage level of the first node EN to provide a supply voltage to the second node FB, And a seventh transistor connected in series with the first node P0.

In some embodiments of the present invention, the second circuit 104 is coupled to an eighth transistor (P1) that is gated to an inverted voltage level of the third node ZZ1 to provide a supply voltage to the second node FB A ninth transistor N3 gated to an inverted voltage level of the second node FB to provide a ground voltage and a seventh transistor N3 connected in series with the ninth transistor N3 to provide a voltage level of the clock signal CK And a tenth transistor N4 which is gated to the first node N2.

In some embodiments of the present invention, the drain of the tenth transistor N4 may be coupled to the second node FB.

In some embodiments of the present invention, the drain of the tenth transistor N4 may be coupled between the first transistor N1 and the second transistor N2.

In some embodiments of the invention, the semiconductor circuit further comprises an output circuit (102) for determining a voltage level of the node (ECK) based on the voltage level of the third node (ZZ1), wherein the output circuit 102 may include a latch circuit.

According to another aspect of the present invention, there is provided a semiconductor circuit comprising a first node (EN) for propagating a value of a first node (EN) to a second node (FB) based on a voltage level of a clock signal 1 circuit 103; A second circuit 104 for propagating the value of the second node FB to the third node ZZ1 based on the voltage level of the clock signal CK; And a third circuit (105) for determining the value of the third node (ZZ1) based on the voltage level of the second node (FB) and the voltage level of the clock signal (CK), and the first circuit A first transistor N1 gated to the voltage level of the first node EN, a second transistor N2 connected in series with the first transistor N1 and gating to the voltage level of the third node ZZ1, And is connected to the first transistor N1 and the second transistor N2 connected in parallel and gated to the inverted voltage level of the clock signal CK to supply the value of the first node EN to the second node FB And the second circuit 104 includes a third transistor P0 that gates to the voltage level of the clock signal CK and transfers the value of the second node FB to the third node ZZ1, (N0).

In some embodiments of the present invention, the third circuit 105 is coupled to a fifth transistor (P2) that is gated to the inverted voltage level of the second node (FB) to provide a power supply voltage to the third node And a sixth transistor connected in parallel with the fifth transistor P2 and gating to an inverted voltage level of the clock signal CK to provide a power supply voltage to the third node ZZ1.

In some embodiments of the present invention, the second circuit 104 is coupled to a seventh transistor P1 (P1) which is gated to the inverted voltage level of the third node ZZ1 to provide a power supply voltage to the second node FB An eighth transistor N3 gated to an inverted voltage level of the second node FB to provide a ground voltage and a seventh transistor N3 connected in series with the eighth transistor N3 to provide a voltage level of the clock signal CK And a ninth transistor N4 which is gated to the first node N2.

According to another aspect of the present invention, there is provided a semiconductor circuit comprising a first node (EN) for propagating a value of a first node (EN) to a second node (FB) based on a voltage level of a clock signal A second circuit 104 for propagating the value of the second node FB to the third node ZZ1 based on the voltage level of the clock signal CK, And a third circuit 105 for determining the value of the third node ZZ1 based on the voltage level of the first node EN and the voltage level of the clock signal CK, A first transistor N1 gated to the first node N1 to provide a ground voltage and a second transistor N2 connected in series with the first transistor N1 and gating to a voltage level of the third node ZZ1 to provide a ground voltage to the second node FB And is gated to the inverted voltage level of the clock signal CK to connect the value of the first node EN to the second node N2 and the second node N2, (FB).

According to another aspect of the present invention, there is provided a semiconductor circuit comprising: a first node which inverts a voltage level of a first node when a clock signal is at a first voltage level, A first circuit (103) comprising a first transistor (P0) which propagates to a node (FB); A second circuit (N0) including a second transistor (N0) that inverts the voltage level of the second node (FB) and propagates to the third node (ZZ1) when the clock signal (CK) is at the second voltage level 104); And when the clock signal CK transits from the first voltage level L to the second voltage level H, the third node ZZ1 is gated to the inverted voltage level of the second node FB, And a third transistor (P2) for providing a second voltage.

In some embodiments of the present invention, the first circuit 103 includes a fifth transistor N1 and a sixth transistor N2 that are connected in series with each other, and the fifth transistor N1 and / Wherein the sixth transistor N2 is connected in parallel or in series with the first transistor P0 and the clock signal CK is a first voltage level L when the first node EN is at a first voltage level L, The first transistor P0 and the sixth transistor N2 are turned on so that the second node FB has a second voltage level H and the clock signal CK is at a voltage level L, The first transistor P0 is turned off to maintain the second voltage level H of the second node FB and the second transistor N0 is turned on when the first transistor P0 is at the second voltage level H, So that the second voltage level H of the second node FB can be inverted and propagated to the third node ZZ1.

In some embodiments of the present invention, when the clock signal (CK) is at a first voltage level (L), the third node (ZZ1) is connected to the fourth The power supply voltage can be supplied by the transistor.

In some embodiments of the present invention, the first circuit 103 includes a fifth transistor N1 and a sixth transistor N2 that are connected in series with each other, and the fifth transistor N1 and / Wherein the sixth transistor N2 is connected in parallel or in series with the first transistor P0 and the clock signal CK is at a first voltage level H when the first node EN is at a second voltage level H, The first transistor P0, the fifth transistor N1 and the sixth transistor N2 are turned on so that the second node FB outputs a first voltage level L The first transistor P0 is turned off to maintain the first voltage level L of the second node FB when the clock signal CK is at the second voltage level H, The second transistor N0 may be turned on and the third node ZZ1 may be supplied with the power supply voltage by the third transistor P2.

According to another aspect of the present invention, there is provided a semiconductor circuit comprising: a clock; A first clock gate circuit and a second clock gate circuit each including a first circuit and a second circuit; And a second operating circuit that is provided with a clock through a first clock gate circuit and a clock that is provided through a second clock gate circuit, wherein the first circuit is configured to receive the clock signal (CK) at a first voltage level (L), the first transistor (P0) inverts the voltage level of the first node (EN) and propagates to the second node (FB), the second transistor (N1) and the third transistor , The second transistor (N1) and the third transistor (N2) connected in series are connected in parallel with the first transistor (P0), and the second circuit is a circuit in which the clock signal (CK) The fourth transistor N0 which inverts the voltage level of the second node FB when the clock signal CK is at the first voltage level and propagates to the third node ZZ1 when the voltage level is H do.

In some embodiments of the present invention, the first clock gate circuit and the second clock gate circuit are configured such that when the clock signal (CK) transitions from the first voltage level (L) to the second voltage level (H) , And a fifth transistor (P2) gated to an inverted voltage level of the second node (FB) to provide a power supply voltage to the third node (ZZ1).

In some embodiments of the present invention, the apparatus further comprises a controller for providing an enable (E) and a scan enable (SE) signal to the first clock gate circuit and the second clock gate circuit, wherein the first voltage level The first clock gate circuit receiving the enable signal of the first transistor P0 and the first transistor P0 uses the first transistor P0 and the fourth transistor N0 to apply the first voltage level L to the first operation circuit, And the second clock gate circuit provided with the enable (E) signal of the second voltage level H uses the first transistor P0 and the fourth transistor N0, 2 < / RTI > operation circuit.

In some embodiments of the present invention, the first clock gate circuit is configured such that when the clock signal CK is at a first voltage level L, the first transistor P0 is turned on and the second node FB The first transistor P0 has a first voltage level L and the first transistor P0 is turned off when the clock signal CK is at a second voltage level H, The fourth transistor N0 may be turned on while the voltage level L is maintained and the third node ZZ1 may be supplied with the power supply voltage by the fifth transistor P2.

In some embodiments of the present invention, the second clock gate circuit is configured such that when the clock signal CK is at a first voltage level L, the first transistor P0 is turned on and the second node FB ) Of the second node (FB) has a second voltage level (H), and when the clock signal (CK) is at a second voltage level (H), the first transistor The fourth transistor N0 is turned on and inverts the second voltage level H of the second node FB to propagate to the third node ZZ1 while maintaining the voltage level H, The third node ZZ1 can be supplied with the power supply voltage by the fifth transistor gated to the inverted voltage level of the clock signal CK when the first node CK is at the first voltage level L. [

The details of other embodiments are included in the detailed description and drawings.

1A is a circuit diagram showing a semiconductor circuit according to an embodiment of the present invention.
1B shows a modification of the output circuit of the semiconductor circuit according to an embodiment of the present invention.
1C shows another modification of the output circuit of the semiconductor circuit according to the embodiment of the present invention.
2 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.
3 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.
4 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.
5 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.
6 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.
7 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.
8 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.
9 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.
10 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.
11 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.
12 is a circuit diagram showing a semiconductor circuit according to still another embodiment of the present invention.
13 is a circuit diagram showing a semiconductor circuit according to still another embodiment of the present invention.
14 is a block diagram of an SoC system including semiconductor circuits according to embodiments of the present invention.
15 is a block diagram of an electronic system including a semiconductor circuit according to embodiments of the present invention.
16 to 18 are exemplary semiconductor systems to which semiconductor circuits according to some embodiments of the present invention may be applied.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

1A is a circuit diagram showing a semiconductor circuit according to an embodiment of the present invention.

1A, a semiconductor circuit 100 according to an embodiment of the present invention includes an input circuit 101a, a first circuit 103a, a second circuit 104, a third circuit 105, and an output circuit 102).

The input circuit 101a can determine the voltage level of the node EN based on the voltage levels of the enable (E) and scan enable (SE) signals. 1A, the input circuit 101a is shown as a NOR gate having an enable (E) signal as a first input and a scan enable (SE) signal as a second input, but the scope of the present invention is not limited thereto . That is, the input circuit 101a may include any circuit capable of determining the voltage level of the node EN of the first circuit 103a. This is also applied to another embodiment of the present invention to be described later with reference to FIGS.

On the other hand, the output circuit 102 can determine the voltage level of the node ECK based on the voltage level of the node ZZ1. In FIG. 1A, the output circuit 102 is shown as an inverter that inverts the voltage level of the node ZZ1, but the scope of the present invention is not limited thereto. That is, the output circuit 102 may include any circuit capable of determining the voltage level of the node ECK. This is also applied to another embodiment of the present invention to be described later with reference to FIGS. In particular, the output circuit 102 may include a latch circuit for operating a semiconductor circuit according to various embodiments of the present invention with a flip-flop, as described below with respect to Figures 1B and 1C.

The first circuit 103a includes a transistor N1 gated to the voltage level of the node EN, a transistor N2 connected in series with the transistor N1 and gating to the voltage level of the node ZZ1, , N2 and gated to the inverted voltage level of the clock signal (CK). In particular, the transistors N1 and N2 are connected in parallel with the transistor P0, and the source of any one of the transistors N1 and N2 is connected to the node FB. In some embodiments of the present invention, the order of connection of the transistors N1 and N2 connected in series to one another may be reversed.

The second circuit 104 is gated to the inverted voltage level of the node ZZ1 to provide the supply voltage to the node FB and to the inverted voltage level of the node FB to provide the ground voltage And a transistor N4 connected in series with transistor N3 and transistor N3 which gates to the voltage level of clock signal CK and provides a ground voltage to node FB. In some embodiments of the present invention, the order of connection of the transistors N3 and N4 connected in series to one another may be reversed. That is, the transistor N4 may be disposed between the drain and the node FB of the transistor N3 to provide the ground voltage provided by the transistor N3 to the node FB, and the ground voltage Lt; RTI ID = 0.0 > N4. ≪ / RTI > In the latter case, the transistor N3 may be disposed between the drain of the transistor N4 and the node FB. The second circuit 104 also includes a transistor N0 gated to the voltage level of the clock signal CK.

The third circuit 105 is connected in parallel with the transistor P2 and the transistor P2 which gates to the inverted voltage level of the node FB and provides the power supply voltage to the node ZZ1 and inverts the clock signal CK Lt; RTI ID = 0.0 > ZZ1 < / RTI >

Hereinafter, the operation of the semiconductor circuit 100 will be described.

The first circuit 103a propagates the value of the node EN to the node FB based on the voltage level of the enable E and the voltage level of the clock signal CK. That is, the value of the node EN is propagated to the node FB through the transistors P0, N1 and N2. For example, when the clock signal CK is at the first voltage level L, the transistors P0 and N2 are turned on regardless of the state of the transistor N1. Therefore, the value of the node FB is determined as the value of the inverted node EN via the inverter.

In this case, the node ZZ1 has the second voltage level H by the transistor which is gated to the inverted voltage level of the clock signal CK in the third circuit 105. When the clock signal CK is at the first voltage level L, the node ZZ1 has the second voltage level H. Therefore, the node ECK is at the same level as the voltage level of the clock signal CK 1 voltage level (L).

In this specification, the meaning of any circuit propagating the value of a specific node A to another specific node B means that it is possible to determine the value of another specific node B according to the value of the specific node A . Therefore, the value of the specific node A does not have to be the same as the value of the specific node B. For example, in FIG. 1A, the first circuit 103a includes an inverter that inverts the value of the node EN, and the first circuit 103a is configured to propagate the value of the node EN to the node FB Means meaning to transfer the value inverted by the inverter (i.e., / EN) to node FB using transistors P0, N1, N2.

The second circuit 104 propagates the value of the node FB to the node ZZ1 based on the voltage level of the clock signal CK. That is, the value of the node FB is propagated through the transistor N0 to the node ZZ1. For example, when the clock signal CK is at the second voltage level H, the transistor N0 is turned on, so that the value of the node ZZ1 is determined as the value of the inverted node FB via the inverter.

The third circuit 105 determines the value of the node ZZ1 based on the voltage level of the node FB and the voltage level of the clock signal CK. Particularly, when the clock signal CK transitions from the first voltage level L to the second voltage level H, the transistor P2 is gated to the inverted voltage level of the node FB and supplied to the node ZZ1 Provide the power supply voltage.

The operation of the semiconductor circuit 100 will be described in more detail. When the node EN is at the first voltage level L, the transistor P0 is turned on when the clock signal CK is at the first voltage level L The node FB has a second voltage level H. At this time, the node ZZ1 can be supplied with the power supply voltage by the transistor gated to the inverted voltage level of the clock signal CK in the third circuit 105. [ On the other hand, when the clock signal CK is at the second voltage level H, the transistor P0 is turned off to maintain the second voltage level H of the node FB. At this time, the transistor N0 is turned on, inverts the second voltage level H of the node FB, and propagates to the node ZZ1.

In other words, when the node EN is at the first voltage level L, that is, when the enable signal E has the second voltage level H, the clock signal CK is at the first voltage level L ), The node FB, ZZ1 has the second voltage level H, which causes the node ECK to have the first voltage level L. [ On the other hand, when the clock signal CK is at the second voltage level H, the voltage level of the node FB is maintained at the second voltage level H as it is and the node ZZ1 is maintained at the first voltage level L , Which causes the node ECK to have a second voltage level H. That is, when the enable (E) signal has the second voltage level (H), it can be seen that the node ECK has the same value as the value of the clock signal CK.

On the other hand, when the node EN is at the second voltage level H, when the clock signal CK is at the first voltage level L, the transistors N1 and N2 are turned on according to the condition of the transistor P0 The node FB has a first voltage level L. [ On the other hand, when the clock signal CK is at the second voltage level H, the transistor P0 is turned off to maintain the first voltage level L of the node FB. At this time, the node ZZ1 can be supplied with the power supply voltage by the transistor P2 which is gated to the inverted voltage level of the node FB.

In other words, when the node EN is at the second voltage level H, that is, when the enable signal E has the first voltage level L, the clock signal CK is at the first voltage level L , The node FB has the first voltage level L and the node ZZ1 has the second voltage level H so that the node ECK has the first voltage level L. [ On the other hand, when the clock signal CK is at the second voltage level H, the voltage level of the node FB is maintained at the first voltage level L as it is and the node ZZ1 is maintained at the second voltage level H , Which causes the node ECK to have the first voltage level L. That is, when the enable (E) signal has the first voltage level L, it can be seen that the node ECK has the first voltage level L value regardless of the value of the clock signal CK.

1B shows a modification of the output circuit of the semiconductor circuit according to an embodiment of the present invention.

Referring to FIG. 1B, the output circuit 102a includes transistors LP1, LN1, and LN2 coupled in series with each other and transistors LP2, LP3, LN3, and LN4 coupled in series with each other.

The transistor LP1 is gated to the inverted voltage level of the node ZZ1 to provide the supply voltage to the node ZZ2 and the transistor LN2 is gated to the inverted voltage level FBN of the node FB, And the transistor LN1 is gated to the voltage level of the clock signal CK to provide the ground voltage to the node ZZ2.

On the other hand, the transistor LP2 is gated to the voltage level of the node ZZ2 to provide the power supply voltage, and the transistor LP3 is gated to the inverted voltage level of the clock signal CK to supply the power supply voltage to the node ZZ2 do. The transistor LN4 is gated to the voltage level of the node ZZ1 to provide the battery voltage and the transistor LN3 is gated to the inverted voltage level of the node ZZ2 to provide the ground voltage to the node ZZ2.

The output circuit 102a includes a latch in this arrangement, and can operate as a flip-flop if the semiconductor circuit according to various embodiments of the present invention includes the output circuit 102a. This is also applied to another embodiment of the present invention to be described later with reference to FIGS.

1C shows another modification of the output circuit of the semiconductor circuit according to the embodiment of the present invention.

Referring to FIG. 1C, the output circuit 102b includes transistors LP1, LN1, and LN2 coupled in series with each other and transistors LP2, LP3, and LN3 coupled in series with each other.

The transistor LP1 is gated to the inverted voltage level of the node ZZ1 to provide a supply voltage to the node ZZ2 and the transistor LN2 is gated to the voltage level of the node ZZ1 to provide the ground voltage, (LN1) is gated to the voltage level of the clock signal (CK) to provide the ground voltage to the node (ZZ2).

On the other hand, the transistor LP2 is gated to the voltage level of the node ZZ2 to provide the power supply voltage, and the transistor LP3 is gated to the inverted voltage level of the clock signal CK to supply the power supply voltage to the node ZZ2 do. The transistor LN3 is gated to the inverted voltage level of the node ZZ2 to provide the ground voltage from the transistor LN2 to the node ZZ2.

The output circuit 102b includes a latch in this arrangement, and can operate as a flip-flop if the semiconductor circuit according to various embodiments of the present invention includes the output circuit 102b. This is also applied to another embodiment of the present invention to be described later with reference to FIGS.

2 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.

Referring to Fig. 2, the semiconductor circuit 110 according to the embodiment of Fig. 2 includes a first circuit 103b. The first circuit 103b includes a transistor N1 gated to the voltage level of the node EN, a transistor N2 connected in series with the transistor N1 and gating to the voltage level of the node ZZ1, , N2 and gated to the inverted voltage level of the clock signal CK. In particular, the transistors N1 and N2 are connected in series with the transistor P0, and the drain of one of the transistors N1 and N2 is connected to the node FB. In some embodiments of the present invention, the order of connection of the transistors N1 and N2 connected in series to one another may be reversed.

3 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.

Referring to FIG. 3, the semiconductor circuit 120 according to the embodiment of FIG. 3 includes a first circuit 103c. The transistor N1 and the second transistor N2 in the first circuit 103c are connected in series with the transistor P0 and the first circuit 103c is gated to the inverted voltage level of the node EN, To the node FB, and a transistor connected in series with the transistor P0. In some embodiments of the invention, the connection order of the transistors connected in series to one another may be interchanged.

4 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.

Referring to FIG. 4, the semiconductor circuit 130 according to the embodiment of FIG. 4 includes a first circuit 103d. The first circuit 103d includes a transistor N1 gated to the voltage level of the node EN, a transistor N2 connected in series with the transistor N1 and gating to the voltage level of the node ZZ1, , N2 and gated to the inverted voltage level of the clock signal (CK). In particular, the transistors N1 and N2 are connected in parallel with the transistor P0, and the source of any one of the transistors N1 and N2 is connected to the node FB.

The second circuit 104 is gated to the inverted voltage level of the node ZZ1 to provide the supply voltage to the node FB and to the inverted voltage level of the node FB to provide the ground voltage And a transistor N4 connected in series with transistor N3 and transistor N3 which gates to the voltage level of clock signal CK and provides a ground voltage to node FB. Particularly noteworthy is that the drain of the transistor N4 of the second circuit 104 is connected between the transistor N1 and the transistor N2 of the first circuit 103d.

5 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.

Referring to FIG. 5, the semiconductor circuit 140 according to the embodiment of FIG. 5 includes a first circuit 103c. The transistor N1 and the second transistor N2 in the first circuit 103c are connected in series with the transistor P0 and the first circuit 103c is gated to the inverted voltage level of the node EN, To the node FB, and a transistor connected in series with the transistor P0.

The second circuit 104 is gated to the inverted voltage level of the node ZZ1 to provide the supply voltage to the node FB and to the inverted voltage level of the node FB to provide the ground voltage And a transistor N4 connected in series with transistor N3 and transistor N3 which gates to the voltage level of clock signal CK and provides a ground voltage to node FB. Particularly noteworthy is that the drain of the transistor N4 of the second circuit 104 is connected between the transistor N1 of the first circuit 103d and the second transistor N2.

6 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.

6, the semiconductor circuit 150 according to the embodiment of FIG. 6 includes a first circuit 103a and a fourth circuit 104b corresponding to the second circuit 104 and the third circuit 105 in the above- Circuit 106, The first circuit 103a includes a transistor N1 gated to the voltage level of the node EN, a transistor N2 connected in series with the transistor N1 and gating to the voltage level of the node ZZ1, , N2 and gated to the inverted voltage level of the clock signal (CK). In particular, the transistors N1 and N2 are connected in parallel with the transistor P0, and the source of any one of the transistors N1 and N2 is connected to the node FB. In some embodiments of the present invention, the order of connection of the transistors N1 and N2 connected in series to one another may be reversed.

The fourth circuit 106 is connected to the transistor P2 and the transistor P2 which gates to the inverted voltage level of the node FB and provides the power supply voltage to the node ZZ1 and the clock signal CK, Lt; RTI ID = 0.0 > ZZ1 < / RTI > Particularly noteworthy is that the fourth circuit 106 is gated to the voltage level of the node FB and its source is connected to the drain of the transistor N0.

The fourth circuit 106 is also gated to the inverted voltage level of the transistor P1, node FB which is gated to the inverted voltage level of the node ZZ1 to provide the power supply voltage to the node FB, And a transistor N3 for providing a voltage, and the source of the transistor N3 is connected to the drain of the transistor N0.

7 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.

Referring to FIG. 7, unlike FIG. 6, the semiconductor circuit 160 according to the embodiment of FIG. 7 includes a first circuit 103b. The first circuit 103b includes a transistor N1 gated to the voltage level of the node EN, a transistor N2 connected in series with the transistor N1 and gating to the voltage level of the node ZZ1, , N2 and gated to the inverted voltage level of the clock signal CK. In particular, the transistors N1 and N2 are connected in series with the transistor P0, and the drain of one of the transistors N1 and N2 is connected to the node FB. In some embodiments of the present invention, the order of connection of the transistors N1 and N2 connected in series to one another may be reversed.

8 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.

8, the semiconductor circuit 170 according to the embodiment of FIG. 8 includes a first circuit 103d and a second circuit 104 and a third circuit 105 in the previous embodiment, And a fourth circuit 106 corresponding to the second circuit 106. The first circuit 103d includes a transistor N1 gated to the voltage level of the node EN, a transistor N2 connected in series with the transistor N1 and gating to the voltage level of the node ZZ1, , N2 and gated to the inverted voltage level of the clock signal (CK). In particular, the transistors N1 and N2 are connected in parallel with the transistor P0, and the source of any one of the transistors N1 and N2 is connected to the node FB.

The fourth circuit 106 is connected to the transistor P2 and the transistor P2 which gates to the inverted voltage level of the node FB and provides the power supply voltage to the node ZZ1 and the clock signal CK, Lt; RTI ID = 0.0 > ZZ1 < / RTI > Here, the fourth circuit 106 is gated to the voltage level of the node FB, and its source is connected to the drain of the transistor N0. The fourth circuit 106 is also gated to the inverted voltage level of the transistor P1, node FB which is gated to the inverted voltage level of the node ZZ1 to provide the power supply voltage to the node FB, And a transistor N3 for providing a voltage, and the source of the transistor N3 is connected to the drain of the transistor N0.

Particularly noteworthy is that the drain of the transistor N3 is connected between the transistor N1 and the transistor N2.

9 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.

9, the semiconductor circuit 180 according to the embodiment of FIG. 9 includes a first circuit 103c and a second circuit 104 and a third circuit 105 in the previous embodiment, And a fourth circuit 106 corresponding to the second circuit 106. The transistor N1 and the second transistor N2 in the first circuit 103c are connected in series with the transistor P0 and the first circuit 103c is gated to the inverted voltage level of the node EN, To the node FB, and a transistor connected in series with the transistor P0.

The fourth circuit 106 is connected to the transistor P2 and the transistor P2 which gates to the inverted voltage level of the node FB and provides the power supply voltage to the node ZZ1 and the clock signal CK, Lt; RTI ID = 0.0 > ZZ1 < / RTI > Here, the fourth circuit 106 is gated to the voltage level of the node FB, and its source is connected to the drain of the transistor N0. The fourth circuit 106 is also gated to the inverted voltage level of the transistor P1, node FB which is gated to the inverted voltage level of the node ZZ1 to provide the power supply voltage to the node FB, And a transistor N3 for providing a voltage, and the source of the transistor N3 is connected to the drain of the transistor N0.

Particularly noteworthy is that the drain of the transistor N3 is connected between the transistor N1 and the transistor N2.

10 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.

10, the semiconductor circuit 190 according to the embodiment of FIG. 10 includes a first circuit 103a, a fifth circuit 107a, and a NAND gate 108. The first circuit 103a, the fifth circuit 107a, The first circuit 103a includes a transistor N1 gated to the voltage level of the node EN, a transistor N2 connected in series with the transistor N1 and gating to the voltage level of the node ZZ1, , N2 and gated to the inverted voltage level of the clock signal (CK). In particular, the transistors N1 and N2 are connected in parallel with the transistor P0, and the source of any one of the transistors N1 and N2 is connected to the node FB. In some embodiments of the present invention, the order of connection of the transistors N1 and N2 connected in series to one another may be reversed.

The fifth circuit 107a gates to the inverted voltage level of the node ZZ1 to provide the power supply voltage to the node FB and gates to the inverted voltage level of the node FB to provide the ground voltage And a transistor N4 connected in series with transistor N3 and transistor N3 which gates to the voltage level of clock signal CK and provides a ground voltage to node FB. In some embodiments of the present invention, the order of connection of the transistors N3 and N4 connected in series to one another may be reversed.

The NAND gate 108 determines the voltage level of the node ZZ1 with the voltage level of the clock signal CK as the first input and the voltage level of the node FB as the second input.

11 is a circuit diagram showing a semiconductor circuit according to another embodiment of the present invention.

Referring to Fig. 11, unlike the embodiment of Fig. 10, the semiconductor circuit 200 according to the embodiment of Fig. 11 includes a first circuit 103b. The first circuit 103b includes a transistor N1 gated to the voltage level of the node EN, a transistor N2 connected in series with the transistor N1 and gating to the voltage level of the node ZZ1, , N2 and gated to the inverted voltage level of the clock signal CK. In particular, the transistors N1 and N2 are connected in series with the transistor P0, and the drain of one of the transistors N1 and N2 is connected to the node FB. In some embodiments of the present invention, the order of connection of the transistors N1 and N2 connected in series to one another may be reversed.

12 is a circuit diagram showing a semiconductor circuit according to still another embodiment of the present invention.

Referring to Fig. 12, unlike the embodiment of Fig. 10, the semiconductor circuit 200 according to the embodiment of Fig. 12 includes a fifth circuit 107b. The fifth circuit 107b is gated to the inverted voltage level of the node ZZ1 to provide the power supply voltage to the node FB and to the inverted voltage level of the node FB to provide the ground voltage And a transistor N4 connected in series with transistor N3 and transistor N3 which gates to the voltage level of clock signal CK and provides a ground voltage to node FB.

Particularly noteworthy is that the drain of the transistor N4 of the fifth circuit 107b is connected between the transistor N1 and the transistor N2 of the first circuit 103a.

13 is a circuit diagram showing a semiconductor circuit according to still another embodiment of the present invention.

13, a semiconductor circuit 300 according to another embodiment of the present invention includes a first clock gate circuit 310 including a clock CK, a first circuit and a second circuit, The clock signal CK is provided through the first operation circuit 320 and the second clock gate circuit 330 receiving the clock signal CK through the circuit 330 and the first clock gate circuit 310, And a second operating circuit 340.

The first circuit includes a transistor P0 that inverts the voltage level of the node EN and propagates to the node FB when the clock signal CK is at the first voltage level L. [ On the other hand, when the clock signal CK is at the second voltage level H, the second circuit inverts the voltage level of the node FB when the clock signal CK is at the first voltage level L, ZZ1, respectively. In some embodiments of the present invention, the first circuit and the second circuit may each be configured such that when the clock signal CK transitions from the first voltage level L to the second voltage level H, And a transistor P2 that is gated to a voltage level that provides the power supply voltage to the node ZZ1.

The first clock gate circuit 310 of the semiconductor circuit 300 according to another embodiment of the present invention may be provided with the enable E and scan enable signals and the second clock gate circuit 330 May be provided with an enable (E ') and a scan enable (SE') signal. The first clock gate circuit 310 provided with the enable signal E of the first voltage level L is supplied with the first voltage level V1 to the first operation circuit 320 using the transistor P0 and the transistor N0, (L) < / RTI > The second clock gate circuit 330 receiving the enable signal E 'of the second voltage level H is connected to the second operation circuit 340 using the transistor P0 and the transistor N0, It is possible to transmit the signal CK.

For example, when the clock signal CK is at the first voltage level L, the first clock gate circuit 310 turns on the transistor P0 and the node FB sets the first voltage level L to When the clock signal CK is at the second voltage level H, the transistor P0 is turned off to maintain the first voltage level L of the node FB, the transistor N0 is turned on, The node ZZ1 may be supplied with the power supply voltage by the third transistor P2.

On the other hand, when the clock signal CK is at the first voltage level L, the second clock gate circuit 330 has the transistor P0 turned on and the node FB having the second voltage level H, When the clock signal CK is at the second voltage level H, the transistor P0 is turned off to maintain the second voltage level H of the node FB, and the transistor N0 is turned on, And when the clock signal CK is at the first voltage level L, the node ZZ1 inverts the second voltage level H of the clock signal CK and inverts the second voltage level H of the clock signal CK to the node ZZ1, The power supply voltage can be provided by the transistor being gated to the level.

14 is a block diagram of an SoC system including semiconductor circuits according to embodiments of the present invention.

Referring to FIG. 14, the SoC system 1000 includes an application processor 1001 and a DRAM 1060.

The application processor 1001 may include a central processing unit 1010, a multimedia system 1020, a bus 1030, a memory system 1040, and a peripheral circuit 1050.

The central processing unit 1010 can perform operations necessary for driving the SoC system 1000. [ In some embodiments of the invention, the central processing unit 1010 may be configured in a multicore environment that includes a plurality of cores.

The multimedia system 1020 may be used in the SoC system 1000 to perform various multimedia functions. The multimedia system 1020 may include a 3D engine module, a video codec, a display system, a camera system, a post-processor, and the like .

The bus 1030 can be used for data communication between the central processing unit 1010, the multimedia system 1020, the memory system 1040, and the peripheral circuit 1050. In some embodiments of the invention, such a bus 1030 may have a multi-layer structure. For example, the bus 1030 may be a multi-layer Advanced High-performance Bus (AHB) or a multi-layer Advanced Extensible Interface (AXI). However, the present invention is not limited thereto.

The memory system 1040 can be connected to an external memory (for example, DRAM 1060) by the application processor 1001 to provide an environment necessary for high-speed operation. In some embodiments of the invention, the memory system 1040 may include a separate controller (e.g., a DRAM controller) for controlling an external memory (e.g., DRAM 1060).

The peripheral circuit 1050 can provide an environment necessary for the SoC system 1000 to be smoothly connected to an external device (e.g., a main board). Accordingly, the peripheral circuit 1050 may include various interfaces for allowing an external device connected to the SoC system 1000 to be compatible.

The DRAM 1060 may function as an operation memory required for the application processor 1001 to operate. In some embodiments of the invention, the DRAM 1060 may be located external to the application processor 1001 as shown. Specifically, the DRAM 1060 can be packaged in an application processor 1001 and a package on package (PoP).

At least one of the elements of the SoC system 1000 may employ any one of the semiconductor circuits according to the embodiments of the present invention described above.

15 is a block diagram of an electronic system including a semiconductor circuit according to embodiments of the present invention.

15, an electronic system 1100 according to an embodiment of the present invention includes a controller 1110, an input / output (I / O) device 1120, a memory device 1130, an interface 1140, 1150, bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via a bus 1150. The bus 1150 corresponds to a path through which data is moved.

 The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The interface 1140 may perform the function of transmitting data to or receiving data from the communication network. Interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver.

Although not shown, the electronic system 1100 may further include a high-speed DRAM and / or SRAM as an operation memory for improving the operation of the controller 1110. [

Electronic system 1100 can be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

At least one of the components of the electronic system 1100 may employ any one of the semiconductor circuits according to the embodiments of the present invention described above.

16 to 18 are exemplary semiconductor systems to which semiconductor circuits according to some embodiments of the present invention may be applied.

Fig. 16 shows the tablet PC 1200, Fig. 17 shows the notebook 1300, and Fig. 18 shows the smartphone 1400. Fig. At least one of the semiconductor circuits according to embodiments of the present invention may be used in such a tablet PC 1200, notebook 1300, smart phone 1400, and the like.

It will also be apparent to those skilled in the art that semiconductor circuits according to some embodiments of the present invention may also be applied to other integrated circuit devices not illustrated. That is, although only the tablet PC 1200, the notebook computer 1300, and the smartphone 1400 have been described as examples of the semiconductor system according to the present embodiment, examples of the semiconductor system according to the present embodiment are not limited thereto. In some embodiments of the invention, the semiconductor system may be a computer, an Ultra Mobile PC (UMPC), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a wireless phone, A mobile phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, A digital audio recorder, a digital audio recorder, a digital picture recorder, a digital picture player, a digital video recorder, ), A digital video player, or the like.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210:
101a: input circuit 102: output circuit
103a, 103b, 103c, 103d: a first circuit 104: a second circuit
105: third circuit 106: fourth circuit
107a, 107b: fifth circuit 108: NAND gate

Claims (20)

A first circuit for propagating the value of the first node to the second node based on the voltage level of the clock signal;
A second circuit for propagating the value of the second node to a third node based on the voltage level of the clock signal; And
And a third circuit for determining a value of the third node based on the voltage level of the second node and the voltage level of the clock signal,
Wherein the first circuit includes a first transistor gated to a voltage level of the first node, a second transistor coupled in series with the first transistor and gating to a voltage level of the third node, And a third transistor coupled in parallel with the second transistor and gated to an inverted voltage level of the clock signal to provide a value of the first node to a second node. The method according to claim 1,
The third circuit gating to an inverted voltage level of the second node to provide a power supply voltage to the third node and a fifth transistor coupled in parallel with the fifth transistor and gating to an inverted voltage level of the clock signal, And a sixth transistor for providing a power supply voltage to the third node. 3. The method of claim 2,
Wherein the second circuit is gated to an inverted voltage level of the third node to provide a power supply voltage to the second node, a fourth transistor gated to a voltage level of the clock signal, And providing a ground voltage to the second node by gating to a voltage level of the second node. The method of claim 3,
And the second circuit further comprises a tenth transistor coupled in series with the ninth transistor and gated to a voltage level of the clock signal. 5. The method of claim 4,
And a drain of the tenth transistor is connected to the second node. 5. The method of claim 4,
And a drain of the tenth transistor is connected between the first transistor and the second transistor. The method of claim 3,
Wherein the third circuit further comprises a seventh transistor gated to a voltage level of the second node,
Wherein a source of the seventh transistor and a source of the ninth transistor are connected to a drain of the fourth transistor. 8. The method of claim 7,
And a drain of the ninth transistor is connected to the second node. 8. The method of claim 7,
And a drain of the ninth transistor is connected between the first transistor and the second transistor. 3. The method of claim 2,
Wherein the second circuit is gated to the inverted voltage level of the third node to provide a power supply voltage to the second node and an eighth transistor gated to the inverted voltage level of the second node to provide a ground voltage, Transistors,
Wherein the third circuit includes a NAND gate having a voltage level of the clock signal as a first input and a voltage level of the second node as a second input. 11. The method of claim 10,
And a drain of the tenth transistor is connected to the second node. 11. The method of claim 10,
And a drain of the tenth transistor is connected between the first transistor and the second transistor. The method according to claim 1,
Further comprising an output circuit for determining a voltage level of the node based on the voltage level of the third node,
Wherein the output circuit includes a latch circuit. A first circuit for propagating the value of the first node to the second node based on the voltage level of the clock signal;
A second circuit for propagating the value of the second node to a third node based on the voltage level of the clock signal; And
And a third circuit for determining a value of the third node based on the voltage level of the second node and the voltage level of the clock signal,
The first circuit comprising: a first transistor gated to a voltage level of the first node; a second transistor coupled in series with the first transistor and gating to a voltage level of the third node; And providing a value of the first node to a second node,
Wherein the second circuit includes an inverter for inverting a value of the second node and a fourth transistor gated to a voltage level of the clock signal to transfer an output value of the inverter to a third node,
The third circuit gating to an inverted voltage level of the second node to provide a power supply voltage to the third node and a fifth transistor coupled in parallel with the fifth transistor and gating to an inverted voltage level of the clock signal, And a sixth transistor for providing a power supply voltage to the third node. 15. The method of claim 14,
And the third transistor is connected in parallel with the first transistor and the second transistor connected in series. 15. The method of claim 14,
And the third transistor is connected in series with the first transistor and the second transistor connected in series. 15. The method of claim 14,
Wherein the first circuit further comprises a seventh transistor gated at an inverted voltage level of the first node to provide a supply voltage to the second node and connected in series with the third transistor. 15. The method of claim 14,
The second circuit gating to an inverted voltage level of the third node to provide a power supply voltage to the second node, a third transistor gated to the inverted voltage level of the second node to provide a ground voltage, And a tenth transistor coupled in series with the ninth transistor and gated to a voltage level of the clock signal. 19. The method of claim 18,
And a drain of the tenth transistor is connected to the second node. 19. The method of claim 18,
And a drain of the tenth transistor is connected between the first transistor and the second transistor.

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