CN107402622B - Memory storage device and power management method thereof - Google Patents
Memory storage device and power management method thereof Download PDFInfo
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- CN107402622B CN107402622B CN201610338976.9A CN201610338976A CN107402622B CN 107402622 B CN107402622 B CN 107402622B CN 201610338976 A CN201610338976 A CN 201610338976A CN 107402622 B CN107402622 B CN 107402622B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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Abstract
The invention provides a memory storage device and a power management method thereof. When the external power supply device is electrically connected to the second connection interface unit, the power management circuit receives a second power supply voltage from the external power supply device through the second connection interface unit, supplies an operation voltage to the memory control circuit unit and the rewritable non-volatile memory module, and simultaneously provides the second power supply voltage to the host device. The technical scheme of the invention can receive power from the host device when being electrically connected with the host device and simultaneously receive power from the external power supply device when being electrically connected with the host device and the external power supply device so as to charge the host device.
Description
Technical Field
The invention relates to a memory storage device and a power management method thereof.
Background
As mobile electronic devices (e.g., smart phones) become more popular, their functions are comparable to those of personal computers, and thus the demand for storing and browsing a large amount of video data on the mobile electronic devices is rapidly increasing. Since the storage space inside a general mobile electronic device is limited, and the price of a mobile electronic device with a high storage capacity is not good, the external storage device is also grown. For example, a USB Flash disk is an external storage device using a NAND Flash Memory (Flash Memory) as a storage medium, and a user can easily plug and unplug the USB Flash disk into and out of a mobile electronic device through a Universal Serial Bus (USB) to transfer digital data. After the conventional external storage device is connected to the mobile electronic device, the inconvenience of using the external storage device for a long time or during movement is caused by the volume or the connection mode. Accordingly, mobile electronic device protective cases have been developed that have memory storage devices embedded therein. That is, when a user places the mobile electronic device in such a protective case, the mobile electronic device can be connected to the memory storage device embedded in the protective case, thereby expanding the storage capacity of the mobile electronic device. However, when the storage capacity is expanded by this method, the connection port of the mobile electronic device is occupied by the storage device, and the mobile electronic device must be taken out from the protective case whenever the mobile electronic device needs to be charged, which causes inconvenience in use. Therefore, it is an objective of those skilled in the art to simultaneously charge a mobile electronic device when a memory storage device is connected to the mobile electronic device.
Disclosure of Invention
The invention provides a memory storage device and a power management method thereof, which can receive power from a host device when being electrically connected with the host device and can receive power from an external power supply device to charge the host device when being electrically connected with the host device and the external power supply device.
An exemplary embodiment of the present invention provides a memory storage device, which includes a rewritable non-volatile memory module, a first connection interface unit, a second connection interface unit, a power management circuit, and a memory control circuit unit. The first connection interface unit is used for connecting to a host device, wherein the first connection interface unit is provided with a first power supply pin and a channel configuration pin. The second connection interface unit is provided with a second power supply pin. The power management circuit is used for receiving a first power supply voltage from the host device through a first power pin of the first connection interface unit and supplying an operation voltage to the memory control circuit unit and the rewritable non-volatile memory module. The memory control circuit unit is coupled to the power management circuit, the rewritable non-volatile memory, the first connection interface unit and the second connection interface unit. When the external power supply device is electrically connected with the second connection interface unit, the power management circuit receives a second power supply voltage from the external power supply device through a second power pin of the second connection interface unit and supplies an output voltage to the memory control circuit unit and the rewritable non-volatile memory module, wherein the second power supply voltage is supplied to the host device through a first power pin of the first connection interface unit. When the external power supply device is electrically disconnected with the second connection interface unit, the power management circuit receives a third power supply voltage through the channel configuration pin of the first connection interface unit and supplies an output voltage to the memory control circuit unit and the rewritable non-volatile memory module. When the first power supply voltage is detected on the first power pin of the first connection interface unit during the period of receiving the third power supply voltage through the channel configuration pin of the first connection interface unit, the power management circuit receives the first power supply voltage through the first power pin of the first connection interface unit and supplies output voltage to the memory control circuit unit and the rewritable non-volatile memory module.
In an exemplary embodiment of the invention, when the external power supply device is electrically connected to the second connection interface unit, the power management circuit transmits a first mode switching request to the host device, wherein the host device switches to a power receiving mode according to the first mode switching request; and when the external power supply device is electrically disconnected with the second connection interface unit, the power management circuit transmits a second mode switching request to the host device, wherein the host device is switched into a power supply mode according to the second mode switching request.
In an exemplary embodiment of the invention, the power management circuit includes a power input terminal, a first switch circuit, a second switch circuit and a third switch circuit. The first end of the first switch circuit is coupled to the power input end, and the second end of the first switch circuit is coupled to the first power pin of the first connection interface unit. The first end of the second switch circuit is coupled to the power input end, and the second end of the second switch circuit is coupled to the second power pin of the second connection interface unit. The first end of the third switch circuit is coupled to the power input end, and the second end of the third switch circuit is coupled to the configuration channel pin of the first connection interface. The memory control circuit unit and the rewritable non-volatile memory module are coupled to the power input end.
In an exemplary embodiment of the invention, when the second power supply voltage is detected at the second power pin of the second connection interface unit, the power management circuit turns on the second switch circuit to receive the second power supply voltage from the external power supply device through the second power pin of the second connection interface unit and to supply the output voltage to the memory control circuit unit and the rewritable non-volatile memory module through the power output terminal.
In an exemplary embodiment of the invention, when detecting that the second connection interface unit is electrically disconnected from the external power supply device, the power management circuit turns off the second switch, and turns on the third switch circuit to receive the third power supply voltage through the channel configuration pin of the first connection interface unit and supply the output voltage to the memory control circuit unit and the rewritable non-volatile memory module through the power output terminal.
In an exemplary embodiment of the invention, when the first power supply voltage is detected on the first power pin of the first connection interface unit, the power management circuit turns off the third switch, and turns on the first switch circuit to receive the first power supply voltage through the first power pin of the first connection interface unit and supply the output voltage to the memory control circuit unit and the rewritable non-volatile memory module through the power output terminal.
In an exemplary embodiment of the invention, the power management circuit further includes a power control circuit, a power detection circuit and a power switching circuit. The power detection circuit is coupled to the power control circuit and coupled to the second terminal of the first switch circuit, the second terminal of the second switch circuit and the second terminal of the third switch circuit. The power switching circuit is coupled to the power control circuit and is coupled to the control terminal of the first switch circuit, the control terminal of the second switch circuit and the control terminal of the third switch circuit. When the power detection circuit detects the second power supply voltage, the first detection signal is transmitted to the power control circuit, and the power control circuit controls the power switching circuit to turn on the second switch circuit according to the first detection signal. When the power detection circuit does not detect the second power supply voltage, the second detection signal is transmitted to the power control circuit, and the power control circuit controls the power switching circuit to close the second switch circuit and open the third switch circuit according to the second detection signal. When the power detection circuit detects the first power supply voltage, the third detection signal is transmitted to the power control circuit, and the power control circuit controls the power switching circuit to close the third switch circuit and open the first switch circuit according to the third detection signal.
In an exemplary embodiment of the invention, the power management circuit further includes a voltage regulator circuit coupled to the third switch and configured to regulate a third power supply voltage received through the channel configuration pin of the first connection interface unit.
An exemplary embodiment of the present invention provides a power management method for a memory storage device, where the memory storage device includes a rewritable non-volatile memory module, a first connection interface unit, a second connection interface unit, a memory control circuit unit, and a power management circuit. The power management method comprises the following steps: when the first connection interface unit is electrically connected with the host device, the first power supply pin of the first connection interface unit receives a first power supply voltage from the host device and supplies an operation voltage to the memory control circuit unit and the rewritable non-volatile memory module. The power management method further comprises the step of receiving a second power supply voltage from the external power supply device through a second power pin of the second connection interface unit and supplying the output voltage to the memory control circuit unit and the rewritable non-volatile memory module when the external power supply device is electrically connected with the second connection interface unit, wherein the second power supply voltage is supplied to the host device through a first power pin of the first connection interface unit. The power management method also includes: when the external power supply device is electrically disconnected with the second connection interface unit, the power management circuit receives a third power supply voltage through the channel configuration pin of the first connection interface unit and supplies an output voltage to the memory control circuit unit and the rewritable non-volatile memory module. The power management method further comprises: when the first power supply voltage is detected on the first power pin of the first connection interface unit during the period of receiving the third power supply voltage through the channel configuration pin of the first connection interface unit, the first power supply voltage is received through the first power pin of the first connection interface unit and the output voltage is supplied to the memory control circuit unit and the rewritable non-volatile memory module.
In an exemplary embodiment of the invention, the power management method further includes: when the external power supply device is electrically connected with the second connection interface unit, transmitting a first mode switching request to the host device, wherein the host device is switched into a power receiving mode according to the first mode switching request; and when the external power supply device is electrically disconnected with the second connection interface unit, transmitting a second mode switching request to the host device, wherein the host device is switched into a power supply mode according to the second mode switching request.
In an exemplary embodiment of the invention, the power management method further includes: when a second power supply voltage is detected on a second power pin of the second connection interface unit, the second switch circuit is turned on to receive the second power supply voltage from the external power supply device through the second power pin of the second connection interface unit and supply an output voltage to the memory control circuit unit and the rewritable non-volatile memory module through the power output end.
In an exemplary embodiment of the invention, the power management method further includes: when the second connection interface unit is detected to be electrically disconnected with the external power supply device, the second switch is closed, and the third switch circuit is opened to receive the third power supply voltage through the channel configuration pin of the first connection interface unit and supply the output voltage to the memory control circuit unit and the rewritable non-volatile memory module through the power output end.
In an exemplary embodiment of the invention, the power management method further includes: when the first power supply voltage is detected on the first power pin of the first connection interface unit, the third switch is closed, and the first switch circuit is opened to receive the first power supply voltage through the first power pin of the first connection interface unit and supply the output voltage to the memory control circuit unit and the rewritable non-volatile memory module through the power output end.
In an exemplary embodiment of the invention, the power management method further includes: and adjusting the third power supply voltage received by the channel configuration pin of the first connection interface unit.
An exemplary embodiment of the present invention provides a memory storage device, which includes a rewritable non-volatile memory module, a first connection interface unit, a second connection interface unit, a power management circuit, and a memory control circuit unit. The first connection interface unit is used for connecting to a host device. The memory control circuit unit is coupled to the rewritable non-volatile memory, the first connection interface unit and the second connection interface unit. The power management circuit is coupled to the rewritable non-volatile memory module and the memory control circuit unit. When the external power supply device is electrically connected to the second connection interface unit, the power management circuit receives a second power supply voltage from the external power supply device through the second connection interface unit and supplies an operation voltage to the memory control circuit unit and the rewritable non-volatile memory module. When the second connection interface is electrically disconnected with the external power supply device, the power management circuit receives a first power supply voltage from the host device through the first connection interface unit and supplies an operation voltage to the memory control circuit unit and the rewritable non-volatile memory module.
In an exemplary embodiment of the invention, when the external power supply device is electrically connected to the second connection interface unit, the power management circuit transmits a first mode switching request to the host device, wherein the host device switches to the power receiving mode according to the first mode switching request. And when the external power supply device is electrically disconnected with the second connection interface unit, the power management circuit transmits a second mode switching request to the host device, wherein the host device is switched to the power supply mode according to the second mode switching request.
Based on the above, the memory storage device and the power management method thereof according to the exemplary embodiments of the invention can connect or remove the external power supply device to or from the memory storage device while stably maintaining the power supply of the memory storage device when the memory storage device is connected to the host device.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram illustrating a host device and a memory storage device according to an example embodiment;
FIG. 2 is a schematic block diagram of a memory device according to an example embodiment;
FIG. 3 is a schematic block diagram of a memory control circuit unit shown in accordance with an example embodiment;
FIGS. 4 and 5 illustrate exemplary diagrams of managing physically erased cells, according to an exemplary embodiment;
FIG. 6 is a schematic block diagram of a power management circuit according to an exemplary embodiment of the present invention;
FIG. 7 is an operational diagram of a power management circuit according to an example;
FIG. 8 is an operational diagram of a power management circuit according to another example;
FIG. 9 is an operational diagram of a power management circuit according to another example;
FIG. 10 is a flow chart illustrating a method of power management according to an example embodiment.
Description of reference numerals:
11: a host device;
10: a memory storage device;
111: a processor;
112：RAM；
113：ROM；
114: a connection port;
115: a display;
116: a communication chip;
202: a first connection interface unit;
204: a second connection interface unit;
206: a rewritable non-volatile memory module;
208: a memory control circuit unit;
210: a power management circuit;
302: a memory management circuit;
304: a memory interface;
306: a buffer memory;
308: an error checking and correcting circuit;
410(0) to 410 (N): a physical erase unit;
402: an idle area;
406: a system area;
408: a substitution region;
LBA (0) to LBA (h): a logical block address;
LZ (0) to LZ (M): a logical area;
602: a first switching circuit;
604: a second switching circuit;
606: a third switch circuit;
608: a power supply control circuit;
610: a power supply detection circuit;
612: a power switching circuit;
614: a voltage stabilizing circuit;
616: a power supply input terminal;
p1: a first terminal of a first switching circuit;
p2: a second terminal of the first switching circuit;
c1: a control terminal of the first switching circuit;
p3: a first terminal of a second switching circuit;
p4: a second terminal of the second switching circuit;
c2: a control terminal of the second switching circuit;
p5: a first terminal of a third switch circuit;
p6: a second terminal of the third switching circuit;
c3: a control terminal of the third switch circuit;
802: an external power supply device;
s1001: a step of receiving a first power supply voltage from the host device through a first power pin of the first connection interface unit and supplying an operation voltage to the memory control circuit unit and the rewritable non-volatile memory module;
s1003: a step of judging whether an external power supply device is electrically connected with the second connection interface unit;
s1005: a step of receiving a second power supply voltage from the external power supply device through a second power pin of the second connection interface unit and supplying an output voltage to the memory control circuit unit and the rewritable non-volatile memory module, while the second power supply voltage is supplied to the host device through a first power pin of the first connection interface unit;
s1007: step of judging whether the external power supply device is electrically disconnected with the second connection interface unit;
s1009: a step of receiving a third power supply voltage through a channel configuration pin of the first connection interface unit and supplying an output voltage to the memory control circuit unit and the rewritable non-volatile memory module;
s1011: "determining whether the first power supply voltage is detected on the first power pin of the first connection interface unit".
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit unit). Typically, memory storage devices are used with host devices so that the host devices can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host device and a memory storage device according to an example embodiment.
Referring to fig. 1, a host device 11 is a mobile electronic device, such as a smart phone. The host device 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, a connection port 114, a display 115, and a communication chip 116.
In the exemplary embodiment, host device 11 is coupled to memory storage device 10 through connection port 114. For example, the host device 11 can write data to the memory storage device 10 or read data from the memory storage device 10 through the connection port 114.
FIG. 2 is a schematic block diagram of a memory device according to an example embodiment.
Referring to fig. 2, the memory storage device 10 includes a first connection interface unit 202, a second connection interface unit 204, a rewritable non-volatile memory module 206, a memory control circuit unit 208, and a power management circuit 210.
The first connection interface unit 202 is compatible with a Universal Serial Bus (USB) standard and is used for connecting to the host device 11. For example, the first connection interface unit 202 is a USB 3.1Type-C male connection interface unit.
The second connection interface unit 204 is also compatible with Universal Serial Bus (USB) standard. For example, the second connection interface unit 204 is a USB 3.0Type-a male connection interface unit. In the present exemplary embodiment, a device for supplying power (hereinafter, referred to as an external power supply device) may be connected to the memory storage device 10 through the second connection interface unit 204. For example, the external power supply device may be a computer, a charger, a mobile power supply, or the like.
The rewritable nonvolatile memory module 206 is coupled to the memory control circuit unit 208 and is used for storing data written by the host device 11. The rewritable non-volatile memory module 206 has physically erasable units 410(0) -410 (N). For example, the physical erase units 410(0) -410 (N) may belong to the same memory die (die) or to different memory dies. Each of the plurality of physical erase units has a plurality of physical program units, wherein the physical program units belonging to the same physical erase unit can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each of the plurality of physically erased cells may be composed of 64 physically programmed cells, 256 physically programmed cells, or any other number of physically programmed cells.
In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. The physical programming unit is a minimum unit for programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundancy bit region stores system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program unit includes 8 physical access addresses in the data bit region, and one physical access address has a size of 512 bit group (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physically erased cells are physical blocks, and the physically programmed cells are physical pages or physical sectors, but the invention is not limited thereto.
In the exemplary embodiment, the rewritable nonvolatile memory module 206 is a single level Cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 1 data bit in one memory Cell). However, the invention is not limited thereto, and the rewritable non-volatile memory module 206 may also be a Multi-Level Cell (MLC) NAND-type flash memory module (i.e., a flash memory module that can store 2 data bits in one memory Cell), a Triple Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module that can store 3 data bits in one memory Cell), or other memory modules with the same characteristics.
The memory control circuit unit 208 is used for executing a plurality of logic gates or control commands implemented by hardware or software, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 206 according to commands of the host device 11.
The power management circuit 210 is coupled to the memory management circuit 302 and is used for controlling the power of the memory storage device 10.
For example, in an exemplary embodiment, when the memory device 10 is electrically connected to the host device 11 through the first interface connection unit 202, the power management circuit 210 receives a power supply voltage (hereinafter referred to as a first power supply voltage) through the first interface connection unit 202 and provides an operation voltage to the rewritable nonvolatile memory module 206 and the memory control circuit unit 208 according to the first power supply voltage, so that the memory control circuit unit 208 initializes and performs a memory access operation. At this time (i.e., under the condition that the memory device 10 is electrically connected to the host device 11), when the external power supply device is electrically connected to the memory storage device 10 through the second interface connection unit 204, the power management circuit 210 receives a power supply voltage (hereinafter referred to as a second power supply voltage) through the second interface connection unit 204, and provides an operation voltage to the rewritable nonvolatile memory module 206 and the memory control circuit unit 208 according to the second power supply voltage, and the second power supply voltage is provided to the host device 11 through the first interface connection unit 202.
In more detail, when the memory device 10 is electrically connected to the host device 11 through the first interface connection unit 202, the host device 11 negotiates with the memory storage device 10 to determine the roles of each other according to the USB specification. After the negotiation confirms that the host device 11 is the master and the memory storage device 10 is the slave, the power management circuit 210 receives power from the host device 11 through the power pin of the first interface connection unit 202 (hereinafter also referred to as the first power pin) according to the USB specification to activate the memory storage device 10 so that the host device 11 can access the host device 11. When the host device 11 is a master device and the memory storage device 10 is a slave device, the power management circuit 210 sends a mode switching request to the host device 11 to request the host device 11 to change its role as a slave device, and receives power from the external power supply device through the power pin of the second interface connection unit 204 (hereinafter also referred to as the second power pin) according to the USB specification, and simultaneously, the power provided by the external power supply device is input to the host device 11 through the power pin of the first interface connection unit 202, so that the host device 11 can be charged. That is, when the external power supply device is not electrically connected to the memory storage device 10, the host device 11 is in a power supply mode to provide power to the memory storage device 10; when the external power supply device is electrically connected to the memory storage device 10, the host device 11 is in a power receiving mode for performing a charging operation.
In particular, in the exemplary embodiment, when the external power supply device electrically connected to the memory storage device 10 through the second interface connection unit 204 is removed (i.e., the external power supply device is electrically disconnected from the memory storage device 10), the power management circuit 210 receives a power supply voltage (hereinafter referred to as a third power supply voltage) as a standby power through the channel configuration pin of the first interface connection unit 202 and provides an operation voltage to the rewritable nonvolatile memory module 206 and the memory control circuit unit 208 according to the third power supply voltage, and the power management circuit 210 sends a mode switching request to the host device 11 to request the host device 11 to change its role as a master. After the host device 11 is switched to the host device again according to the USB specification, the power management circuit 210 receives the first power supply voltage from the host device 11 through the power pin of the first interface connection unit 202 according to the USB specification and provides the operation voltage to the rewritable non-volatile memory module 206 and the memory control circuit unit 208 according to the first power supply voltage to continue to maintain the operation.
FIG. 3 is a schematic block diagram of a memory control circuit unit according to an example embodiment.
Referring to FIG. 3, the memory control circuit unit 208 includes a memory management circuit 302, a memory interface 304, a buffer 306, and an error checking and correcting circuit 308.
The memory management circuit 302 is used to control the overall operation of the memory control circuit unit 208. Specifically, memory management circuit 302 has a plurality of control commands, and when memory storage device 10 is in operation, the control commands are executed to perform data writing, reading, and erasing operations.
In the exemplary embodiment, the control instructions of memory management circuit 302 are implemented in software. For example, the memory management circuit 302 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
FIGS. 4 and 5 illustrate exemplary diagrams of managing physically erased cells, according to an exemplary embodiment.
It should be understood that, when describing the operation of the physically erased cells of the rewritable non-volatile memory module 206, it is a logical concept to operate the physically erased cells by the terms "extract", "group", "partition", "associate", and the like. That is, the physical locations of the physical erase units of the rewritable non-volatile memory module are not changed, but the physical erase units of the rewritable non-volatile memory module are logically operated.
Referring to FIG. 4, the memory control circuit unit 208 (or the memory management circuit 302) logically groups the physical erase units 410(0) -410 (N) into a data area 402, an idle area 404, a system area 406 and a replacement area 408.
The physically erased cells logically belonging to the data area 402 and the idle area 404 are used for storing data from the host device 11. Specifically, the physical erase units in the data area 402 are regarded as the physical erase units with stored data, and the physical erase units in the idle area 404 are used to replace the physical erase units in the data area 402. That is, when receiving a write command and data to be written from the host device 11, the memory control circuit unit 208 (or the memory management circuit 302) writes the data by using the physical erase unit extracted from the idle area 404 to replace the physical erase unit in the data area 402.
The physically erased cells logically belonging to the system area 406 are used for recording system data. For example, the system data includes information about the manufacturer and model of the rewritable non-volatile memory module, the number of erase units of the rewritable non-volatile memory module, the number of programmed units of each erase unit, and so on.
The physically erased cells logically belonging to the replacement area 408 are used in the bad-physically-erased-cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are still normal physically erased cells in the replacement area 408 and the physically erased cells in the data area 402 are damaged, the memory control circuit unit 208 (or the memory management circuit 302) extracts the normal physically erased cells from the replacement area 408 to replace the damaged physically erased cells.
In particular, the number of physically erased cells in the data area 402, the idle area 404, the system area 406 and the replacement area 408 may vary according to different memory specifications. Moreover, it should be understood that during operation of memory storage device 10, the grouping relationship of physically erased cells associated with data region 402, idle region 404, system region 406, and replacement region 408 may dynamically change. For example, when the physically erased cells in the idle area 404 are damaged and replaced by the physically erased cells in the replacement area 408, the physically erased cells in the replacement area 408 are associated with the idle area 404.
Referring to fig. 5, the memory control circuit unit 208 (or the memory management circuit 302) allocates logical block addresses LBA (0) -LBA (h) to map the physical erase units of the data area 402, where each logical block address has a plurality of logical addresses to map the physical program units of the corresponding physical erase units. Moreover, when the host device 11 intends to write data to the logical address or update the data stored in the logical address, the memory control circuit unit 208 (or the memory management circuit 302) extracts a physical erase unit from the idle area 404 as an active physical erase unit to write data, so as to replace the physical erase unit of the data area 402. Moreover, when the physical erase unit as the active physical erase unit is full, the memory control circuit unit 208 (or the memory management circuit 302) will extract the empty physical erase unit from the idle area 404 as the active physical erase unit to continue writing the update data corresponding to the write command from the host device 11. In addition, when the number of the available physical erase units in the idle area 404 is smaller than the predetermined value, the memory control circuit unit 208 (or the memory management circuit 302) performs a garbage collection (garbage collection) operation (also referred to as an active data merge operation) to arrange the active data in the data area 402, so as to re-associate the physical erase units in the data area 402 that do not store the active data with the idle area 404.
In order to identify the physical program unit in which the data of each logical address is stored, in the present exemplary embodiment, the memory control circuit unit 208 (or the memory management circuit 302) records the mapping relationship between the logical address and the physical program unit. For example, in the present exemplary embodiment, the memory control circuit unit 208 (or the memory management circuit 302) stores a logical address-physical address mapping table in the rewritable non-volatile memory module 206 to record the physical programming unit mapped by each logical address. When data is to be accessed, the memory control circuit unit 208 (or the memory management circuit 302) loads the logical address-physical address mapping table into the buffer memory 306 for maintenance, and writes or reads data according to the logical address-physical address mapping table.
It should be noted that, since the capacity of the buffer memory 306 is limited and cannot store a mapping table for recording mapping relationships of all logical addresses, in the exemplary embodiment, the memory control circuit unit 208 (or the memory management circuit 302) groups the logical block addresses LBA (0) -LBA (h) into a plurality of logical zones LZ (0) -LZ (m), and configures a logical address-physical address mapping table for each logical zone. In particular, when the memory control circuit unit 208 (or the memory management circuit 302) wants to update the mapping of a logical block address, the logical address-physical address mapping table corresponding to the logical area to which the logical block address belongs is loaded into the buffer memory 306 for updating.
In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 302 can also be stored in the form of program codes in a specific area of the rewritable non-volatile memory module 206 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 302 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a driver code, and when the memory control circuit unit 208 is enabled, the microprocessor unit first executes the driver code segment to load the control instruction stored in the rewritable nonvolatile memory module 206 into the ram of the memory management circuit 302. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 302 may also be implemented in hardware. For example, the memory management circuit 302 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used for managing the physical erase cells of the rewritable non-volatile memory module 206; the memory write-in circuit is used for issuing a write-in command to the rewritable non-volatile memory module 206 so as to write data into the rewritable non-volatile memory module 206; the memory reading circuit is used for sending a reading instruction to the rewritable non-volatile memory module 206 so as to read data from the rewritable non-volatile memory module 206; the memory erasing circuit is used for issuing an erasing instruction to the rewritable non-volatile memory module 206 so as to erase data from the rewritable non-volatile memory module 206; the data processing circuit is used for processing data to be written into the rewritable non-volatile memory module 206 and data read from the rewritable non-volatile memory module 206.
Referring to fig. 3 again, the memory interface 304 is coupled to the memory management circuit 302 and is used for accessing the rewritable nonvolatile memory module 206. That is, the data to be written into the rewritable nonvolatile memory module 206 is converted into a format accepted by the rewritable nonvolatile memory module 206 through the memory interface 304.
The buffer memory 306 is coupled to the memory management circuit 302 and is used for temporarily storing temporary data and instructions from the host device 11 or data from the rewritable non-volatile memory module 206.
The error checking and correcting circuit 308 is coupled to the memory management circuit 302 and is used for performing an error checking and correcting process to ensure the correctness of data. For example, when the memory management circuit 302 receives a write command from the host device 11, the Error Checking and Correcting circuit 308 generates an Error Checking and Correcting Code (ECC Code) corresponding to the data corresponding to the write command, and the memory management circuit 302 writes the data corresponding to the write command and the corresponding ECC Code into the rewritable nonvolatile memory module 206. Thereafter, when the memory management circuit 302 reads data from the rewritable non-volatile memory module 206, the corresponding error checking and correcting code is simultaneously read, and the error checking and correcting circuit 308 performs an error checking and correcting procedure on the read data according to the error checking and correcting code.
FIG. 6 is a schematic block diagram of a power management circuit according to an exemplary embodiment of the present invention.
Referring to fig. 6, the power management circuit 210 includes a first switch circuit 602, a second switch circuit 604, a third switch circuit 606, a power control circuit 608, a power detection circuit 610, a power switching circuit 612, a voltage stabilizing circuit 614, and a power input terminal 616.
The first switch circuit 602 includes a first terminal P1, a second terminal P2 and a control terminal C1, wherein the first terminal P1 is coupled to the power pin of the first connector block 202, the second terminal P2 is coupled to the power input terminal 616, and the control terminal C1 is coupled to the power switch circuit 612.
The second switch circuit 604 includes a first terminal P3, a second terminal P4 and a control terminal C2, wherein the first terminal P3 is coupled to the power pin of the second connection interface unit 204, the second terminal P4 is coupled to the power input terminal 616, and the control terminal C2 is coupled to the power switching circuit 612.
The third switch circuit 606 includes a first terminal P5, a second terminal P6, and a control terminal C3, wherein the first terminal P5 is coupled to the channel allocation pin of the first connection interface unit 202, the second terminal P6 is coupled to the power input terminal 616, and the control terminal C3 is coupled to the power switching circuit 612.
When the memory storage device 10 is not connected to the host device 11, the first switch circuit 602, the second switch circuit 604 and the third switch circuit 606 are in the initial state of being turned off, i.e. none of the first switch circuit 602, the second switch circuit 604 and the third switch circuit 606 are turned on.
The power control circuit 608 is coupled to the power detection circuit 610 and the power switching circuit 612, and is used for controlling the power switching circuit 612 to turn on or off the first switch circuit 602, the second switch circuit 604 and the third switch circuit 606 according to the detection result of the power detection circuit 610.
The power detection circuit 610 detects voltages at the first terminal P1, the first terminal P3 and the first terminal P5, and transmits a detection signal to the power control circuit 608 according to the detection result.
The power switching circuit 612 operates the control terminal C1, the control terminal C2 and the control terminal C3 to turn on or off the first switch circuit 602, the second switch circuit 604 and the third switch circuit 606 according to the indication of the power control circuit 608.
The voltage stabilizing circuit 614 is used for adjusting the voltage received from the channel configuration pins of the first connection interface unit 202. For example, the power pin of the first connection interface unit 202 and the power pin of the second connection interface unit 204 receive a voltage of 5 volts (V) as the operating voltages of the memory control circuit unit 208 and the rewritable nonvolatile memory module 206. As described above, in the exemplary embodiment, the power management circuit 210 uses the power received from the channel allocation pin of the first connection interface unit 202 as the backup power, and the voltage stabilizing circuit 614 adjusts the voltage received from the channel allocation pin of the first connection interface unit 202 to 5V in order to ensure that the voltage received from the channel allocation pin of the first connection interface unit 202 is stable as the operation voltage supplied to the memory control circuit unit 208 and the rewritable nonvolatile memory module 206.
The power input end 616 is coupled to the memory control circuit unit 208 and the rewritable nonvolatile memory module 206 to supply an operating voltage to the memory control circuit unit 208 and the rewritable nonvolatile memory module 206.
FIG. 7 is an operation diagram of a power management circuit according to an example.
Referring to fig. 7, when the user connects the first connection interface unit 202 of the memory storage device 10 to the connection port of the host device 11, the host device 11 performs handshaking (handshaking) with the memory storage device 10 according to the USB specification and confirms that the host device 11 is a master device and the memory storage device 10 is a slave device. Accordingly, the power control circuit 608 transmits a control signal to the power switching circuit 612, and the power switching circuit 612 turns on the control terminal C1 of the first switch circuit 602 according to the control signal to turn on the first switch circuit 602. In this state, the host device 11 is in a host power supply mode, in which the power management circuit 210 receives a power supply voltage (hereinafter referred to as a first power supply voltage) through the power pin of the first connection interface unit 202, and thus supplies an operating voltage to the memory control circuit unit 208 and the rewritable nonvolatile memory module 206 through the power input 616.
FIG. 8 is an operation diagram of a power management circuit according to another example.
Referring to fig. 8, in the host power mode shown in fig. 7, when the user connects the external power supply device 802 to the second connection interface unit 204 of the memory storage device 10, the power detection circuit 610 detects that the power pin of the second connection interface unit 204 receives the power supply voltage (hereinafter referred to as the second power supply voltage), and transmits a detection signal (hereinafter referred to as the first detection signal) to the power control circuit 608. Upon receiving the first detection signal, the power control circuit 608 instructs the power switching circuit 612 to turn off the control terminal C1 of the first switch circuit 602 (i.e., the first switch circuit is in a non-conducting state) and turn on the control terminal C2 of the second switch circuit 604 (i.e., the second switch circuit is in a conducting state). Then, the memory storage device 10 sends a mode switching request (hereinafter referred to as a first mode switching request) according to the USB specification, and when the role of the host device 11 is changed from the master device to the slave device, the power control circuit 608 sends a control signal to the power switching circuit 612, and the power switching circuit 612 turns on the control terminal C1 of the first switch circuit 602 according to the control signal to turn on the first switch circuit 602. In this state, the host device 11 is in the host powered mode, wherein the power management circuit 210 receives the second power supply voltage through the power pin of the second connection interface unit 204, and thus supplies the operation voltage to the memory control circuit unit 208 and the rewritable nonvolatile memory module 206 through the power input 616. In particular, the second power supply voltage is transmitted to the host device 11 through the power pin of the first connection interface unit 202 to charge the host device 11.
FIG. 9 is an operation diagram of a power management circuit according to another example.
Referring to fig. 9, in the host powered mode shown in fig. 8, when the user removes the external power supply device 802 (i.e., the external power supply device 802 is electrically disconnected from the second connection interface unit 204 of the memory storage device 10), the power detection circuit 610 does not detect the second power supply voltage at the power pin of the second connection interface unit 204, and transmits a detection signal (hereinafter referred to as a second detection signal) to the power control circuit 608. Upon receiving the second detection signal, the power control circuit 608 issues a command according to the second detection signal to enable the power switching circuit 612 to turn off the control terminal C2 of the second switch circuit 604 (i.e., the second switch circuit is in a non-conducting state) and turn on the control terminal C3 of the third switch circuit 606 (i.e., the third switch circuit is in a conducting state). In this state, the memory storage device 10 is in a standby power supply mode, in which the power management circuit 210 receives a power supply voltage (hereinafter referred to as a third power supply voltage) through the channel configuration pin of the first connection interface unit 202, and thus supplies an operation voltage to the memory control circuit unit 208 and the rewritable nonvolatile memory module 206 through the power input terminal 616.
Then, the memory storage device 10 sends a mode switching request (hereinafter referred to as a second mode switching request) according to the USB specification, and when the role of the host device 11 is changed from the slave device to the master device, the power control circuit 608 transmits a control signal to the power switching circuit 612, and the power switching circuit 612 turns off the control terminal C3 of the third switch circuit 606 (i.e., the third switch circuit is in a non-conducting state) and turns on the control terminal C1 of the first switch circuit 602 (i.e., the first switch circuit is in a conducting state) according to the control signal, thereby returning to the host power supply mode shown in fig. 7. Generally, during the mode switching process, the memory storage device 10 and the host device 11 will continuously transmit and receive protocol commands to each other, and it takes about 55 milliseconds (ms) to complete the role switching.
Based on the above, in the case of using the memory storage device 10 to expand the host device 11, the user can directly connect the external power supply device 802 to the memory storage device 10 to charge the host device 11, and when the external power supply device 802 is disconnected, the memory storage device 10 can restore the state of supplying power to the host device 11.
FIG. 10 is a flow chart illustrating a method of power management according to an example embodiment.
Referring to fig. 10, when the first connection interface unit 202 is electrically connected to the host device 11, in step S1001, the power management circuit 210 receives a first power supply voltage from the host device 11 through the power pin of the first connection interface unit 202 and supplies an operating voltage to the memory control circuit unit 208 and the rewritable non-volatile memory module 206. That is, in step S1001, the memory storage device 10 enters a host power mode using the host device 11 as a power source, and the host power mode is described in detail with reference to fig. 7, and will not be described again.
In step S1003, the power management circuit 210 determines whether the external power supply device 802 is electrically connected to the second connection interface unit 204. An example of determining that the external power supply device 802 is electrically connected to the second connection interface unit 204 is described above in detail with reference to fig. 8, and will not be described again.
If it is determined that the external power supply 802 is not electrically connected to the second connection interface unit 204, step S1001 is continuously executed.
If the external power supply device 802 is electrically connected to the second connection interface unit 204, in step S1005, the power management circuit 210 receives a second power supply voltage from the external power supply device 802 through the power pin of the second connection interface unit 204 and supplies an output voltage to the memory control circuit unit 208 and the rewritable non-volatile memory module 206, and the second power supply voltage is supplied to the host device 11 through the power pin of the first connection interface unit 202. That is, in step S1005, the memory storage device 10 enters the host power mode, and the example of the host power mode is described in detail with reference to fig. 8, and will not be described again.
Next, in step 1007, the power management circuit 210 determines whether the external power supply device 802 is electrically disconnected from the second connection interface unit 204.
If the external power supply device 802 is not electrically disconnected from the second connection interface unit 204, step S1005 is continuously executed.
If the external power supply device 802 is electrically disconnected from the second connection interface unit 204, in step S1009, the power management circuit 210 receives a third power supply voltage through the channel configuration pins of the first connection interface unit 202 and supplies an output voltage to the memory control circuit unit 208 and the rewritable non-volatile memory module 206. That is, in step S1009, the memory storage device 10 enters the standby power supply mode, and the example of the standby power supply mode is described in detail with reference to fig. 9, and will not be described again.
Next, in step S1011, the power management circuit 210 determines whether the first power supply voltage is detected at the power pin of the first connection interface unit 202.
If the first power supply voltage is not detected on the power pin of the first connection interface unit 202, step S1009 is continuously performed.
If the first power supply voltage is detected on the power pin of the first connection interface unit 202, step S1001 is executed. That is, the memory storage device 10 reverts to the host power mode.
In summary, the memory storage device and the power management method according to the exemplary embodiments of the invention can charge the host device by connecting the external power supply device to the memory storage device when the connection port of the host device is occupied by the memory storage device. For example, when a user protects and expands the capacity of the host device with a protective case embedded with a memory storage device, the user can charge the host device without detaching the protective case, thereby greatly reducing the inconvenience of the user.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (17)
1. A memory storage device, comprising:
a rewritable non-volatile memory module;
the first connection interface unit is used for connecting to a host device and is provided with a first power supply pin and a channel configuration pin;
a second connection interface unit having a second power pin;
a memory control circuit unit; and
a power management circuit for receiving a first power supply voltage from the host device through a first power pin of the first connection interface unit and supplying an operating voltage corresponding to the first power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module,
wherein the memory control circuit unit is coupled to the power management circuit, the rewritable non-volatile memory, the first connection interface unit and the second connection interface unit,
when an external power supply device is electrically connected with the second connection interface unit, the power management circuit receives a second power supply voltage from the external power supply device through the second power pin of the second connection interface unit and supplies an output voltage corresponding to the second power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module, wherein the second power supply voltage is supplied to the host device through the first power pin of the first connection interface unit;
when the external power supply device is electrically disconnected from the second connection interface unit, the power management circuit receives a third power supply voltage through the channel configuration pin of the first connection interface unit and supplies an output voltage corresponding to the third power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module;
during the period of receiving the third power supply voltage through the channel configuration pin of the first connection interface unit, when the first power supply voltage is detected on the first power pin of the first connection interface unit, the power management circuit receives the first power supply voltage through the first power pin of the first connection interface unit and supplies the operation voltage corresponding to the first power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module.
2. The memory storage device of claim 1, wherein the power management circuit transmits a first mode switch request to the host device when the external power supply device is electrically connected to the second connection interface unit, wherein the host device switches to a power receiving mode according to the first mode switch request,
when the external power supply device is electrically disconnected from the second connection interface unit, the power management circuit transmits a second mode switching request to the host device, wherein the host device is switched to a power supply mode according to the second mode switching request.
3. The memory storage device of claim 1, wherein the power management circuit comprises a power input, a first switch circuit, a second switch circuit, and a third switch circuit,
a first terminal of the first switch circuit is coupled to the power input terminal, and a second terminal of the first switch circuit is coupled to the first power pin of the first connection interface unit,
a first terminal of the second switch circuit is coupled to the power input terminal, and a second terminal of the second switch circuit is coupled to the second power pin of the second connection interface unit,
a first terminal of the third switch circuit is coupled to the power input terminal, and a second terminal of the third switch circuit is coupled to the channel allocation pin of the first connection interface unit,
the memory control circuit unit and the rewritable non-volatile memory module are coupled to the power supply input end.
4. The memory storage device of claim 3, wherein when the second power supply voltage is detected at the second power pin of the second connection interface unit, the power management circuit turns on the second switch circuit to receive the second power supply voltage from the external power supply device through the second power pin of the second connection interface unit, and supplies the output voltage corresponding to the second power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module through the power input terminal.
5. The memory storage device of claim 4, wherein when it is detected that the second connection interface unit is electrically disconnected from the external power supply device, the power management circuit turns off the second switch, and turns on the third switch circuit to receive the third power supply voltage through the channel configuration pin of the first connection interface unit and to supply the output voltage corresponding to the third power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module through the power input terminal.
6. The memory storage device of claim 5, wherein when the first power supply voltage is detected at the first power pin of the first connection interface unit, the power management circuit turns off the third switch and turns on the first switch circuit to receive the first power supply voltage through the first power pin of the first connection interface unit and to supply the operation voltage corresponding to the first power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module through the power input terminal.
7. The memory storage device of claim 6, wherein the power management circuit further comprises:
a power control circuit for controlling the power of the power supply,
a power detection circuit coupled to the power control circuit and coupled to the second terminal of the first switch circuit, the second terminal of the second switch circuit, and the second terminal of the third switch circuit,
a power switching circuit coupled to the power control circuit and coupled to a control terminal of the first switch circuit, a control terminal of the second switch circuit and a control terminal of the third switch circuit,
wherein when the power detection circuit detects the second power supply voltage, a first detection signal is transmitted to the power control circuit and the power control circuit controls the power switching circuit to turn on the second switch circuit according to the first detection signal,
wherein when the power detection circuit does not detect the second power supply voltage, a second detection signal is transmitted to the power control circuit and the power control circuit controls the power switching circuit to turn off the second switch circuit and turn on the third switch circuit according to the second detection signal,
when the power detection circuit detects the first power supply voltage, a third detection signal is transmitted to the power control circuit, and the power control circuit controls the power switching circuit to close the third switch circuit and open the first switch circuit according to the third detection signal.
8. The memory storage device of claim 7, wherein the power management circuit further comprises:
a voltage regulator circuit coupled to the third switch for regulating the third power supply voltage received through the channel configuration pin of the first connection interface unit.
9. A power management method is used for a memory storage device, the memory storage device comprises a rewritable non-volatile memory module, a first connection interface unit, a second connection interface unit, a memory control circuit unit and a power management circuit, the power management method comprises the following steps:
when the first connection interface unit is electrically connected with a host device, a first power supply pin of the first connection interface unit receives a first power supply voltage from the host device and supplies an operation voltage to the memory control circuit unit and the rewritable non-volatile memory module;
when an external power supply device is electrically connected with the second connection interface unit, receiving a second power supply voltage from the external power supply device through a second power pin of the second connection interface unit and supplying an output voltage corresponding to the second power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module, wherein the second power supply voltage is supplied to the host device through the first power pin of the first connection interface unit;
when the external power supply device is electrically disconnected from the second connection interface unit, the power management circuit receives a third power supply voltage through a channel configuration pin of the first connection interface unit and supplies an output voltage corresponding to the third power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module; and
during the period of receiving the third power supply voltage through the channel configuration pin of the first connection interface unit, when the first power supply voltage is detected on the first power pin of the first connection interface unit, receiving the first power supply voltage through the first power pin of the first connection interface unit and supplying the operation voltage corresponding to the first power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module.
10. The power management method of claim 9, further comprising:
when the external power supply device is electrically connected with the second connection interface unit, a first mode switching request is transmitted to the host device, wherein the host device is switched to a power receiving mode according to the first mode switching request,
when the external power supply device is electrically disconnected from the second connection interface unit, a second mode switching request is transmitted to the host device, wherein the host device is switched to a power supply mode according to the second mode switching request.
11. The power management method of claim 9, wherein the power management circuit comprises a power input, a first switch circuit, a second switch circuit and a third switch circuit,
a first terminal of the first switch circuit is coupled to the power input terminal, and a second terminal of the first switch circuit is coupled to the first power pin of the first connection interface unit,
a first terminal of the second switch circuit is coupled to the power input terminal, and a second terminal of the second switch circuit is coupled to the second power pin of the second connection interface unit,
a first terminal of the third switch circuit is coupled to the power input terminal, and a second terminal of the third switch circuit is coupled to the channel allocation pin of the first connection interface,
the memory control circuit unit and the rewritable non-volatile memory module are coupled to the power supply input end.
12. The power management method of claim 11, further comprising:
when the second power supply voltage is detected on the second power pin of the second connection interface unit, the second switch circuit is turned on to receive the second power supply voltage from the external power supply device through the second power pin of the second connection interface unit and supply the output voltage corresponding to the second power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module through the power input terminal.
13. The power management method of claim 12, further comprising:
when detecting that the second connection interface unit is electrically disconnected from the external power supply device, the second switch is turned off, and the third switch circuit is turned on to receive the third power supply voltage through the channel configuration pin of the first connection interface unit and supply the output voltage corresponding to the third power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module through the power input terminal.
14. The power management method of claim 13, further comprising:
when the first power supply voltage is detected on the first power pin of the first connection interface unit, the third switch is turned off, and the first switch circuit is turned on to receive the first power supply voltage through the first power pin of the first connection interface unit and supply the operation voltage corresponding to the first power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module through the power input terminal.
15. The power management method of claim 14, further comprising:
adjusting the third power supply voltage received through the channel configuration pin of the first connection interface unit.
16. A memory storage device, comprising:
a rewritable non-volatile memory module;
the first connection interface unit is used for connecting to a host device and is provided with a first power supply pin;
a second connection interface unit having a second power pin; and
the memory control circuit unit is coupled to the rewritable non-volatile memory, the first connection interface unit and the second connection interface unit;
a power management circuit coupled to the rewritable non-volatile memory module and the memory control circuit unit,
wherein when an external power supply device is electrically connected to the second connection interface unit, the power management circuit receives a second power supply voltage from the external power supply device through the second power pin of the second connection interface unit and supplies an operating voltage corresponding to the second power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module, wherein the second power supply voltage is supplied to the host device through the first power pin of the first connection interface unit,
when the second connection interface is electrically disconnected from the external power supply device, the power management circuit receives a first power supply voltage from the host device through the first connection interface unit and supplies an operating voltage corresponding to the first power supply voltage to the memory control circuit unit and the rewritable non-volatile memory module.
17. The memory storage device of claim 16, wherein the power management circuit transmits a first mode switch request to the host device when the external power supply device is electrically connected to the second connection interface unit, wherein the host device switches to a power receiving mode according to the first mode switch request,
when the external power supply device is electrically disconnected from the second connection interface unit, the power management circuit transmits a second mode switching request to the host device, wherein the host device is switched to a power supply mode according to the second mode switching request.
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| JP5152785B2 (en) * | 2008-01-28 | 2013-02-27 | ソニーオプティアーク株式会社 | Peripheral device, operation method of peripheral device, electronic device system |
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| US6532500B1 (en) * | 2000-01-24 | 2003-03-11 | Dell Products L.P. | System and method to support out-band storage subsystem management via SCSI bus when operating power to a computer system is off |
| CN101359316A (en) * | 2007-08-03 | 2009-02-04 | 大唐移动通信设备有限公司 | Method and apparatus for implementing general-purpose serial bus USB OTG |
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