CN107396008A - A kind of cmos image sensor low noise reading circuit and its reading method - Google Patents
A kind of cmos image sensor low noise reading circuit and its reading method Download PDFInfo
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- CN107396008A CN107396008A CN201710565831.7A CN201710565831A CN107396008A CN 107396008 A CN107396008 A CN 107396008A CN 201710565831 A CN201710565831 A CN 201710565831A CN 107396008 A CN107396008 A CN 107396008A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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Abstract
The invention discloses a kind of cmos image sensor low noise reading circuit and its reading method, the reading circuit includes signal multiple repairing weld module, signal integration module and signal averaging module, the signal integration module both ends connect the signal multiple repairing weld module and signal averaging module respectively, the other end of the signal integration module is signal input part, the other end of the signal averaging module is signal output part, the signal multiple repairing weld module, which treats process signal progress multiple repairing weld processing and transmits it to the signal integration module, carries out integration summation, integration summing signal is transmitted to the signal averaging module again and averaged, finally average value signal is exported by signal output part.A kind of cmos image sensor low noise reading circuit provided by the invention, can effectively reduce PIXEL equivalent input noises, especially suitable for low photoenvironment, picture quality can be effectively improved, suitable for promoting the use of.
Description
Technical field
The present invention relates to field of image sensors, and in particular to a kind of cmos image sensor low noise reading circuit and its
Reading method.
Background technology
In field of image sensors, it is an eternal theme to improve picture quality.The photoreceptor signal of imaging sensor exists
Can be by miscellaneous noise source in transmission so that signal to noise ratio is difficult to improve.Noise can cause image various FPN occur
(solid-state noise) and various random bright spots or dim spot.Especially under low light situation, because photogenerated current is smaller, signal holds very much
Easily it is submerged in noise, the problem of low photoenvironment hypograph quality is particularly poor occurs.
The method used in the prior art to noise processed is CDS technology, i.e. Correlated Double Sampling, and this method is in CMOS
Field of image sensors is widely used, and the technology can reduce the FPN and source follower noise of pixel cell, but this method is low
Effect is limited under photoenvironment, it is impossible to improves the image quality issues under low luminous environment.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of cmos image sensor low noise reading circuit and its reading
Go out method, the low noise reading circuit can effectively reduce PIXEL equivalent input noises, especially suitable for low photoenvironment, energy
Picture quality is effectively improved, suitable for promoting the use of.
To achieve these goals, the present invention adopts the following technical scheme that：A kind of cmos image sensor low noise is read
Circuit, wherein, including signal multiple repairing weld module, signal integration module and signal averaging module, the signal integration module two
End connects the signal multiple repairing weld module and signal averaging module respectively, and the other end of the signal multiple repairing weld module is letter
Number input, the other end of the signal averaging module is signal output part, and the signal multiple repairing weld module is to pending letter
Number M sampling processing is carried out, M is integer more than 1.
Further, the signal integration module carries out integration summation to the signal after M sampling, and exports integration summation
Signal.
Further, the signal averaging module is averaged to the integration summing signal, and exports average value signal.
Further, the signal multiple repairing weld module includes first switch, second switch, third switch, the 4th switch
With the first electric capacity, wherein, signal input part is connected with one end of the first switch, the other end of the first switch and institute
State one end of the first electric capacity and one end of the second switch to be connected with each other, the other end and reference voltage of the second switch
Be connected, the other end of first electric capacity with described three, the 4th switch one end be connected with each other, it is described 3rd switch it is another
Outer one end is connected with the signal integration module, and the other end of the 4th switch is connected with ground level.
Further, the signal integration module includes operational amplifier, and the 5th switch and the second electric capacity are formed；Wherein,
The negative input of the operational amplifier and the other end of the described 3rd switch, one end and described the of the 5th switch
One end of two electric capacity is connected with each other；The positive input of the operational amplifier is connected with ground level, its output end and described the
The other end of five switches and the other end of second electric capacity are connected with each other.
Further, the signal averaging module includes the 6th switch, the 7th switch, the 8th switch, the 3rd electric capacity and the
Four electric capacity；Wherein, one end of the 6th switch is connected with the output end of the operational amplifier, its other end and described the
One end of three electric capacity and one end of the 7th switch are connected with each other, and the other end of the 3rd electric capacity is connected with ground level,
The other end of 7th switch is connected with each other with one end of the described 8th switch and one end of the 4th electric capacity, and described the
The other end of eight switches and the other end of the 4th electric capacity are connected with ground level.
Further, the capacitance of the 4th electric capacity is M-1 times of the capacitance of the 3rd electric capacity.
A kind of reading method of cmos image sensor low noise reading circuit, step are as follows：
S01：Pending signal is inputted by signal input part, signal multiple repairing weld module is carried out to the pending signal
M sampling processing simultaneously transmits the signal after sampling to signal integration module, and M is the integer more than 1；
S02：The signal integration module carries out integration summation to the signal after the sampling, and exports integration summing signal
To signal averaging module；
S03：The signal averaging module is averaged to the integration summing signal, and is exported and put down by signal output part
Mean value signal.
Further, when pending signal is voltage signal, the integration summing signal is
Wherein,For average voltage of the pending signal after M sampling, VREFFor reference voltage.
Further, when pending signal is voltage signal, the average value signal isIts
In,For average voltage of the pending signal after M sampling, VREFFor reference voltage.
Beneficial effects of the present invention are：A kind of cmos image sensor low noise reading circuit provided by the invention passes through more
The method that secondary sample integration summation is averaged again is handled picture element signal, can effectively reduce PIXEL equivalent inpnts
Noise, especially suitable for low photoenvironment, picture quality can be effectively improved, suitable for promoting the use of.
Brief description of the drawings
Fig. 1 is a kind of structural representation of cmos image sensor low noise reading circuit of the present invention.
Fig. 2 is circuit diagram corresponding to this patent embodiment 1.
Fig. 3 is timing diagram corresponding to this patent embodiment 1.
In figure, 1 signal multiple repairing weld module, 2 signal integration modules, 3 signal averaging modules.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with the accompanying drawings to the specific reality of the present invention
The mode of applying is described in further detail.
As shown in figure 1, a kind of cmos image sensor low noise reading circuit provided by the invention, including signal are repeatedly adopted
Egf block 1, signal integration module 2 and signal averaging module 3, signal integration module both ends connect signal multiple repairing weld module respectively
With signal averaging module, the other end of signal integration module is signal input part, and the other end of signal averaging module is defeated for signal
Go out end, pending signal passes through signal input part entering signal multiple repairing weld module, and signal multiple repairing weld module is to pending letter
Number carry out M sampling processing and transmit the signal after sampling to signal integration module, after signal integration module samples to M times
Signal carries out integration summation, and integration summing signal is transmitted to signal averaging module, and signal averaging module is to integration summation letter
Number average, and average value signal is exported by signal output part, M is the integer more than 1.
The reading method of a kind of cmos image sensor low noise reading circuit provided by the invention, when pending signal is
During voltage, step is as follows：
S01：Pending signal is inputted by signal input part, signal multiple repairing weld module is treated process signal and carried out M times
Sampling processing is simultaneously transmitted to the signal integration module, and M is the integer more than 1.
S02：Signal integration module carries out integration summation to acquisition process signal, and exports integration sum voltages signalTo signal averaging module, wherein, M is the number sampled in signal multiple repairing weld module,For
Average voltage of the pending signal after M sampling, VREFFor reference voltage.
S03：Signal averaging module is used to average to above-mentioned integration sum voltages, and is exported and put down by signal output part
Average voltage signal, wherein,
As shown in figure 1, signal multiple repairing weld module 1 includes first switch SW1, second switch SW2, the 3rd switch SW3, the
Four switch SW4 and the first electric capacity C1.Wherein, signal input part PIXEL_IN is connected with first switch SW1 one end, first switch
SW1 other end is connected with each other with the first electric capacity C1 one end and second switch SW2 one end.Second switch SW2 is in addition
One end and reference voltage VREFIt is connected.First electric capacity C1 other end and the 3rd switch SW3 and the 4th switch SW4 one end phase
Connect.3rd switch SW3 other end is connected with signal integration module 2.4th switch SW4 other end and ground level
VSS is connected.
Signal integration module 2 includes operational amplifier OPA1, the 5th switch SW5, the second electric capacity C2.Wherein, operation amplifier
One end of device OPA1 negative input and the 3rd switch SW3 other end, the 5th switch SW5 one end and the second electric capacity C2
It is connected with each other.Operational amplifier OPA1 positive input is connected with ground level VSS, and its output end is another with the 5th switch SW5's
Outer one end and the second electric capacity C2 other end are connected with each other.
Signal averaging module includes the 6th switch SW6, the 7th switch SW7, the 8th switch SW8, the 3rd electric capacity C3 and the 4th
Electric capacity C4 is formed.Wherein, the 4th electric capacity C4 capacitance is M-1 times of the 3rd electric capacity C3, and wherein M is signal multiple repairing weld module
The middle number sampled.6th switch SW6 one end is connected with operational amplifier OPA1 output end, its other end and the
Three electric capacity C3 one end and the 7th switch SW7 one end are connected with each other.3rd electric capacity C3 other end and ground level VSS phases
Even.7th switch SW7 other end is connected with each other with the 8th switch SW8 one end and the 4th electric capacity C4 one end and is used as this
The signal output part of invention reading circuit.8th switch SW8 other end and the 4th electric capacity C4 other end are electric with ground
Flat VSS is connected.
A kind of cmos image sensor low noise reading circuit and its reading method provided by the invention can be directed to voltage
Signal, current signal or other signals transmitted in circuit can also be directed to.
A kind of reading method of cmos image sensor low noise reading circuit provided by the invention, using voltage signal as
Example, step are as follows：
S01：The switches of first switch SW1 and the 4th SW4 is first controlled to open, the first electric capacity C1 being connected with first switch SW1
One terminal voltage is changed into V, and other end is ground level 0；Control second switch SW2 and the 3rd to switch SW3 again to open, with second switch
First connected SW2 electric capacity C1 one end is changed into reference voltage VREF, other end is connected with operational amplifier negative input, by
This is realized samples to the first time of pending voltage signal.So circulation is carried out M times, completes M times to pending voltage signal
Correlated sampling.
S02：Integration summation is carried out to the signal of above-mentioned multiple repairing weld processing, the output end voltage of operational amplifier is：Wherein, M is the number sampled in signal multiple repairing weld module,Pass through for pending signal
Average voltage after M sampling, VREFFor reference voltage.
S03：The 6th switch SW6 and the 8th switch SW8 shut-offs are controlled, subsequent 3rd electric capacity C3 is in parallel with the 4th electric capacity C4, C3
On electric charge and C4 mean allocations, due to C4=(M-1) * C3, therefore, mean voltage signal is：
Now, VOUT exports the average value of M correlated sampling of pending voltage signal, gives analog-digital converter ADC afterwards and treats place
Manage signal and carry out analog-to-digital conversion；
Become apparent from order that obtaining protection scope of the present invention, specifically describe reading circuit pair of the present invention by the following examples
The flow and method that PIXEL RESET signal and SIGNAL signals is read.
Embodiment 1
As shown in Figure 2 and Figure 3, reading circuit proposed by the present invention is connected with standard 4T PIXEL, and connects with light sensitive diode
The metal-oxide-semiconductor connect is M1, M2, M3 and M4, wherein, the upper additional TX signals of M1, the upper additional RST signals of M2, the upper additional RS signals of M4,
Additional Φ on the additional signals of Φ 2 on the additional signals of Φ 1 on SW1 and SW4, SW2 and SW3, the upper additional Φ R signals of SW5, SW6 and SW8
3 signals, the upper additional signals of Φ 4 of SW7, specific reading method step are as follows：
Step 1：After exposition, RST is changed into high level to light sensitive diode PD from low level, becomes again from high level afterwards
Low level, there is a high impulse in Φ R in the time interval, keep low level afterwards.Φ 3 is changed into high level from low level, makes
Obtain the 6th switch SW6 and the 8th switch SW8 conductings.
Step 2：RS is changed into high level from low level, and RESET signal is exported by M4 source electrode.
Step 3：Control signal Φ 1 and Φ 2 is the non-overlapping clock of a pair of two-phases, and the high impulses of Φ 1 arrive first at, and opens first
The switch SW4 of SW1 and the 4th are switched, the terminal voltages of the first electric capacity C1 mono- being connected with first switch SW1 are changed into VRESET1, other end
For ground level 0；The high impulses of Φ 2 reach afterwards, and Φ 1 keeps low level, the switch SW3 of second switch SW2 and the 3rd are opened, with second
First connected switch SW2 electric capacity C1 one end is changed into reference voltage VREF, other end and operational amplifier negative input phase
Even, it is achieved in the first correlated sampling to RESET signal.So circulation is carried out M times, completes the M correlation to RESET signal
Sampling and integration summation；
After Φ 1 and Φ 2 keep low level, the integration sum voltages signal of OPA1 output ends is：
In formula 1For average voltage of the RESET signal after M sampling.
Step 4：Φ 3 is changed into low level, the 6th switch SW6 and the 8th switch SW8 shut-offs, subsequent Φ 4 from high level afterwards
High level is changed into from low level, the 3rd electric capacity C3 is in parallel with the 4th electric capacity C4.Electric charge and C4 mean allocations on C3, due to C4=
(M-1) * C3, therefore, mean voltage signal is：
Now, VOUT1The average value of M correlated sampling of RESET signal is exported, gives ADC pairs of analog-digital converter afterwards
RESET signal carries out analog-to-digital conversion.
Step 5：There is a high impulse in Φ R, keep low level afterwards, Φ 3 is changed into high level from low level so that the 6th
The switch SW8 conductings of SW6 and the 8th are switched, Φ 4 is changed into low level from high level before, and TX signals are changed into high electricity from low level
It is flat, PIXEL output SIGNAL signals.
Step 6：Control signal Φ 1 and Φ 2 is the non-overlapping clock of a pair of two-phases, and the high impulses of Φ 1 arrive first at, and opens first
The switch SW4 of SW1 and the 4th are switched, the terminal voltages of the first electric capacity C1 mono- being connected with first switch SW1 are changed into VSIGNAL1, other end
For ground level 0；The high impulses of Φ 2 reach afterwards, and Φ 1 keeps low level, the switch SW3 of second switch SW2 and the 3rd are opened, with second
First connected switch SW2 electric capacity C1 one end is changed into reference voltage VREF, other end and operational amplifier negative input phase
Even, it is achieved in the first correlated sampling to SIGNAL signals.So circulation is carried out M times, completes the M phase to SIGNAL signals
Close sampling and integration summation.
After Φ 1 and Φ 2 keep low level, the integration sum voltages signal of OPA1 outputs is：
In formula 3For average voltage of the SIGNAL signals after M sampling.
Step 7：Φ 3 is changed into low level, the 6th switch SW6 and the 8th switch SW8 shut-offs, subsequent Φ 4 from high level afterwards
High level is changed into from low level, the 3rd electric capacity C3 is in parallel with the 4th electric capacity C4.Electric charge and C4 mean allocations on C3, due to C4=
(M-1) * C3, therefore, mean voltage signal is：
Now, VOUT2The average value of M correlated sampling of SIGNAL signals is exported, gives ADC pairs of analog-digital converter afterwards
SIGNAL signals carry out analog-to-digital conversion.
Step 8：By VOUT1And VOUT2Complete the digital value after analog-to-digital conversion and ask poor, you can obtain the illumination letter of low noise
Number conversion value.
The preferred embodiments of the present invention are the foregoing is only, the embodiment is not intended to limit the patent protection of the present invention
Scope, therefore the equivalent structure change that every specification and accompanying drawing content with the present invention is made, similarly should be included in this
In the protection domain of invention appended claims.
Claims (10)
1. a kind of cmos image sensor low noise reading circuit, it is characterised in that accumulated including signal multiple repairing weld module, signal
Sub-module and signal averaging module, the signal integration module both ends connect the signal multiple repairing weld module and the letter respectively
Number averaging module, the other end of the signal multiple repairing weld module are signal input part, the other end of the signal averaging module
For signal output part, the signal multiple repairing weld module treats process signal and carries out M sampling, and M is the integer more than 1.
A kind of 2. cmos image sensor low noise reading circuit according to claim 1, it is characterised in that the signal
Integration module carries out integration summation to the signal after M sampling, and exports integration summing signal.
A kind of 3. cmos image sensor low noise reading circuit according to claim 2, it is characterised in that the signal
Averaging module is averaged to the integration summing signal, and exports average value signal.
A kind of 4. cmos image sensor low noise reading circuit according to claim 1, it is characterised in that the signal
Multiple repairing weld module includes first switch, second switch, third switch, the 4th switch and the first electric capacity, wherein, signal input part
It is connected with one end of the first switch, the other end of the first switch and one end and described second of first electric capacity
One end of switch is connected with each other, and the other end of the second switch is connected with reference voltage, and other the one of first electric capacity
End and one end of described three, the 4th switches are connected with each other, the other end and the signal integration module of the 3rd switch
It is connected, the other end of the 4th switch is connected with ground level.
A kind of 5. cmos image sensor low noise reading circuit according to claim 1, it is characterised in that the signal
Integration module includes operational amplifier, and the 5th switch and the second electric capacity are formed；Wherein, the negative input of the operational amplifier
Other end, one end of the 5th switch and one end of second electric capacity with the described 3rd switch are connected with each other；It is described
The positive input of operational amplifier is connected with ground level, its output end and the other end and described second of the described 5th switch
The other end of electric capacity is connected with each other.
A kind of 6. cmos image sensor low noise reading circuit according to claim 1, it is characterised in that the signal
Averaging module includes the 6th switch, the 7th switch, the 8th switch, the 3rd electric capacity and the 4th electric capacity；Wherein, it is described 6th switch
One end is connected with the output end of the operational amplifier, the one end and the 7th switch of its other end with the 3rd electric capacity
One end be connected with each other, the other end of the 3rd electric capacity is connected with ground level, the described 7th other end switched and institute
State one end of the 8th switch and one end of the 4th electric capacity to be connected with each other, the other end and the described 4th of the 8th switch
The other end of electric capacity is connected with ground level.
7. a kind of cmos image sensor low noise reading circuit according to claim 6, it is characterised in that the described 4th
The capacitance of electric capacity is M-1 times of the capacitance of the 3rd electric capacity.
8. a kind of reading method of cmos image sensor low noise reading circuit, step are as follows：
S01：Pending signal is inputted by signal input part, signal multiple repairing weld module is carried out M times to the pending signal
Sampling processing simultaneously transmits the signal after sampling to signal integration module, and M is the integer more than 1；
S02：The signal integration module carries out integration summation to the signal after the sampling, and exports integration summing signal to letter
Number averaging module；
S03：The signal averaging module is averaged to the integration summing signal, and exports average value by signal output part
Signal.
9. a kind of reading method of cmos image sensor low noise reading circuit according to claim 8, its feature exist
In when pending signal is voltage signal, the integration summing signal isWherein,To wait to locate
Manage average voltage of the signal after M sampling, VREFFor reference voltage.
10. a kind of reading method of cmos image sensor low noise reading circuit according to claim 8, its feature exist
In when pending signal is voltage signal, the average value signal isWherein,To be pending
Average voltage of the signal after M sampling, VREFFor reference voltage.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3770893A4 (en) * | 2018-03-23 | 2021-12-22 | BOE Technology Group Co., Ltd. | Power source voltage supply circuit, method, display substrate and display device |
| CN117155070A (en) * | 2023-10-30 | 2023-12-01 | 湃晟芯(苏州)科技有限公司 | Detection circuit of high-frequency DCDC switching power supply |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101204013A (en) * | 2005-05-05 | 2008-06-18 | 阿纳洛格装置公司 | Accurate low noise analog to digital converter system |
| CN101582978A (en) * | 2009-06-18 | 2009-11-18 | 东南大学 | Background suppression method for infrared reading circuit and circuit thereof |
| CN104469201A (en) * | 2014-12-29 | 2015-03-25 | 中国科学院半导体研究所 | Analog reading preprocessing circuit for CMOS image sensor and control method thereof |
| CN104836966A (en) * | 2015-04-20 | 2015-08-12 | 中国航天科技集团公司第九研究院第七七一研究所 | CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor line buffer signal integrity optimization circuit and method |
| WO2016133666A1 (en) * | 2015-02-20 | 2016-08-25 | Northrop Grumman Systems Corporation | Delta-sigma digital radiometric system |
| US20170054930A1 (en) * | 2015-08-19 | 2017-02-23 | Semiconductor Energy Laboratory Co., Ltd. | Imaging device, operating method thereof, and electronic device |
-
2017
- 2017-07-12 CN CN201710565831.7A patent/CN107396008B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101204013A (en) * | 2005-05-05 | 2008-06-18 | 阿纳洛格装置公司 | Accurate low noise analog to digital converter system |
| CN101582978A (en) * | 2009-06-18 | 2009-11-18 | 东南大学 | Background suppression method for infrared reading circuit and circuit thereof |
| CN104469201A (en) * | 2014-12-29 | 2015-03-25 | 中国科学院半导体研究所 | Analog reading preprocessing circuit for CMOS image sensor and control method thereof |
| WO2016133666A1 (en) * | 2015-02-20 | 2016-08-25 | Northrop Grumman Systems Corporation | Delta-sigma digital radiometric system |
| CN104836966A (en) * | 2015-04-20 | 2015-08-12 | 中国航天科技集团公司第九研究院第七七一研究所 | CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor line buffer signal integrity optimization circuit and method |
| US20170054930A1 (en) * | 2015-08-19 | 2017-02-23 | Semiconductor Energy Laboratory Co., Ltd. | Imaging device, operating method thereof, and electronic device |
Non-Patent Citations (2)
| Title |
|---|
| 周同: "具有背景电流自补偿功能的红外读出电路研究", 《中国博士学位论文全文数据库 信息科技辑》 * |
| 黄智伟: "《基于TI器件的模拟电路设计》", 31 July 2014, 北京航空航天大学出版社 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3770893A4 (en) * | 2018-03-23 | 2021-12-22 | BOE Technology Group Co., Ltd. | Power source voltage supply circuit, method, display substrate and display device |
| CN117155070A (en) * | 2023-10-30 | 2023-12-01 | 湃晟芯(苏州)科技有限公司 | Detection circuit of high-frequency DCDC switching power supply |
| CN117155070B (en) * | 2023-10-30 | 2023-12-29 | 湃晟芯(苏州)科技有限公司 | Detection circuit of high-frequency DCDC switching power supply |
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