CN107396008A - A kind of cmos image sensor low noise reading circuit and its reading method - Google Patents
A kind of cmos image sensor low noise reading circuit and its reading method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/618—Noise processing, e.g. detecting, correcting, reducing or removing noise for random or high-frequency noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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Abstract
The invention discloses a kind of cmos image sensor low noise reading circuit and its reading method, the reading circuit includes signal multiple repairing weld module, signal integration module and signal averaging module, the signal integration module both ends connect the signal multiple repairing weld module and signal averaging module respectively, the other end of the signal integration module is signal input part, the other end of the signal averaging module is signal output part, the signal multiple repairing weld module, which treats process signal progress multiple repairing weld processing and transmits it to the signal integration module, carries out integration summation, integration summing signal is transmitted to the signal averaging module again and averaged, finally average value signal is exported by signal output part.A kind of cmos image sensor low noise reading circuit provided by the invention, can effectively reduce PIXEL equivalent input noises, especially suitable for low photoenvironment, picture quality can be effectively improved, suitable for promoting the use of.
Description
Technical Field
The invention relates to the field of image sensors, in particular to a CMOS image sensor low-noise reading circuit and a reading method thereof.
Background
In the field of image sensors, improving image quality is a constant theme. The photosensitive signal of the image sensor is affected by various noise sources during transmission, so that the signal-to-noise ratio is difficult to improve. The noise can cause various FPN (solid state noise) and various random bright or dark spots to appear in the image. Particularly in low-light conditions, because the photo-generated current is relatively small, signals are easily submerged in noise, and the problem of particularly poor image quality in low-light environments occurs.
In the prior art, a method adopted for noise processing is a CDS (correlated double sampling) technology, the method is widely applied to the field of CMOS (complementary metal oxide semiconductor) image sensors, the FPN (floating gate noise) of a pixel unit and the noise of a source follower can be reduced by the technology, but the method has limited effect in a low-light environment and cannot improve the image quality in the low-light environment.
Disclosure of Invention
The invention aims to solve the technical problem of providing a low-noise reading circuit and a reading method of a CMOS image sensor, wherein the low-noise reading circuit can effectively reduce the equivalent input noise of PIXEL, is particularly suitable for low-illumination environments, can effectively improve the image quality, and is suitable for popularization and use.
In order to achieve the purpose, the invention adopts the following technical scheme: the utility model provides a CMOS image sensor low noise readout circuit, wherein, includes signal sampling module, signal integral module and signal average module many times, signal integral module both ends are connected respectively signal sampling module and signal average module many times, the other end of signal sampling module many times is signal input part, the other end of signal average module is signal output part, signal sampling module many times carries out M times sampling process to the signal of treating, and M is for being greater than 1 integer.
Further, the signal integration module performs integration and summation on the signals after the M times of sampling, and outputs an integration and summation signal.
Further, the signal averaging module averages the integrated summation signal and outputs an average signal.
Further, the signal multi-sampling module includes a first switch, a second switch, a third switch, a fourth switch and a first capacitor, wherein a signal input end is connected to one end of the first switch, the other end of the first switch is connected to one end of the first capacitor and one end of the second switch, the other end of the second switch is connected to a reference voltage, the other end of the first capacitor is connected to one ends of the third switch and the fourth switch, the other end of the third switch is connected to the signal integration module, and the other end of the fourth switch is connected to a ground level.
Furthermore, the signal integration module comprises an operational amplifier, a fifth switch and a second capacitor; the negative input end of the operational amplifier is connected with the other end of the third switch, one end of the fifth switch and one end of the second capacitor; and the positive input end of the operational amplifier is connected with the ground level, and the output end of the operational amplifier is mutually connected with the other end of the fifth switch and the other end of the second capacitor.
Further, the signal averaging module comprises a sixth switch, a seventh switch, an eighth switch, a third capacitor and a fourth capacitor; one end of the sixth switch is connected to the output end of the operational amplifier, the other end of the sixth switch is connected to one end of the third capacitor and one end of the seventh switch, the other end of the third capacitor is connected to ground, the other end of the seventh switch is connected to one end of the eighth switch and one end of the fourth capacitor, and the other end of the eighth switch and the other end of the fourth capacitor are both connected to ground.
Further, the capacitance value of the fourth capacitor is M-1 times of the capacitance value of the third capacitor.
A reading method of a CMOS image sensor low-noise reading circuit comprises the following steps:
s01: inputting a signal to be processed through a signal input end, carrying out M times of sampling processing on the signal to be processed through a signal multi-sampling module, and transmitting the sampled signal to a signal integration module, wherein M is an integer greater than 1;
s02: the signal integration module performs integration summation on the sampled signals and outputs integration summation signals to the signal averaging module;
s03: the signal averaging module averages the integrated summation signal and outputs an average signal through a signal output end.
Further, when the signal to be processed is a voltage signal, the integrated summation signal isWherein,is the average voltage V of the signal to be processed after M times of samplingREFIs a reference voltage.
Further, when the signal to be processed is a voltage signal, the average value signal isWherein,is the average voltage V of the signal to be processed after M times of samplingREFIs a reference voltage.
The invention has the beneficial effects that: the low-noise reading circuit of the CMOS image sensor processes the PIXEL signals by a method of sampling, integrating, summing and averaging for multiple times, can effectively reduce the equivalent input noise of PIXEL, is particularly suitable for low-illumination environments, can effectively improve the image quality, and is suitable for popularization and use.
Drawings
Fig. 1 is a schematic structural diagram of a low noise readout circuit of a CMOS image sensor according to the present invention.
Fig. 2 is a circuit diagram corresponding to embodiment 1 of the present patent application.
Fig. 3 is a timing chart corresponding to embodiment 1 of this patent.
In the figure, 1 a signal multi-sampling module, 2 a signal integrating module and 3 a signal averaging module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the low-noise readout circuit of a CMOS image sensor according to the present invention includes a signal multi-sampling module 1, a signal integrating module 2, and a signal averaging module 3, wherein two ends of the signal integrating module are respectively connected to the signal multi-sampling module and the signal averaging module, the other end of the signal integrating module is a signal input end, the other end of the signal averaging module is a signal output end, a signal to be processed enters the signal multi-sampling module through the signal input end, the signal multi-sampling module performs M-time sampling on the signal to be processed and transmits the sampled signal to the signal integrating module, the signal integrating module performs integration and summation on the M-time sampled signal, and transmitting the integral summation signal to a signal averaging module, averaging the integral summation signal by the signal averaging module, and outputting an average value signal through a signal output end, wherein M is an integer greater than 1.
The invention provides a reading method of a CMOS image sensor low-noise reading circuit, when a signal to be processed is voltage, the steps are as follows:
s01: the signal to be processed is input through a signal input end, the signal multi-time sampling module performs M-time sampling processing on the signal to be processed and transmits the signal to the signal integration module, and M is an integer greater than 1.
S02: the signal integration module performs integration summation on the acquired and processed signals and outputs an integration summation voltage signalTo a signal averaging block, where M is the signalThe number of times sampling is performed in the multi-sampling module,is the average voltage V of the signal to be processed after M times of samplingREFIs a reference voltage.
S03: the signal averaging module is used for averaging the integrated summation voltage and outputting an average voltage signal through a signal output end, wherein,
as shown in fig. 1, the signal multi-sampling module 1 includes a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, and a first capacitor C1. The signal input terminal PIXEL _ IN is connected to one terminal of the first switch SW1, and the other terminal of the first switch SW1 is connected to one terminal of the first capacitor C1 and one terminal of the second switch SW 2. The other end of the second switch SW2 is connected to the reference voltage VREFAre connected. The other end of the first capacitor C1 is connected to one end of the third switch SW3 and the fourth switch SW 4. The other end of the third switch SW3 is connected to the signal integration block 2. The other terminal of the fourth switch SW4 is connected to the ground level VSS.
The signal integration block 2 includes an operational amplifier OPA1, a fifth switch SW5, and a second capacitor C2. The negative input terminal of the operational amplifier OPA1 is connected to the other terminal of the third switch SW3, one terminal of the fifth switch SW5, and one terminal of the second capacitor C2. The positive input terminal of the operational amplifier OPA1 is connected to the ground level VSS, and the output terminal thereof is connected to the other terminal of the fifth switch SW5 and the other terminal of the second capacitor C2.
The signal averaging module comprises a sixth switch SW6, a seventh switch SW7, an eighth switch SW8, a third capacitor C3 and a fourth capacitor C4. The capacitance value of the fourth capacitor C4 is M-1 times that of the third capacitor C3, wherein M is the number of times of sampling in the signal multi-sampling module. One end of the sixth switch SW6 is connected to the output terminal of the operational amplifier OPA1, and the other end thereof is connected to one end of the third capacitor C3 and one end of the seventh switch SW 7. The other terminal of the third capacitor C3 is connected to ground level VSS. The other end of the seventh switch SW7, one end of the eighth switch SW8 and one end of the fourth capacitor C4 are connected to each other and serve as a signal output terminal of the readout circuit of the present invention. The other end of the eighth switch SW8 and the other end of the fourth capacitor C4 are both connected to the ground level VSS.
The CMOS image sensor low-noise reading circuit and the reading method thereof provided by the invention can be used for voltage signals, current signals or other signals transmitted in a circuit.
The invention provides a reading method of a CMOS image sensor low-noise reading circuit, which takes a voltage signal as an example and comprises the following steps:
s01: firstly, the first switch SW1 and the fourth switch SW4 are controlled to be opened, one end of a first capacitor C1 connected with the first switch SW1 is changed into V, and the other end of the first capacitor C1 is at a ground level of 0; then the second switch SW2 and the third switch SW3 are controlled to be opened, and one end of the first capacitor C1 connected with the second switch SW2 becomes the reference voltage VREFAnd the other end of the sampling circuit is connected with the negative input end of the operational amplifier, so that the first sampling of the voltage signal to be processed is realized. And circularly performing the operation for M times to finish M times of correlated sampling of the voltage signal to be processed.
S02: and performing integral summation on the signals subjected to the multiple sampling processing, wherein the output end voltage of the operational amplifier is as follows:wherein M is the sampling times in the signal multi-sampling module,is the average voltage V of the signal to be processed after M times of samplingREFIs a reference voltage.
S03: the sixth switch SW6 and the eighth switch SW8 are controlled to be turned off, then the third capacitor C3 is connected with the fourth capacitor C4 in parallel, and the charge on the C3 is evenly distributed with the C4Since C4 is (M-1) × C3, the average voltage signal is:at the moment, the VOUT outputs the average value of M times of correlated sampling of the voltage signal to be processed, and then the average value is delivered to an analog-to-digital converter ADC to perform analog-to-digital conversion on the signal to be processed;
in order to make the scope of the present invention clearer, the following describes the flow method of the readout circuit of the present invention for reading out the RESET SIGNAL and SIGNAL of the PIXEL by embodiments.
Example 1
As shown in fig. 2 and fig. 3, the readout circuit provided by the present invention is connected to a standard 4T PIXEL, and the MOS transistors connected to the photodiodes are M1, M2, M3 and M4, where a TX signal is applied to M1, a RST signal is applied to M2, an RS signal is applied to M4, a Φ 1 signal is applied to SW1 and SW4, a Φ 2 signal is applied to SW2 and SW3, a Φ R signal is applied to SW5, a Φ 3 signal is applied to SW6 and SW8, and a Φ 4 signal is applied to SW7, and the specific readout method includes the following steps:
step 1: the photodiode PD changes RST from low to high after exposure and then from high to low again, and a high pulse occurs in Φ R during this time interval and then remains low. Φ 3 changes from the low level to the high level, so that the sixth switch SW6 and the eighth switch SW8 are turned on.
Step 2: the RS changes from low to high and the RESET signal is output through the source of M4.
And step 3: the control signals phi 1 and phi 2 are a pair of two-phase non-overlapping clocks, a phi 1 high pulse arrives first, the first switch SW1 and the fourth switch SW4 are opened, and the voltage at one end of a first capacitor C1 connected with the first switch SW1 is changed into VRESET1The other end is a ground level 0; then the phi 2 high pulse arrives, the phi 1 keeps low level, the second switch SW2 and the third switch SW3 are opened, and one end of the first capacitor C1 connected with the second switch SW2 becomes reference electricityPressure VREFAnd the other end is connected with the negative input end of the operational amplifier, so that the first correlated sampling of the RESET signal is realized. Performing circulation for M times to complete M times of correlated sampling and integral summation of the RESET signal;
when both Φ 1 and Φ 2 remain low, the integrated summed voltage signal at the output of OPA1 is:
in formula 1Is the average voltage of the RESET signal after M times of sampling.
And 4, step 4: after that, Φ 3 changes from high to low, the sixth switch SW6 and the eighth switch SW8 are turned off, and then Φ 4 changes from low to high, and the third capacitor C3 is connected in parallel with the fourth capacitor C4. The charge on C3 is equally distributed to C4, and since C4 is (M-1) C3, the average voltage signal is:
at this time, VOUT1And outputting the average value of the M correlated samples of the RESET signal, and then delivering the average value to an analog-to-digital converter (ADC) to perform analog-to-digital conversion on the RESET signal.
And 5: Φ R is a high pulse and then is kept low, Φ 3 changes from low to high, so that the sixth switch SW6 and the eighth switch SW8 are turned on, Φ 4 changes from high to low, the TX SIGNAL changes from low to high, and the PIXEL outputs the SIGNAL.
Step 6: the control signals phi 1 and phi 2 are a pair of two-phase non-overlapping clocks, a phi 1 high pulse arrives first, the first switch SW1 and the fourth switch SW4 are opened, and the voltage at one end of a first capacitor C1 connected with the first switch SW1 is changed into VSIGNAL1The other end is a ground level 0; then the phi 2 high pulse arrives, the phi 1 keeps low level, the second switch SW2 and the third switch SW3 are opened, and one end of the first capacitor C1 connected with the second switch SW2 becomes the reference voltage VREFAnd the other end is connected with the negative input end of the operational amplifier, thereby realizing the first correlated sampling of the SIGNAL. The above-mentioned process is circularly performed for M times, and M times of correlation sampling and integral summation of the SIGNAL are completed.
After both Φ 1 and Φ 2 remain low, the integrated summation voltage signal output by OPA1 is:
in formula 3The average voltage of the SIGNAL after M times of sampling is obtained.
And 7: after that, Φ 3 changes from high to low, the sixth switch SW6 and the eighth switch SW8 are turned off, and then Φ 4 changes from low to high, and the third capacitor C3 is connected in parallel with the fourth capacitor C4. The charge on C3 is equally distributed to C4, and since C4 is (M-1) C3, the average voltage signal is:
at this time, VOUT2The average of M correlated samples of the SIGNAL is output and then forwarded to an analog-to-digital converter ADC for analog-to-digital conversion of the SIGNAL.
And 8: will VOUT1And VOUT2And (4) obtaining the conversion value of the illumination signal with low noise by subtracting the digital values after the analog-to-digital conversion.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.
Claims (10)
1. The utility model provides a CMOS image sensor low noise readout circuit, its characterized in that includes signal sampling module, signal integral module and signal average module many times, signal integral module both ends are connected respectively signal sampling module many times with signal average module, the other end of signal sampling module many times is signal input end, the other end of signal average module is signal output end, signal sampling module many times carries out M sampling to the signal of treating, and M is for being greater than 1 integer.
2. The CMOS image sensor low noise readout circuit of claim 1, wherein the signal integration module integrates and sums the M sampled signals and outputs an integrated sum signal.
3. A CMOS image sensor low noise readout circuit according to claim 2, wherein the signal averaging block averages the integrated sum signal and outputs an averaged value signal.
4. The CMOS image sensor low-noise readout circuit according to claim 1, wherein the signal multi-sampling module comprises a first switch, a second switch, a third switch, a fourth switch, and a first capacitor, wherein a signal input terminal is connected to one terminal of the first switch, the other terminal of the first switch is connected to one terminal of the first capacitor and one terminal of the second switch, the other terminal of the second switch is connected to a reference voltage, the other terminal of the first capacitor is connected to one terminals of the third and fourth switches, the other terminal of the third switch is connected to the signal integration module, and the other terminal of the fourth switch is connected to a ground level.
5. The CMOS image sensor low noise readout circuit of claim 1, wherein said signal integration module comprises an operational amplifier, a fifth switch and a second capacitor; the negative input end of the operational amplifier is connected with the other end of the third switch, one end of the fifth switch and one end of the second capacitor; and the positive input end of the operational amplifier is connected with the ground level, and the output end of the operational amplifier is mutually connected with the other end of the fifth switch and the other end of the second capacitor.
6. The CMOS image sensor low noise readout circuit of claim 1, wherein said signal averaging block comprises a sixth switch, a seventh switch, an eighth switch, a third capacitor and a fourth capacitor; one end of the sixth switch is connected to the output end of the operational amplifier, the other end of the sixth switch is connected to one end of the third capacitor and one end of the seventh switch, the other end of the third capacitor is connected to ground, the other end of the seventh switch is connected to one end of the eighth switch and one end of the fourth capacitor, and the other end of the eighth switch and the other end of the fourth capacitor are both connected to ground.
7. A CMOS image sensor low noise readout circuit as in claim 6, wherein said fourth capacitor has a capacitance value M-1 times the capacitance value of said third capacitor.
8. A reading method of a CMOS image sensor low-noise reading circuit comprises the following steps:
s01: inputting a signal to be processed through a signal input end, carrying out M times of sampling processing on the signal to be processed through a signal multi-sampling module, and transmitting the sampled signal to a signal integration module, wherein M is an integer greater than 1;
s02: the signal integration module performs integration summation on the sampled signals and outputs integration summation signals to the signal averaging module;
s03: the signal averaging module averages the integrated summation signal and outputs an average signal through a signal output end.
9. The readout method of claim 8, wherein when the signal to be processed is a voltage signal, the integrated summation signal isWherein,is the average voltage V of the signal to be processed after M times of samplingREFIs a reference voltage.
10. The readout method of claim 8, wherein when the signal to be processed is a voltage signal, the average signal isWherein,is the average voltage V of the signal to be processed after M times of samplingREFIs a reference voltage.
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