CN107395525A

CN107395525A - A kind of rapidIO network exchange methods of VPX power boards

Info

Publication number: CN107395525A
Application number: CN201710621909.2A
Authority: CN
Inventors: 王静娇; 姜小祥; 翟刚毅; 李云飞
Original assignee: 724th Research Institute of CSIC
Current assignee: 724th Research Institute of CSIC
Priority date: 2017-07-27
Filing date: 2017-07-27
Publication date: 2017-11-24
Anticipated expiration: 2037-07-27
Also published as: CN107395525B

Abstract

The present invention relates to a kind of rapidIO network exchange methods of VPX power boards, including：On the fpga chip of VPX cabinet power boards, based on SOPC frameworks, invention customized IP core, integrated interface between rapidIO FC translation functions and rapidIO maintenance ports and the soft cores of CPU, simultaneously under this hardware frame, rapidIO drivings, network enumeration are completed using SDK softwares, and realize bandwidth allocation, hot plug management function.

Description

A kind of rapidIO network exchange methods of VPX power boards

Technical field

The rapidIO high-speed datas that this method is related to a kind of VPX cabinets exchange improved method.

Background technology

RapidIO is a kind of embedded system interconnection technique, is an open point-to-point interchange standard, has high band Width, low latency, it is highly reliable the advantages of, can also in VPX cabinets across backboard connection processor, memory and external equipment, It is widely applied in Radar Signal Transmission.

Power board in conventional VPX cabinets only with the addition of rapidIO exchange chips, realize the rapidIO data between cabinet Exchange, and enumerating for rapidIO networks is realized by a certain piece of powerpc board card；Data exchange between cabinet and cabinet is By FC fiber optic communications, i.e., the conversion of rapidIO and FC data is carried out by one piece of FC board on rear IO.This design is to nothing Need the system of powerpc board card a kind of wasting of resources to be then present, and be inconvenient to carry out rapidIO node administrations, any one piece PowerPC can be enumerated, unavoidable to produce conflict, so as to cause dead chain.

The present invention proposes a kind of improved method based on VPX cabinet power boards, using the fpga chip on power board, adopts Designed with SOPC, realize that rapidIO networks are enumerated and rapidIO-FC functions, be truly realized the function of exchange collection of power board Into, board is saved, is economized on resources, is minimized for radar system, it is integrated to do basis.

The content of the invention

It is an object of the invention to a kind of rapidIO high-speed datas exchange of VPX power boards is provided for Transmission System of Radar Data Improved method.Data exchange is by rapidIO agreements in VPX cabinets, by FC agreements between cabinet and cabinet, in conventional system Realize that rapidIO networks are enumerated and rapidIO-FC agreements respectively by one piece of powerpc board card in cabinet and FC back card/back boards Conversion, the present invention are integrated with the two functions on the FPGA of power board.

Realize that the object of the invention technical solution is：SOPC systems are built by vivado based on fpga chip, with The soft cores of MicroBlaze are core, create the customized IP core based on AXI buses, realize that rapidIO mountings, rapidIO are safeguarded Communication interface and rapidIO-FC translation functions between port and the soft cores of CPU.Under hardware frame, opened using SDK softwares Hair rapidIO drivings and rapidIO networks enumeration simultaneously realize bandwidth allocation, hot plug management function, by register and Customized IP core is communicated.

Advantages of the present invention and effect：The function of exchange for being truly realized power board integrates, and saves board, economizes on resources, Minimized for radar system, it is integrated to lay the first stone.

The present invention is described in further detail below in conjunction with the accompanying drawings.

Brief description of the drawings

RapidIO power board block diagram of the accompanying drawing 1 based on SOPC.

Accompanying drawing 2rapidIO exchanges the logical design block diagram of IP kernel.

Accompanying drawing 3rapidIO enumerations.

The cabinet rapidIO network topological diagrams of accompanying drawing 4.

Embodiment

The present invention mainly realized on the FPGA of power board rapidIO networks enumerate, hot plug and bandwidth allocation function, and Integrated rapidIO-FC fiber-optic switching modules, embodiment are：

1) the SOPC hardware systems structure based on MicroBlaze：

Using the vivado external members of Xilinx companies, by the soft cores of MicroBlaze, AXI Connect cores, UART and from Define rapidIO and exchange IP kernel combination structure SOPC on-chip system hardware frames.Connected by AXI buses and ancillary equipment IP kernel Connect, interacted between each equipment by AXI bus protocols.RapidIO power boards block diagram such as Fig. 1 institutes wherein based on SOPC Show, the logical design block diagram that rapidIO exchanges IP kernel is as shown in Figure 2.

2) rapidIO networks are enumerated realizes with bandwidth allocation：

Under hardware frame, using SDK softwares, for known rapidIO Network Topology Designs depth finding algorithm algorithm Flow chart is as shown in figure 3, record the device node detected, according to groove position fixed allocation ID number.

Two panels CPS1848 exchange chips on power board, the board of the 5 groove positions in every each connection left and right, in order to prevent RapidIO network congestions, 5 × 4 port connection, such as Fig. 4, each groove bit occupancy one are devised between two panels exchange chip X4 connection, by groove position order, distribution is route one by one, so as to realize bandwidth allocation.For example, for slot8 it is upper 29,30,31,32ID Number configuration CPS1848 (1) routing table, then the port numbers configured are 2, be that to configure port numbers be 3 for device id on slot9, Device id configuration port numbers on slot10 be that to configure port numbers be the device id on 9, slot12 for device id on 6, slot11 Configuration port numbers are that the upper device ids of 10, slot1-slot5 are configured to CPS1848 (2) port numbers also by that analogy.

3) management of rapidIO node hot plugs is realized：

Using CPS1848 exchange chips, supporting node hot plug, the insertion of cpu node is notified using interrupt mode and pulled out Go out, register is safeguarded according to handbook read-write, recovers port status, and establish mistake administrative mechanism, regularly inquire about each exchange core The port of piece, once having error by link-reset or writing port state registers, real-time recovery port status, keep Link is unimpeded.

4) rapdiIO-FC modular converters are realized：

Communicated between board on cabinet by RapidIO, and between each cabinet be different RapidIO nets Network, their high-speed communication use FC optical fiber.According to rapdiIO agreements and FC protocol characteristics, FC is added in customized IP core The logical code of adaptation module, the mutual conversion of two kinds of protocol datas is realized, so as to complete the high speed data transfer between cabinet, SRIO bags use HELLO forms.

● rapidIO turns FC：

I.e. PPC processing modules send SRIO protocol datas to the FPGA rapidIO host nodes on power board, then it is turned FC protocol signals are changed to, then FC interchangers are sent to by optical fiber.

FC adaptation modules transmission interface face in the case where data are accumulated, the ready signals of SRIO buses is dragged down, back-pressure To SRIO；PPC processing modules send big data bag by SRIO, are sent using Nwrite, final stage data use Nwrite_ R is sent, and then retransmits doorbell, confirms that data have been sent completely；After FC adaptation modules receive SRIO data, according to The base address put confirms the beginning (SOP) of packet, and the end of packet is confirmed according to the Nwrite_R and doorbell received (EOP)；Remove the HELLO header packet informations of addition simultaneously, be placed on ASM payload beginning；By SRIO SRCID and DESID (bit wide 8bit), it is put into inside ASM reserved fields, is sent with FC data；FC adaptation modules receive HELLO forms by SRIO Bao Hou, sendaisle is confirmed by base address and srcID/desID；

● FC turns rapidIO：

I.e. FC adaptation modules receive FC-AE-ASM protocol datas, convert it into SRIO protocol datas, then pass through RapidIO networks are sent to PPC processing modules：

Base address and SRCID/DESID are parsed according to ASM data；FC agreement payload data are cut into composition HELLO lattice The packet of formula is exported by SRIO buses；FC data according to receiving parse base address, SRCID and DESID and remapped Cheng Xin SRIO base address, SRCID and DESID, the packet that new HELLO forms are formed with data export.

Claims

1. a kind of rapidIO network exchange methods of VPX power boards, it is characterised in that：1) FPGA based on VPX cabinet power boards SOPC frameworks are built by vivado；2) using MicroBlaze as core, the customized IP core based on AXI buses is created, i.e., Trio IP kernels, the IP kernel realize the mounting of rapidIO nodes, the interface between rapidIO maintenance ports and the soft cores of CPU and RapidIO-FC translation functions；3) under hardware frame, enumerated using SDK software developments rapidIO drivings and rapidIO networks Algorithm, so as to realize enumerating and exchanging for rapidIO networks on power board, and it is integrated with the mutual revolving die of rapidIO-FC agreements Block, the high-speed data function of exchange for being truly realized power board integrate.

2. the rapidIO network exchange methods according to claim 1 based on power board, it is characterised in that：Based on known The rapidIO data bandwidth allocations and warm connection function of VPX cabinets.