CN107393985B - 一种背照式雪崩光敏器件及其制备方法 - Google Patents
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Abstract
本发明提供了一种背照式雪崩光敏器件及其制备方法，背照式雪崩光敏器件包括：位于硅衬底上的MOS管和PIN结构；PIN结构包括：位于硅衬底的部分正面的N+层；位于硅衬底的整个背面的P+层；位于N+层和P+层之间的硅衬底，作为I层；位于硅衬底的部分正面的MOS管的栅极、源极和漏极；P+层与MOS管的源极或漏极相连接；位于PIN结构中的N+层作为PIN结构与MOS管共享源极或共享漏极；并且，通过离子注入形成N+层和P+层，从而提高了背面的P+层的表面积，在从硅片背面进行光照时，由于硅片背面的光敏器件的表面积得到的光照得到提高，从而提高了器件的灵敏度。
Description
技术领域
本发明涉及半导体技术领域，具体涉及一种背照式雪崩光敏器件及其制备方法。
背景技术
雪崩光敏器件是指在激光通信中使用的光敏元件。在以硅或折为材料制成的光电二极管的PN结上加上反向偏压后，入射光被PN结吸收后会形成光电流，加大反向偏压会产生雪崩现象，也即是光电流成倍地激增的现象，这种器件被称为雪崩光敏器件。
然而，PN结构成的雪崩光敏器件存在隧道电路倍增的过程，将产生较大的散粒噪音，因此，倍增区采用较宽禁带宽度的材料，光吸收区采用较窄禁带宽度的材料，形成突变异质结，将使光生空穴有所积累而影响到器件的相应速度，此时，采用在突变异质结的中间插入一层缓变层形成PIN结构来减小上述温度。
因此，PIN结构的雪崩光敏器件在微光和单光子探测方面具有独特优势。
发明内容
为了克服以上问题，本发明旨在提供一种背照式雪崩光敏器件，在硅片正面和背面分别形成P+和N+区，从而形成P+I N+结构的雪崩光敏器件。
为了达到上述目的，本发明提供了一种背照式雪崩光敏器件，位于一硅衬底上，其包括：位于硅衬底上的MOS管和PIN结构；其中，
PIN结构包括：
位于所述硅衬底的部分正面的N+层；
位于所述硅衬底的整个背面的P+层；
位于N+层和P+层之间的硅衬底，作为I层；
位于硅衬底的部分正面的MOS管的栅极、源极和漏极；
所述P+层与MOS管的源极或漏极相连接；
位于PIN结构中的所述N+层作为PIN结构与MOS管共享源极或共享漏极。
优选地，所述P+层通过一通孔与MOS管的源极或漏极相连接。
优选地，所述P+层连接第一通孔的一端，所述MOS管的源极或漏极连接第二通孔的一端，所述第一通孔的另一端与所述第二通孔的另一端共同连接至一导电金属上。
优选地，所述硅衬底背面且对应于N+层的区域具有多个凹槽，所述P+层形成于所述凹槽顶部和侧壁、以及所述硅衬底的背面。
为了达到上述目的，本发明还提供了一种背照式雪崩光敏器件的制备方法，其包括：
步骤01：提供一硅衬底；
步骤02：在硅衬底正面形成MOS管以及形成N+层；
步骤03：在硅衬底整个背面形成P+层；
步骤04：在MOS管和N+层之外的硅衬底中形成通孔，通孔的一端与MOS管的源极或漏极相电连，另一端与硅衬底背面的P+层的相电连。
优选地，所述步骤03中，还包括：在对应于N+层下方的硅衬底背面中形成多个凹槽；然后，在凹槽侧壁和顶部、以及硅衬底背面形成P+层。
优选地，所述N+层的形成采用离子注入N型杂质到硅衬底表面中。
优选地，所述P+层的形成采用离子注入P型杂质表面中。
优选地，所述步骤04中，具体包括：在MOS管和N+层之外的硅衬底中形成第一通孔，使第一通孔的一端与P+层接触。第一通孔的另一端与一金属导电层的一端连接，金属导电层的另一端与一MOS管的源极或漏极通过第二通孔相连接。
优选地，所述步骤04中，采用光刻和刻蚀工艺形成所述通孔。
本发明的背照式雪崩光敏器件，提高了背面的P+层的表面积，在从硅片背面进行光照时，由于硅片背面的光敏器件的表面积得到的光照得到提高，从而提高了器件的灵敏度。
附图说明
图1为本发明的一个较佳实施例的背照式雪崩光敏器件的结构示意图
图2为本发明的一个较佳实施例的背照式雪崩光敏器件的制备方法
图3～6为图2的背照式雪崩光敏器件的制备方法的各步骤示意图
具体实施方式
为使本发明的内容更加清楚易懂，以下结合说明书附图，对本发明的内容作进一步说明。当然本发明并不局限于该具体实施例，本领域内的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。
以下结合1～6和具体实施例对本发明作进一步详细说明。需说明的是，附图均采用非常简化的形式、使用非精准的比例，且仅用以方便、清晰地达到辅助说明本实施例的目的。
请参阅图1，本实施例的一种背照式雪崩光敏器件，位于一硅衬底上，其包括：位于硅衬底00上的MOS管031、032和PIN结构；其中，PIN结构包括：位于硅衬底00的部分正面的N+层01；位于硅衬底00的整个背面的P+层02；位于N+层01和P+层02之间的硅衬底00，作为I层；位于硅衬底00的部分正面的MOS管031、032的栅极、源极和漏极；P+层02与MOS管031的源极或漏极相连接；位于PIN结构中的N+层01作为PIN结构与MOS管032共享源极或共享漏极。本实施例中，P+层02可以通过第一通孔041与MOS管031的源极或漏极相连接。为了节省空间，提高器件集成度和灵敏度，P+层02可以连接第一通孔041的一端，MOS管031的源极或漏极连接第二通孔042的一端，第一通孔041的另一端与第二通孔042的另一端共同连接至一导电金属05上。
这里，N+层01还可以作为与之邻近的一个MOS管032的源极或漏极。
此外，为了提高硅衬底00背面的光吸收面积，从而提高光敏感性和探测灵敏度，可以在硅衬底00背面且对应于N+层01的区域设置多个凹槽，这样，P+层02形成于凹槽顶部和侧壁、以及硅衬底00的背面，从而提高了P+层02的受光照面积。
请参阅图2，本实施例的一种背照式雪崩光敏器件的制备方法，包括：
步骤01：请参阅图3，提供一硅衬底00；
步骤02：请参阅图4，在硅衬,00正面形成MOS管031、032以及形成N+层01；
具体的，关于MOS管031、032的制备可以包括制备栅极、源漏极等。N+层01的形成可以N型离子注入到MOS管031、032之外的硅衬底00正面而得到。这里，N+层01还可以作为与之邻近的一个MOS管032的源极或漏极，如图4所示。
步骤03：请参阅图5，在硅衬底00整个背面形成P+层02；
具体的，可以采用P型离子注入到硅衬底00的整个背面，从而在硅衬底00整个背面形成P+层02。
这里，还包括：在对应于N+层01下方的硅衬底00背面中形成多个凹槽；然后，在凹槽侧壁和顶部、以及硅衬底00背面形成P+层02。
步骤04：请参阅图6，在MOS管031、032和N+层01之外的硅衬底00中形成通孔041，通孔041的一端与MOS管031的源极或漏极相电连，另一端与硅衬底00背面的P+层02的相电连。
具体的，本步骤04包括：在MOS管031、032和N+层01之外的硅衬底00中形成第一通孔041，使第一通孔041的一端与P+层02接触。然后，在与第一通孔041邻近的MOS管031的源极或漏极上形成第二通孔042，最后，形成金属导电层05，使得金属导电层05的一端与第一通孔041顶部连接，金属导电层05的另一端与第二通孔042的顶部连接。
虽然本发明已以较佳实施例揭示如上，然实施例仅为了便于说明而举例而已，并非用以限定本发明，本领域的技术人员在不脱离本发明精神和范围的前提下可作若干的更动与润饰，本发明所主张的保护范围应以权利要求书为准。
Claims (7)
1.一种背照式雪崩光敏器件，位于一硅衬底上，其特征在于，包括：位于硅衬底上的PIN结构和两个MOS管；其中，
PIN结构包括：
位于所述硅衬底的部分正面的N+层；
位于所述硅衬底的整个背面的P+层；
位于N+层和P+层之间的硅衬底，作为I层；
所述背照式雪崩光敏器件还包括位于硅衬底的部分正面的MOS管的栅极、源极和漏极；
所述P+层通过通孔与其中一个MOS管的源极或漏极相连接；
位于PIN结构中的所述N+层作为PIN结构与另外一个MOS管共享源极或共享漏极；
所述硅衬底背面且对应于N+层的区域具有多个凹槽，所述P+层形成于所述凹槽顶部和侧壁、以及所述硅衬底的背面。
2.根据权利要求1所述的背照式雪崩光敏器件，其特征在于，所述P+层连接第一通孔的一端，所述MOS管的源极或漏极连接第二通孔的一端，所述第一通孔的另一端与所述第二通孔的另一端共同连接至一导电金属上。
3.一种背照式雪崩光敏器件的制备方法，其特征在于，包括：
步骤01：提供一硅衬底；
步骤02：在硅衬底正面形成两个MOS管以及形成N+层；
步骤03：在硅衬底整个背面形成P+层；具体地，在对应于N+层下方的硅衬底背面中形成多个凹槽；然后，在凹槽侧壁和顶部、以及硅衬底背面形成P+层；
步骤04：在MOS管和N+层之外的硅衬底中形成通孔，通孔的一端与其中一个MOS管的源极或漏极相电连，另一端与硅衬底背面的P+层的相电连，且位于PIN结构中的所述N+层作为PIN结构与另外一个MOS管共享源极或共享漏极。
4.根据权利要求3所述的背照式雪崩光敏器件的制备方法，其特征在于，采用离子注入N型杂质到硅衬底表面中形成所述N+层。
5.根据权利要求3所述的背照式雪崩光敏器件的制备方法，其特征在于，采用离子注入P型杂质到硅衬底背面表面中，形成所述P+层。
6.根据权利要求3所述的背照式雪崩光敏器件的制备方法，其特征在于，所述步骤04中，具体包括：在MOS管和N+层之外的硅衬底中形成第一通孔，使第一通孔的一端与P+层接触，从而实现与P+层相电连；第一通孔的另一端与一金属导电层的一端连接，金属导电层的另一端与一MOS管的源极或漏极通过第二通孔相连接，从而实现与MOS管的源极或漏极相电连。
7.根据权利要求3所述的背照式雪崩光敏器件的制备方法，其特征在于，所述步骤04中，采用光刻和刻蚀工艺形成所述通孔。
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| CN101069288A (zh) * | 2004-11-03 | 2007-11-07 | X-Fab半导体制造股份公司 | 垂直的pin或nip光电二极管和用于与传统cmos工艺兼容地制造的方法 |
| CN104201219A (zh) * | 2009-02-24 | 2014-12-10 | 浜松光子学株式会社 | 光电二极管以及光电二极管阵列 |
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| CN104201182A (zh) * | 2014-09-04 | 2014-12-10 | 北京思比科微电子技术股份有限公司 | 一种背照式图像传感器像素及其制作方法 |
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