CN107391853B - PCB packaging design method and device - Google Patents
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- CN107391853B CN107391853B CN201710617180.1A CN201710617180A CN107391853B CN 107391853 B CN107391853 B CN 107391853B CN 201710617180 A CN201710617180 A CN 201710617180A CN 107391853 B CN107391853 B CN 107391853B
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- 238000013461 design Methods 0.000 title claims abstract description 94
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Abstract
The embodiment of the invention provides a PCB packaging design method and a PCB packaging design device, and belongs to the technical field of circuit board packaging. The PCB packaging design method and the device provided by the embodiment of the invention perform binding operation on the forbidden zone in the device packaging library, and when the device packaging library is called to perform PCB design, the forbidden zone is bound in the graph of the device. Through the binding operation, in the process of PCB design, the forbidden region of the device can not be deleted independently, and only the whole device can be deleted. Therefore, the problem that an engineer mistakenly deletes the forbidden region of the device package itself is solved, the error probability and workload of a PCB design engineer are reduced, and the condition that a large amount of wires are arranged in the forbidden region in the later stage is avoided to a certain extent.
Description
Technical Field
The invention relates to the technical field of circuit board packaging, in particular to a PCB packaging design method and device.
Background
With the development of modern electronic circuits and microelectronic circuits, especially IC (Integrated Circuit) packaging technology, the advent of TSV (Through Silicon Via) technology, Flip Chip (Flip Chip) and other packaging technologies makes the Chip detachable from the carrier, and realizes a direct packaging form of bare Chip (Wafer, also called as die), which reduces the area and thickness of the Chip, but because of lack of the separation of the carrier, when the Chip is soldered on a PCB (Printed Circuit board), the Circuit on the surface layer of the PCB affects the sensitive Circuit in the Chip Wafer, resulting in abnormal operation of the Chip, especially an RF (Radio Frequency) Chip.
Along with the integration of mechanical and electronic components, peripheral mechanical and other structural components integrated on the PCB can make corresponding mechanical movement in the use process of a product, such as a clamping groove of a mobile phone, and can be drawn out, inserted and the like. In the mechanical movement processes, the mechanical part may rub against the surface of the PCB, so that the solder resist covered on the surface of the PCB is worn through, the surface circuit of the PCB is exposed, and the faults such as short circuit and open circuit are caused, thereby the whole machine is scrapped.
To solve the two common problems, it is common practice not to wire the sensitive area or the active area of the structure under the chip. Namely, when the circuit board is designed to be wired, a forbidden region is added in the packaging of the device. In the circuit board design and simulation software, each device package has a self-contained forbidden region, an engineer also needs to add and delete the forbidden region of the PCB at any time in the process of designing the wiring of the PCB, and the forbidden region of the PCB and the forbidden region of the device package are of the same attribute, so that the situation that the engineer mistakenly deletes the forbidden region of the device package in the process of designing the PCB frequently occurs, and the error rate of the PCB in the design process and the workload of the engineer are increased.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method and an apparatus for designing a PCB package, so as to alleviate the problem that an engineer mistakenly deletes a forbidden area of a device package itself.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:
in a first aspect, an embodiment of the present invention provides a PCB package design method, applied to Allegro software, including:
when the current device packaging library is provided with the forbidden region, binding the elements in the device packaging library, wherein the elements at least comprise the forbidden region;
when the device packaging library is called to design the PCB, displaying a device graph corresponding to the device packaging library, and binding a forbidden region in the device graph;
and designing the PCB based on the device graph.
In a preferred embodiment of the present invention, the step of performing a binding operation on elements in the device package library includes:
prompting whether to perform binding operation on the elements;
when an operation instruction of binding the element is received, setting the attribute of the element in the device package library as a binding attribute.
In a preferred embodiment of the present invention, the step of setting the property of the element in the device package library as the binding property includes:
calling a Drawing attribute corresponding to the device packaging library;
and setting the binding property in the Drawing property to be in a selected state.
In a preferred embodiment of the present invention, the step of designing the PCB based on the device pattern comprises:
receiving an operation instruction of a user;
and designing the PCB according to the operation instruction of the user.
In a preferred embodiment of the present invention, the step of designing the PCB according to the operation instruction of the user includes:
when an forbidden zone deleting instruction is received, reading the attribute of the forbidden zone corresponding to the forbidden zone deleting instruction;
and when the binding property is read, sending a prompt message to a user that the deletion of the forbidden region simultaneously deletes the device graph.
In a preferred embodiment of the present invention, the step of sending a prompt message to a user that deletion of the keep-out area will delete the device graphic at the same time includes:
and displaying the prompt information for deleting the device graph simultaneously to the user by deleting the forbidden region in an information prompt box mode.
In a preferred embodiment of the present invention, the step of sending a prompt message to a user that deletion of the keep-out area will delete the device graphic at the same time includes:
and sending prompt information to a user in a dialog box form, wherein the prompt information indicates whether the device graph is deleted and continues to be deleted when the forbidden region is deleted.
In a preferred embodiment of the present invention, after the step of sending a prompt to the user that the deletion of the keep-out region will delete the device graphic at the same time, the method further includes:
and deleting the device graph when receiving an instruction of continuing the deleting operation.
In a preferred embodiment of the present invention, when the current device package library has the keep-out region, the step of performing the binding operation on the elements in the device package library includes:
when an instruction for storing the current device packaging library is received, judging whether the device packaging library has a forbidden deployment area, if so, binding elements in the device packaging library, and storing the device packaging library after the binding operation; alternatively, the first and second electrodes may be,
and searching the device packaging library with the forbidden region from the established device packaging library, and binding the elements in the currently searched device packaging library.
In a second aspect, an embodiment of the present invention provides a PCB package design apparatus, applied to Allegro software, including:
the device packaging system comprises an element binding module, a component packaging module and a component packaging module, wherein the element binding module is used for binding elements in a device packaging library when the current device packaging library is provided with a forbidden region, and the elements at least comprise the forbidden region;
the packaging library calling module is used for displaying a device graph corresponding to the device packaging library when the device packaging library is called to design the PCB, and the forbidden arrangement region is bound in the device graph;
and the PCB design module is used for designing the PCB based on the device graph.
In a third aspect, an embodiment of the present invention provides a computer storage medium for storing computer software instructions for the PCB package design apparatus.
Compared with the prior art, the PCB packaging design method and the device provided by the embodiment of the invention perform binding operation on the forbidden region in the device packaging library, and when the device packaging library is called to perform PCB design, the forbidden region is bound in the graph of the device. Through the binding operation, in the process of PCB design, the forbidden region of the device can not be deleted independently, and only the whole device can be deleted. Therefore, the problem that an engineer mistakenly deletes the forbidden region of the device package itself is solved, the error probability and workload of a PCB design engineer are reduced, and the condition that a large amount of wires are arranged in the forbidden region in the later stage is avoided to a certain extent.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a flow chart of a PCB package design method provided by a first embodiment of the present invention;
FIG. 2 is a flow chart of a PCB package design method provided by a second embodiment of the present invention;
FIG. 3 is a flow chart of a PCB package design method provided by a third embodiment of the present invention;
FIG. 4 is a flow chart of a PCB package design method provided by a fourth embodiment of the present invention;
FIG. 5 is a diagram illustrating setting an attribute of an element in a device package library to a bound attribute according to an embodiment of the present invention;
fig. 6 is a block diagram of a PCB package design apparatus according to an embodiment of the present invention;
fig. 7 is a block diagram of a PCB package design apparatus according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The PCB packaging design method and device provided by the embodiment of the invention are applied to Allegro software. The Allegro software is the most widely used design software in the PCB design industry, and schematic diagram design, drawing of a PCB, wiring, packaging and the like can be realized through the software. The automatic layout and wiring function of the simulation circuit diagram design of the Allegro software can also meet the requirements of users on development and expansion. The Librarian in the Allegro software also provides a library development environment, provides a large number of library development toolkits, and facilitates the creation, verification and management of a large number of pin devices.
Considering that the lines on the surface layer of the PCB may affect the sensitive circuits in the bare chip Wafer, resulting in abnormal operation of the chip, or the mechanical component and the surface of the PCB rub against each other, resulting in solder resist wear-through covered on the surface of the PCB and exposing the lines on the surface layer of the PCB, when the Allegro software is used for PCB board packaging, a layout prohibition area needs to be set. The forbidden region on the PCB comprises a forbidden region carried by the device and a forbidden region added by an engineer in the design process of the PCB. Because the two forbidden regions have the same attribute, the situation that an engineer mistakenly deletes the forbidden region of the device package in the process of designing the PCB often occurs, and in order to reduce the situation as much as possible, the embodiment of the invention provides a PCB package design method and a device.
For the convenience of understanding the embodiments of the present invention, a PCB package design method disclosed in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Example one
Fig. 1 shows a flowchart of a PCB package design method provided in this embodiment, please refer to fig. 1, and the PCB package design method provided in this embodiment is applied to the Allegro software. The method comprises the following steps:
step S101, when the current device packaging library has the forbidden region, binding operation is carried out on elements in the device packaging library, wherein the elements at least comprise the forbidden region.
The device package library may be an already established device package library or a device package library newly established by a user. When the user uses the Allegro software, the user can establish a device packaging library according to library establishing guide or manual operation, set devices contained in the device packaging library, and elements of pins, pad groups, silk screen printing and the like of the devices, and store the elements in the library file. If a device needs to have a keep-out region due to having a sensitive circuit or for other reasons, the keep-out region may be set when building a library of device packages. When a layout forbidding area adding instruction of a user is received in the process of designing the device packaging library, adding a layout forbidding area in the device packaging library, wherein the layout forbidding area is the layout forbidding area of the device, and belongs to elements in the device packaging library together with pins and bonding pad groups of the device.
And for the device packaging library newly built by the user, judging whether the device packaging library has a distribution forbidding area or not when receiving an instruction for storing the current device packaging library, and if so, binding the elements in the device packaging library and storing the device packaging library after the binding operation.
And for the established device packaging library, searching the device packaging library with the forbidden deployment region from the established device packaging library, and binding the elements in the currently searched device packaging library to bind the forbidden deployment region with the corresponding device.
Specifically, the element in the device package library is bound, that is, the attribute of the element in the device package library is set as a bound attribute. In practical application, only the forbidden region in the device package library and important elements forming the device can be bound, and all the elements in the device package library can be bound into a whole.
And S102, when the device packaging library is called to design the PCB, displaying a device graph corresponding to the device packaging library, and binding a forbidden distribution area in the device graph.
In the PCB design process, a user may call the device package library, receive an instruction of the user to call the device package library, and display a device graph corresponding to a device in the device package library and bound elements on a display interface, wherein the bound elements include a forbidden region.
And step S103, designing the PCB based on the device graph.
And receiving an operation instruction of a user, and designing PCB packaging, wiring and the like according to the operation instruction of the user based on the device graph displayed on the display interface. And when a wiring operation instruction of a user is received, wiring is carried out outside the layout forbidden region.
In summary, the PCB package design method provided in the embodiments of the present invention performs a binding operation on the forbidden zone in the device package library, and when the device package library is called to perform a PCB design, the forbidden zone is bound in the pattern of the device. Through the binding operation, in the process of PCB design, the forbidden region of the device can not be deleted independently, and only the whole device can be deleted. Therefore, the problem that an engineer mistakenly deletes the forbidden region of the device package itself is solved, the error probability and workload of a PCB design engineer are reduced, and the condition that a large amount of wires are arranged in the forbidden region in the later stage is avoided to a certain extent.
Example two
Some PCB engineers may not need to bind their own keep-out regions in consideration of different design habits of different engineers. In order to meet the diversified demands of different users, the present embodiment provides another PCB package design method.
Fig. 2 is a flowchart of a PCB package design method provided in this embodiment. As shown in fig. 2, the method comprises the steps of:
step S201, when the current device packaging library has a layout prohibition region, prompting whether to perform a binding operation on the element.
The step corresponds to a device packaging library newly built by a user, when an instruction for storing the current device packaging library is received, whether the device packaging library has a distribution forbidding area is judged, and if yes, whether the element is bound is prompted. And if the user chooses not to bind the elements, directly storing the device packaging library newly built by the user. If the user selects the operation of binding the elements, the elements in the device packaging library are bound according to the step S202, and then the device packaging library is saved.
And prompting a user whether to perform element binding operation on the device packaging libraries in the Allegro software or not for the established device packaging libraries. If the user chooses no, no action is taken. If the user selects yes, searching the device packaging library with the forbidden region from the established device packaging library, and binding the elements in the searched device packaging library one by one to bind the forbidden region with the corresponding device.
Step S202, when receiving the operation instruction of the binding element, setting the attribute of the element in the device packaging library as the binding attribute.
Setting the attribute of the element in the device package library as a binding attribute can be realized by the following modes:
calling a Drawing attribute corresponding to the device packaging library;
and setting the binding property in the Drawing property to be in a selected state.
For example, for a device packaging library of a SIM card, after clicking the attribute edit command, "draw" is selected in the drop-down menu, and a draw attribute edit window pops up. As shown in fig. 5, first, a Locked attribute (bound attribute) in the bar box 2 is selected, the attribute is automatically added, and it is confirmed that a Value behind the Locked attribute in the bar box 1 is TRUE. Then, clicking an appliance button in the bar-shaped frame 3, and then clicking an OK button in the bar-shaped frame 4, and the operation of setting the binding property can be completed.
Step S203, when the device packaging library is called to design the PCB, displaying a device graph corresponding to the device packaging library, and binding a forbidden layout area in the device graph.
And step S204, designing the PCB based on the device graph.
Step S203 and step S204 can be implemented by referring to the corresponding technical means provided in the first embodiment, and are not described herein again.
Taking Allegro software as an example, running the Allegro software to design a device package library, for example, generating a minsd8-sim12-1828-015.dra file, and adding a proper banning area at a proper position according to design requirements; and adding a Locked attribute to the device packaging library file Drawing by editing the attribute of the whole design, and binding the added prohibited distribution region with the whole device through the attribute. When the Allegro software is used for designing the PCB, the device package library file can be directly called, and because the forbidden region of the device package library file is set to be the Locked attribute, when the addition and deletion of the forbidden region are carried out based on the device package library file, the forbidden region of the device package library file can be distinguished, and the forbidden region belongs to the forbidden region subsequently added by a designer, for example: deleting the prohibited distribution area of the device package library file gives prompt information for deleting the device as a whole, and deleting the prohibited distribution area added subsequently directly deletes or gives a prompt for whether to delete the prohibited distribution area.
According to the PCB packaging design method provided by the embodiment, different requirements of different engineers are considered while preventing the engineers from mistakenly deleting the forbidden arrangement area of the device packaging, and the flexibility and diversity of design are improved.
EXAMPLE III
In order to prevent an engineer from mistakenly deleting the keep-out area of the device package, the embodiment provides a PCB package design method for prohibiting deletion of the keep-out area of the device package.
Fig. 3 is a flowchart of a PCB package design method provided in this embodiment. As shown in fig. 3, the method comprises the steps of:
step S301, when the current device packaging library has the forbidden region, binding operation is carried out on elements in the device packaging library, wherein the elements at least comprise the forbidden region.
Step S302, when the device packaging library is called to design the PCB, a device graph corresponding to the device packaging library is displayed, and a forbidden region is bound in the device graph.
The step S301 and the step S302 can be implemented by referring to the corresponding technical means provided in the first embodiment or the second embodiment, and are not described herein again.
Step S303, receiving an operation instruction of the user.
And receiving an operation instruction of a user through a display interface, and performing PCB packaging design according to the received operation instruction.
Step S304, when the forbidden region deletion instruction is received, reading the attribute of the forbidden region corresponding to the forbidden region deletion instruction.
Step S305, determining whether the read attribute of the keep-out area is a binding attribute. If yes, step S306 is executed, and if no, step S307 is executed.
And S306, displaying the prompt information for deleting the corresponding device graph in the deletion forbidden region to a user in the form of an information prompt box.
For example, in the current display interface, there are both the keep-out region of the device itself and the keep-out region of the PCB edited by the user. When the user uses the instruction for deleting the forbidden zone independently, that is, after the user selects the deletion instruction, the forbidden zone is selected independently, and at this time, the attribute of the forbidden zone selected by the user needs to be read from the package library file. If the attribute of the forbidden region is a binding attribute, the forbidden region belongs to the forbidden region of the device, potential safety hazards may exist after the forbidden region is deleted, the operation of deleting the forbidden region is not executed, and meanwhile, the prompt information of deleting the forbidden region and simultaneously deleting the corresponding device graph is displayed to a user in an information prompt box mode so as to prompt the user not to allow the forbidden region to be deleted independently. If the user's intention is to delete the corresponding device, an operation of deleting the device may be additionally performed. If the attribute of the forbidden area is the unbound attribute, the following step S307 is performed.
If the user selects a deletion instruction and simultaneously selects a plurality of forbidden regions, when the forbidden regions with binding attributes exist in the plurality of forbidden regions, the deletion operation is not executed, and simultaneously, in the form of an information prompt box, the prompt information for deleting the corresponding device graphs in the forbidden regions is displayed to the user. When all the attributes of the plurality of keep-out areas are non-binding attributes, the following step S307 is performed.
In step S307, the forbidden area specified by the forbidden area deletion instruction is deleted.
The PCB packaging design method provided by the embodiment prohibits a user from independently deleting the forbidden deployment region of the device, thereby effectively avoiding potential safety hazards caused by the fact that an engineer deletes the forbidden deployment region of the device due to misoperation.
Example four
Fig. 4 is a flowchart of a PCB package design method provided in the present embodiment. As shown in fig. 4, the method includes the steps of:
step S401, when the current device packaging library has the forbidden region, binding operation is carried out on elements in the device packaging library, wherein the elements at least comprise the forbidden region.
Step S402, when the device packaging library is called to design the PCB, a device graph corresponding to the device packaging library is displayed, and a forbidden region is bound in the device graph.
Step S401 and step S402 can be implemented by referring to the corresponding technical means provided in the first embodiment or the second embodiment, and are not described herein again.
In step S403, an operation instruction of the user is received.
And receiving an operation instruction of a user through a display interface, and performing PCB packaging design according to the received operation instruction.
Step S404, when the forbidden region deletion instruction is received, reading the attribute of the forbidden region corresponding to the forbidden region deletion instruction.
Step S405, determine whether the read attribute of the keep-out area is a binding attribute. If yes, step S406 is performed, and if no, step S409 is performed.
Step S406, sending a prompt message to the user in a dialog box form, wherein the prompt message indicates whether the device graph is deleted or not at the same time when the layout prohibition area is deleted.
In step S407, it is determined whether the received instruction is to continue the deletion. If yes, step S408 is performed, and if no, the process ends.
In this embodiment, when the user uses the instruction to delete the prohibited area alone, the attribute of the prohibited area selected by the user needs to be read from the package library file. If the attribute of the forbidden zone is the binding attribute, the forbidden zone belongs to the forbidden zone of the device itself, a dialog box form is adopted, the prompting information for deleting the forbidden zone and simultaneously deleting the corresponding device graph is displayed to a user, so that the user is prompted that the forbidden zone belongs to the forbidden zone of the device itself, and the user is asked whether to continue deleting the forbidden zone. If the user selects the instruction to continue deleting the forbidden region, the forbidden region and the corresponding device graph are deleted according to step S408. If the attribute of the forbidden area is the unbound attribute, the following step S409 is performed.
If the user selects a plurality of forbidden areas at the same time after selecting the deletion instruction, when the forbidden areas with the binding property exist in the plurality of forbidden areas, the steps S406, S407 and S408 are performed. When all the attributes of the plurality of keep-out areas are non-binding attributes, the following step S409 is performed.
Step S408, deleting the forbidden region and the corresponding device pattern.
In step S409, the forbidden area specified by the forbidden area deletion instruction is deleted.
Compared with the above embodiment, the embodiment adopts a more flexible processing mode, allows the user to delete the corresponding device by selecting the forbidden region, and if the user selects the forbidden region carried by the device by misoperation, the cancel instruction can be selected in the dialog box, and the system does not execute the delete operation. If the intention of the user is to delete the device corresponding to the forbidden zone, a determination instruction can be selected in the dialog box, and the system deletes the forbidden zone and the device graph corresponding to the forbidden zone.
It should be noted that the above embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are not described repeatedly and can be referred to each other.
EXAMPLE five
Corresponding to the PCB package design method provided by the above embodiment, the embodiment provides a PCB package design apparatus, which is applied to Allegro software. As shown in fig. 6, the apparatus includes the following modules:
and the element binding module 61 is configured to, when the current device package library has a forbidden zone, perform a binding operation on elements in the device package library, where the elements at least include the forbidden zone, and the forbidden zone is a forbidden zone of the device itself.
And for the newly-built device packaging library, when an instruction for storing the current device packaging library is received, judging whether the device packaging library has a distribution forbidding area, if so, performing binding operation on elements in the device packaging library, and storing the device packaging library after the binding operation. Considering the diversified requirements of different users, before the elements in the device packaging library are bound, the user can be prompted whether to bind the elements, and after the instruction for confirming the binding by the user is received, the elements in the device packaging library are bound.
For the established device packaging library, whether the user performs the binding operation on the elements or not can be inquired firstly, after the instruction that the user confirms the binding is received, the device packaging library with the forbidden distribution area is searched from the established device packaging library, and the element in the searched device packaging library is subjected to the binding operation.
The specific steps of the binding operation may refer to fig. 5 and related descriptions in the foregoing method embodiments, and are not described herein again.
And the packaging library calling module 62 is configured to display a device graph corresponding to the device packaging library when the device packaging library is called to perform PCB design, and the device graph is bound with the forbidden region.
And the PCB design module 63 is configured to perform PCB design based on the device graphics, that is, receive an operation instruction of a user, and perform PCB packaging, wiring and other designs based on the device graphics displayed on the display interface and according to the operation instruction of the user.
In a more preferred embodiment as shown in fig. 7, the PCB design module 63 in turn comprises: the attribute reading unit 631 is configured to, when receiving the forbidden region deletion instruction, read an attribute of the forbidden region corresponding to the forbidden region deletion instruction; an information prompting unit 632, configured to issue, when the bound attribute is read, a prompt message to the user that the deletion of the prohibited area will delete the device graphics at the same time.
One implementation is as follows: the information prompt unit 632 displays, in the form of an information prompt box, prompt information for deleting the prohibited area and simultaneously deleting the corresponding device graphic to the user. The other realization mode is as follows: the information prompt unit 632 is configured to send a prompt message to the user, in the form of a dialog box, indicating whether to delete the device graphics corresponding to the deletion prohibited area and continue the deletion prohibited area. When receiving an instruction to continue the deletion operation, the device pattern is deleted by the device deletion unit 633.
The PCB package design apparatus of this embodiment performs a binding operation on the forbidden zone in the device package library, and when the device package library is called to perform PCB design, the forbidden zone is bound in the device graph. Through the binding operation, in the process of PCB design, the forbidden region of the device can not be deleted independently, and only the whole device can be deleted. Therefore, the problem that an engineer mistakenly deletes the forbidden region of the device package itself is solved, the error probability and workload of a PCB design engineer are reduced, and the condition that a large amount of wires are arranged in the forbidden region in the later stage is avoided to a certain extent.
The PCB package design apparatus provided in the above embodiments has the same implementation principle and technical effect as the foregoing method embodiments, and for the sake of brief description, reference may be made to the corresponding contents in the foregoing method embodiments for parts of the apparatus embodiments that are not mentioned.
It should be noted that the embodiment of the present invention further provides a computer storage medium for storing computer software instructions used by the apparatus described in the fifth embodiment.
The PCB packaging design method and the PCB packaging design device provided by the embodiment of the invention can be applied to a computer. The computer should include at least memory, input unit, display unit, processor, and power supply components. The memory may be configured to store software programs and modules, such as program instructions/modules corresponding to the PCB package design method and apparatus in the embodiments of the present invention, and the processor executes various functional applications and data processing by running the software programs and modules stored in the memory, such as the PCB package design method provided in the embodiments of the present invention. The memory may include non-volatile memory, such as at least one magnetic disk storage device or other volatile solid state storage device.
The input unit may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the computer. The display unit may be used to display information input by the user or information provided to the user. The display unit may include a display panel, and optionally, the display panel may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like.
The processor is a control center of the computer, connects various parts of the entire computer using various interfaces and lines, and performs various functions of the computer and processes data by operating or executing software programs and/or modules stored in the memory and calling data stored in the memory. Alternatively, the processor may include one or more processing units; preferably, the processor may integrate the application processor and the modem processor.
The power supply is used for supplying power to each component, and preferably, the power supply can be logically connected with the processor through the power management system, so that functions of charging, discharging, power consumption management and the like can be managed through the power management system.
The PCB packaging design method and the PCB packaging design device provided by the embodiment of the invention have the same technical characteristics, can solve the same technical problems and achieve the same technical effect.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions or without necessarily implying any relative importance. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
The embodiment of the invention also discloses:
A1. a PCB packaging design method is applied to Allegro software and comprises the following steps:
when the current device packaging library is provided with a forbidden region, binding elements in the device packaging library, wherein the elements at least comprise the forbidden region;
when the device packaging library is called to design a PCB, displaying a device graph corresponding to the device packaging library, and binding the forbidden arrangement region in the device graph;
and designing the PCB based on the device graph.
A2. The method of a1, the step of performing a binding operation on an element in the device package library comprising:
prompting whether to perform binding operation on the elements;
and when an operation instruction of binding the elements is received, setting the attributes of the elements in the device packaging library as binding attributes.
A3. The method of a2, wherein the step of setting the property of the element in the device package library as a bound property comprises:
calling a Drawing attribute corresponding to the device packaging library;
and setting the binding property in the Drawing property to be in a selected state.
A4. The method of a1, the step of performing PCB design based on the device pattern, comprising:
receiving an operation instruction of a user;
and designing the PCB according to the operation instruction.
A5. According to the method of a4, the step of designing the PCB according to the operation instruction includes:
when an forbidden zone deleting instruction is received, reading the attribute of a forbidden zone corresponding to the forbidden zone deleting instruction;
and when the binding property is read, sending a prompt message to a user that the deletion of the forbidden region simultaneously deletes the device graph.
A6. The method as in A5, wherein the step of sending a prompt to a user that deleting the keep-out region will delete the device graphic at the same time comprises:
and displaying the prompt information for deleting the device graph simultaneously to the user by deleting the forbidden region in an information prompt box mode.
A7. The method as in A5, wherein the step of sending a prompt to a user that deleting the keep-out region will delete the device graphic at the same time comprises:
and sending prompt information to a user in a dialog box form, wherein the prompt information indicates whether the device graph is deleted and continues to be deleted when the forbidden region is deleted.
A8. The method of a7, wherein after the step of prompting a user that deletion of the keep-out region will simultaneously delete the device graphic, the method further comprises:
and deleting the device graph when receiving an instruction of continuing the deleting operation.
A9. The method of any of a1-A8, wherein the step of performing a binding operation on an element in the device package library when the current device package library carries a keep-out region comprises:
when an instruction for storing a current device packaging library is received, judging whether the device packaging library has a forbidden deployment area, if so, binding elements in the device packaging library, and storing the device packaging library after the binding operation; alternatively, the first and second electrodes may be,
and searching a device packaging library with a forbidden region from the established device packaging library, and binding the elements in the currently searched device packaging library.
B10. A PCB packaging design device is applied to Allegro software and comprises:
the device packaging system comprises an element binding module, a component packaging module and a component packaging module, wherein the element binding module is used for binding elements in a device packaging library when the current device packaging library is provided with a forbidden region, and the elements at least comprise the forbidden region;
the packaging library calling module is used for displaying a device graph corresponding to the device packaging library when the device packaging library is called to design the PCB, and the forbidden arrangement region is bound in the device graph;
and the PCB design module is used for designing the PCB based on the device graph.
B11. The apparatus of B10, the element binding module further configured to:
prompting whether to perform binding operation on the elements;
and when an operation instruction of binding the elements is received, setting the attributes of the elements in the device packaging library as binding attributes.
B12. The apparatus of B11, the element binding module further configured to:
calling a Drawing attribute corresponding to the device packaging library;
and setting the binding property in the Drawing property to be in a selected state.
B13. The apparatus of B10, the PCB design module further to:
receiving an operation instruction of a user;
and designing the PCB according to the operation instruction.
B14. The apparatus of B13, the PCB design module, comprising:
the attribute reading unit is used for reading the attribute of the forbidden zone corresponding to the forbidden zone deleting instruction when the forbidden zone deleting instruction is received;
and the information prompting unit is used for sending a prompting message to a user that the device graph is deleted at the same time when the binding property is read.
B15. The apparatus according to B14, wherein the information prompt unit is configured to display to a user, in the form of an information prompt box, a prompt to delete the keep-out area and a prompt to delete the device graphic at the same time.
B16. According to the device of B14, the information prompting unit is configured to send a prompt to a user in the form of a dialog box to prompt whether deleting the prohibited area will delete the device graphic at the same time and continue.
B17. The apparatus of B16, the PCB design module, further comprising:
and the device deleting unit is used for deleting the device graph when receiving the instruction of continuing the deleting operation.
B18. The apparatus of any of B10-B17, the element binding module further to:
when an instruction for storing a current device packaging library is received, judging whether the device packaging library has a forbidden deployment area, if so, binding elements in the device packaging library, and storing the device packaging library after the binding operation; alternatively, the first and second electrodes may be,
and searching a device packaging library with a forbidden region from the established device packaging library, and binding the elements in the currently searched device packaging library.
C19. A computer storage medium storing computer software instructions for use with the apparatus of any one of B10 to B18.
Claims (17)
1. A PCB packaging design method is characterized in that the method is applied to Allegro software and comprises the following steps:
when the current device packaging library is provided with a forbidden region, binding elements in the device packaging library, wherein the elements at least comprise the forbidden region;
when the device packaging library is called to design a PCB, displaying a device graph corresponding to the device packaging library, and binding the forbidden arrangement region in the device graph;
performing PCB design based on the device graph;
the step of binding the elements in the device package library includes:
prompting whether to perform binding operation on the elements;
when an operation instruction of binding elements is received, setting the attributes of the elements in the device packaging library as binding attributes;
the step of prompting whether to perform the binding operation on the element specifically includes:
prompting a user whether to perform element binding operation on the device packaging libraries in the Allegro software or not for the established device packaging libraries;
the step of setting the attribute of the element in the device package library to be the binding attribute specifically includes:
and searching the device packaging library with the forbidden region from the established device packaging library, and binding the elements in the searched device packaging library one by one to bind the forbidden region with the corresponding device.
2. The method of claim 1, wherein the step of setting the property of the element in the device package library to a bound property comprises:
calling a Drawing attribute corresponding to the device packaging library;
and setting the binding property in the Drawing property to be in a selected state.
3. The method of claim 1, wherein the step of performing PCB design based on the device pattern comprises:
receiving an operation instruction of a user;
and designing the PCB according to the operation instruction.
4. The method of claim 3, wherein the step of performing PCB design according to the operation command comprises:
when an forbidden zone deleting instruction is received, reading the attribute of a forbidden zone corresponding to the forbidden zone deleting instruction;
and when the binding property is read, sending a prompt message to a user that the deletion of the forbidden region simultaneously deletes the device graph.
5. The method of claim 4, wherein the step of sending a prompt to a user that deleting the keep-out region will simultaneously delete the device graphic comprises:
and displaying the prompt information for deleting the device graph simultaneously to the user by deleting the forbidden region in an information prompt box mode.
6. The method of claim 4, wherein the step of sending a prompt to a user that deleting the keep-out region will simultaneously delete the device graphic comprises:
and sending prompt information to a user in a dialog box form, wherein the prompt information indicates whether the device graph is deleted and continues to be deleted when the forbidden region is deleted.
7. The method of claim 6, wherein after the step of issuing a prompt to a user that deleting the keep-out region will simultaneously delete the device graphic, the method further comprises:
and deleting the device graph when receiving an instruction of continuing the deleting operation.
8. The method according to any one of claims 1 to 7, wherein the step of performing a binding operation on the elements in the device package library when the current device package library has the keep-out region comprises:
when an instruction for storing a current device packaging library is received, judging whether the device packaging library has a forbidden deployment area, if so, binding elements in the device packaging library, and storing the device packaging library after the binding operation; alternatively, the first and second electrodes may be,
and searching a device packaging library with a forbidden region from the established device packaging library, and binding the elements in the currently searched device packaging library.
9. A PCB packaging design device is applied to Allegro software and comprises the following components:
the device packaging system comprises an element binding module, a component packaging module and a component packaging module, wherein the element binding module is used for binding elements in a device packaging library when the current device packaging library is provided with a forbidden region, and the elements at least comprise the forbidden region;
the packaging library calling module is used for displaying a device graph corresponding to the device packaging library when the device packaging library is called to design the PCB, and the forbidden arrangement region is bound in the device graph;
the PCB design module is used for designing a PCB based on the device graph; the element binding module is further configured to:
prompting whether to perform binding operation on the elements;
when an operation instruction of binding elements is received, setting the attributes of the elements in the device packaging library as binding attributes;
wherein, for the established device package library, the element binding module is further configured to:
prompting a user whether to perform element binding operation on all device packaging libraries in the Allegro software;
and when an operation instruction of binding the elements is received, searching the device packaging library with the forbidden region from the established device packaging library, and binding the elements in the searched device packaging library one by one to enable the forbidden region to be bound with the corresponding device.
10. The apparatus of claim 9, wherein the element binding module is further configured to:
calling a Drawing attribute corresponding to the device packaging library;
and setting the binding property in the Drawing property to be in a selected state.
11. The apparatus of claim 9, wherein the PCB design module is further configured to:
receiving an operation instruction of a user;
and designing the PCB according to the operation instruction.
12. The apparatus of claim 11, wherein the PCB design module comprises:
the attribute reading unit is used for reading the attribute of the forbidden zone corresponding to the forbidden zone deleting instruction when the forbidden zone deleting instruction is received;
and the information prompting unit is used for sending a prompting message to a user that the device graph is deleted at the same time when the binding property is read.
13. The apparatus of claim 12, wherein the information prompting unit is configured to display, in the form of an information prompting box, a prompting message to a user that the forbidden area is deleted and the device graphic is deleted at the same time.
14. The apparatus of claim 12, wherein the information prompting unit is configured to issue a prompt to a user in the form of a dialog box whether deleting the keep-out region will continue while deleting the device graphic.
15. The apparatus of claim 14, wherein the PCB design module further comprises:
and the device deleting unit is used for deleting the device graph when receiving the instruction of continuing the deleting operation.
16. The apparatus of any of claims 9-15, wherein the element binding module is further configured to:
when an instruction for storing a current device packaging library is received, judging whether the device packaging library has a forbidden deployment area, if so, binding elements in the device packaging library, and storing the device packaging library after the binding operation; alternatively, the first and second electrodes may be,
and searching a device packaging library with a forbidden region from the established device packaging library, and binding the elements in the currently searched device packaging library.
17. A computer storage medium storing computer software instructions for use in the apparatus of any one of claims 9 to 15.
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| CN110244215A (en) * | 2019-06-17 | 2019-09-17 | 蔚复来(浙江)科技股份有限公司 | A kind of integrated security distance automaticly inspects the PCB encapsulation design method of function |
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| US7587695B2 (en) * | 2001-12-10 | 2009-09-08 | Mentor Graphics Corporation | Protection boundaries in a parallel printed circuit board design environment |
| US7546571B2 (en) * | 2004-09-08 | 2009-06-09 | Mentor Graphics Corporation | Distributed electronic design automation environment |
| CN100461190C (en) * | 2006-05-16 | 2009-02-11 | 英业达股份有限公司 | System and method for wiring realtime interactive printing circuit board |
| CN101079080A (en) * | 2007-07-17 | 2007-11-28 | 华为技术有限公司 | Printed circuit board plate frame generation method |
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