CN107359874B

CN107359874B - Integrated circuit, device including integrated circuit, and integrated circuit chip

Info

Publication number: CN107359874B
Application number: CN201710702456.6A
Authority: CN
Inventors: J·P·莱索
Original assignee: Cirrus Logic International Semiconductor Ltd
Current assignee: Cirrus Logic International Semiconductor Ltd
Priority date: 2011-11-21
Filing date: 2012-11-20
Publication date: 2021-01-01
Anticipated expiration: 2032-11-20
Also published as: KR20190086778A; CN104067520A; CN112564701A; CN104067520B; WO2013076470A2; CN107359874A; GB2496673A; KR102000756B1; KR20200069390A; WO2013076470A3; KR102122509B1; KR102222865B1; KR20140103970A; GB2496673B; GB201120016D0

Abstract

The invention provides an integrated circuit, a device comprising the integrated circuit and an integrated circuit chip. The integrated circuit includes: a clock generator for generating a continuous output clock signal, including a first clock signal input for receiving a first input clock signal and a second clock signal input for receiving a second input clock signal; at least one digital audio interface receiving digital audio data and an accompanying audio data clock; a digital-to-analog converter for reconstructing analog audio data based on the received digital audio data; the audio data clock is supplied as a first input clock signal to a clock generator, an output clock signal of the clock generator being used as a clock for the digital-to-analog converter; the received digital audio data and the accompanying audio data clock are received by the device in burst mode, the digital-to-analog converter being continuously supplied with an output clock signal of the clock generator, the output clock signal of the clock generator being based on the first input clock signal and the second input clock signal.

Description

Integrated circuit, device including integrated circuit, and integrated circuit chip

The application is a divisional application of an invention patent application with an application date of 2012, 11/20, an application number of 201280067552.3 and a name of 'clock generator'.

Technical Field

The present invention relates to frequency locked loops, and in particular to frequency locked loops suitable for use as clock generators in the form of integrated circuits.

Background

It is known to use a Frequency Locked Loop (FLL) to generate a clock signal at a frequency that is a multiple of the frequency of the existing (input) clock signal. For example, the high frequency output clock clocks a counter. On the edge of the existing clock signal, the accumulated count is latched and the counter is reset. Thus, the count represents the ratio of the frequency of the output clock to the frequency of the existing clock. This ratio is subtracted from the input value representing the ideal ratio and the frequency error signal thus obtained is fed to the filter. The filter integrates the frequency error to produce an integrated error signal, which is used to drive a numerically controlled oscillator whose output is fed back as a high frequency output clock to clock a counter. The output clock being fed back means that if the frequency of the output clock becomes higher than the ideal frequency, a negative frequency error signal is generated, resulting in the output frequency being lowered. Conversely, if the frequency of the output clock becomes lower than the ideal frequency, a positive frequency error signal is generated, resulting in an increase in the output frequency. Therefore, the frequency of the generated clock converges to the ideal frequency.

One application of such a frequency locked loop is in digital audio signal processing or reproduction circuitry, and in host devices employing such circuitry, including but not limited to: portable electronic devices, mobile phones, personal digital assistants, netbooks, laptops, tablets, computers. For high quality audio reproduction, it is important that the clock driving the output digital-to-analog converter has low jitter (especially within the audio frequency band) to avoid noise, distortion or spurious tones. The clock accompanying the input data may not be of high quality due to poor quality clock sources or degradation along the transmission channel, and the clock used for signal processing may need to be a multiple of the data transmission clock.

Moreover, the generated clock must be closely synchronized with the incoming data: any accumulated clock slip results in gaps in the discarded samples or data to be processed.

Furthermore, in some applications, the clock may be intermittent, possibly because the data is transmitted in bursts. Alternatively, when the modality of the host device is changed to service different usage scenarios and save any unnecessary power consumption, the clock source may change. However, any such clock transitions should be imperceptible in the reproduced audio.

Also preferably, for an economical implementation in integrated circuit form, there should be as few external components as possible, such as large capacitors: a digital based solution is ideal.

Disclosure of Invention

According to a first aspect of the present invention, there is provided a clock generator for generating an output clock signal, the clock generator comprising:

a first clock signal input for receiving a first input clock signal;

a first frequency comparator for generating a first frequency comparison signal based on a ratio of the frequency of the output clock signal to the frequency of the first input clock signal;

a first subtractor for forming a first error signal representing a difference between an input ideal frequency ratio and the first frequency comparison signal;

a first digital filter for receiving the first error signal and forming a filtered first error signal;

a second clock signal input for receiving a second input clock signal;

a second frequency comparator for generating a second frequency comparison signal based on a ratio of the frequency of the output clock signal to the frequency of the second input clock signal;

a second subtractor for forming a second error signal representing a difference between the filtered first error signal and the second frequency comparison signal;

a second digital filter for receiving the second error signal and forming a filtered second error signal; and

a numerically controlled oscillator for receiving the filtered second error signal and generating the output clock signal.

According to a second aspect of the present invention, there is provided an audio processing integrated circuit comprising:

at least one digital audio interface for receiving digital audio data and an accompanying audio data clock;

a digital-to-analog converter for reconstructing analog audio data based on the received digital audio data; and

the clock generator according to the first aspect, wherein the audio data clock is provided to the clock generator as a first input clock signal, and an output clock signal of the clock generator is used as a clock for the digital-to-analog converter.

According to a third aspect of the invention, there is provided an apparatus containing an audio processing integrated circuit according to the second aspect, and further comprising:

a communication processor for receiving a cellular call, the processor coupled to the at least one digital audio interface via a digital audio bus; and/or

An application processor for retrieving audio data from a local memory, the processor coupled to the at least one digital audio interface via a digital audio bus; and/or

A wireless modem for transmitting and/or receiving audio data from a peripheral device, the modem coupled to the at least one digital audio interface via a digital audio bus.

According to a fourth aspect of the invention, there is provided an integrated circuit comprising:

a clock generator according to the first aspect;

a first oscillator for generating a first oscillator clock signal and connected to a first clock signal input of the clock generator; and

a second oscillator for generating a second oscillator clock signal and connected to a second clock signal input of the clock generator,

wherein the first and second oscillators are configured such that the first oscillator clock signal has a lower jitter than the second oscillator clock signal and the second clock signal has a higher frequency accuracy than the first oscillator clock signal.

Drawings

For a better understanding of the present invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:

FIG. 1 is a schematic diagram illustrating the general form of a frequency generator according to the present invention;

FIG. 2 shows the frequency generator as shown in FIG. 1 in more detail;

FIG. 3 is a frequency plot illustrating the performance of the frequency generator of FIG. 2;

FIG. 4 shows a first alternative frequency generator according to the present invention;

FIG. 5 shows a second alternative frequency generator according to the present invention;

FIG. 6 shows a third alternative frequency generator according to the present invention;

fig. 7(a), 7(b), 7(c), 7(d), 7(e) and 7(f) show in more detail possible forms of numerically controlled oscillators in a frequency generator according to the invention;

FIG. 8 shows a first system comprising a frequency generator according to the invention;

fig. 9 shows a first possible form of a delta-sigma modulator in the system of fig. 8;

fig. 10 shows a second possible form of the delta-sigma modulator in the system of fig. 8;

fig. 11 shows a third possible form of a delta-sigma modulator in the system of fig. 8;

FIG. 12 illustrates a first known audio processing channel;

FIG. 13 illustrates a second known audio processing channel;

FIG. 14 shows an audio processing channel incorporating a frequency generator according to the present invention;

FIG. 15 shows a second system comprising a frequency generator according to the invention;

FIG. 16 shows a third system incorporating a frequency generator according to the invention;

FIG. 17 shows a fourth system comprising a frequency generator according to the invention;

fig. 18 shows a fifth system comprising a frequency generator according to the invention.

Detailed Description

FIG. 1 shows a clock generationA frequency generator (or equivalently, a frequency synthesizer) 10 which operates using the principle of a frequency locked loop. The clock generator 10 may be provided, for example, in the form of an integrated circuit, or may be provided as a functional module as part of a larger integrated circuit. The clock generator 10 receives a first input clock signal DCK having a frequency f and a second input clock signal RCK and generates an output clock signal CKout_DCKThe second input clock signal RCK having a frequency f_RCKThe output clock signal CKout has a frequency f_CKout. The clock generator 10 also receives at the frequency control input FC an input value or frequency control word P representing a desired value of the ratio of the frequencies of the output clock signal CKout and the first input clock signal DCK. Thus, when the user wishes to generate a signal having a frequency f_CKoutAnd at an available frequency f_DCKWith the clock signal DCK, the value of P is set equal to f_CKout/f_DCK。

The output clock signal CKout is applied to a clock input (CK) of the first counter 12, acting as a first frequency detector or first frequency comparator. The first input clock signal DCK is applied to the Reset (RST) input of the first counter 12. Therefore, the first counter 12 counts the number of pulses of the output clock signal CKout generated in each pulse of the first input clock signal DCK, and the count value CNT1 output from the first counter 12 is a first frequency comparison signal indicating a ratio of the frequencies of the output clock signal CKout and the first input clock signal DCK, that is, CNT1 ═ f_CKout/f_DCK。

The input value P input at the frequency control input FC is applied to a first input of the first subtractor 14, and the count value CNT1 (i.e., the first frequency comparison signal) output from the first counter 12 is applied to a second input of the subtractor 14. The resulting first error signal Merr1 is applied to the Input (IN) of the first digital filter 16, which is clocked by the first input clock signal DCK, and generates on its Output (OUT) a filtered first error signal Nerr 1. The first digital filter 16 may be an integrator or some other type of low pass filter having a higher gain at low frequencies and a lower gain at higher frequencies.

The output clock signal CKout is also applied to the clock input (CK) of the second counter 18, acting as a second frequency detector or second frequency comparator. The second input clock signal RCK is applied to the reset input (RST) of the second counter 18. Therefore, the second counter 18 counts the number of pulses of the output clock signal CKout generated in each pulse of the second input clock signal RCK, and the count value CNT2 output from the second counter 18 is a second frequency comparison signal representing the ratio of the frequencies of the output clock signal CKout and the second input clock signal RCK, that is, CNT2 ═ f_CKout/f_RCK。

The filtered first error signal Nerr1 is applied to a first input of the second subtractor 20, and the count value CNT2 (i.e., the second frequency comparison signal) output from the second counter 18 is applied to a second input of the second subtractor 20. The resulting second error signal Merr2 is applied to an Input (IN) of the second digital filter 22, which is clocked by the second input clock signal RCK, and generates on its Output (OUT) a filtered second error signal Nerr 2. The second digital filter 22 may be an integrator or some other type of low pass filter with a higher gain at low frequencies and a lower gain at higher frequencies.

The filtered second error signal Nerr2 is passed to a Numerically Controlled Oscillator (NCO)24 which generates an output clock signal CKout in dependence on its input signal Nerr 2.

In some embodiments,

digital filters

16 and 22 are integrators, or other types of low pass filters, that have higher gain at low frequencies than at higher frequencies. Therefore, for a bounded output value, the average input value of each integrator must be close to zero. The operation of the frequency generator 10 can be understood by considering: in steady state, the feedback loop must operate such that the output signal Merr1 of the first subtractor 14 tends towards zero, i.e. such that:

merr1 ═ P-CNT1 ═ 0, that is,

P＝f_CKout/f_DCKor is or

f_CKout＝P·f_DCK

In this embodiment, the value of P is constant or at least relatively slowly changing over time as compared to either the generated frequency or the loop bandwidth, such that the output clock f_CKoutTracks a slowly varying desired value.

Similarly, it can be shown that:

merr 2-Nerr 1-CNT 2-0, i.e.,

Nerr1＝f_CKout/f_RCK，

i.e. the output of the integrator settles to an average value equal to f_CKout/f_RCK。

In steady state, the output of the second filter 22 will settle to the value required by the NCO 24 to provide the desired frequency P · f at CKout_DCK。

Fig. 2 shows in more detail the form of the frequency generator 10 in a particular embodiment.

As shown in fig. 2, the first counter 12 comprises a delay element 30 which is clocked by the output clock CKout, with the result that for each pulse of the output clock CKout an adder 32 adds the received value +1 to the current count value. A multi-bit storage register 34 (drawn for simplicity as a single-bit D-type flip-flop) receives the current count value in each time period and latches and outputs the accumulated count to the first subtractor 14 on each rising edge of the first input clock DCK. At the same time, the rising edge of the first input clock DCK controls the multiplexer 36 so that the value 0 is transferred to the adder 32. This resets the counter value of the first counter 12 to zero until the next CKout pulse arrives.

There are many possible implementations of the counter module 12: for example, the multiplexer may be omitted such that the output of the delay module is successively increased and then the previously delivered output value is subtracted at each rising edge of the first input clock DCK. Of course, this and other modules may be designed to be triggered on the falling edge rather than on the rising edge.

Therefore, the accumulated count value CNT1 (i.e., the first frequency comparison signal) output to the first subtractor 14 is the number of pulses of the output clock CKout for each cycle of the first input clock DCK, and is made available to the subtractor 14 whenever necessary.

Similarly, the second counter 18 may comprise a delay element 40 which is clocked by the output clock CKout, with the result that the adder 42 adds the received value +1 to the current count value of each pulse of the output clock CKout. The multi-bit storage register 44 receives the current count value in each time period and latches, i.e., outputs, the accumulated count to the second subtractor 20 at each rising edge of the second input clock RCK. At the same time, the rising edge of the second input clock RCK controls the multiplexer 46 so that the value 0 is passed to the adder 42. This resets the counter value of the second counter 18. Furthermore, alternative embodiments of suitable counters are also possible.

Therefore, the accumulated count value CNT2 (i.e., the second frequency comparison signal) output to the second subtractor 20 is the number of pulses of the output clock CKout for each cycle of the second input clock RCK, and is made available to the second subtractor 20 whenever necessary.

In the embodiment shown in fig. 2, the first filter 16 takes the form of an integrator comprising an adder 50, a delay element 52 (the delay element 52 being clocked by the first input clock DCK) and a multiplier 53, with the result that, during each cycle of the first input clock DCK, the value Merr1 received from the first subtractor 14 is added to the previous running total output from the delay element 52 to form a new running total which is then multiplied by a factor γ₁Scaled to form a new filter output value Nerr 1. The multiplier may be just a bit shifter to implement 2^NForm of scaling factor gamma₁Or some other simple shift-and-add structure to implement 2^N1+2^N2Reduction of forms or the likeGamma of radioactive factor₁Rather than a full multiplier (full multiplier), as is known.

Similarly, the second filter 22 takes the form of an integrator of similar construction, comprising an adder 60, a delay element 62 (clocked by the second input clock RCK), and a multiplier 63, with the result that, during each cycle of the second input clock RCK, the value Merr2 received from the second subtractor 20 is added to the previous running total output from the delay element 62 to form a new running total, which is then clocked by γ₂The factor is scaled to form a new filter output value Nerr 2.

As shown in fig. 2, the Numerically Controlled Oscillator (NCO)24 may include a digital-to-analog converter (DAC)70 and a Voltage Controlled Oscillator (VCO)72, and thus the numerically controlled oscillator generates the output signal CKout at a frequency corresponding to the value output by the second integrator.

In this illustrated embodiment, the first integrator is designed to have a much lower gain (i.e., longer time constant) than the second integrator.

Fig. 3 is a frequency plot illustrating jitter transfer functions between various points in the circuit of fig. 2. In particular, the curve 80 represents the jitter transfer function from the DCK input to the NCO output CKout, i.e., the factor by which any jitter present on the DCK input at a particular frequency is scaled when reaching the output CKout. Similarly, curve 82 represents the jitter transfer function from the RCK input to the NCO output CKout, while curve 84 represents the jitter transfer function from the input of the NCO 24 to its output CKout.

The break point is defined by the unity gain frequency of the first integrator and the second integrator. More specifically, the turning point f of the transfer function from the DCK input to the NCO output CKout (i.e., curve 80)₈₀From f₈₀＝f(DCK)*γ₁Is given by/2 pi, wherein gamma₁Is the gain of the first integrator; while the turning point f of the transfer function from the RCK input to the NCO output CKout (i.e., curve 82)₈₂From f₈₂＝f(RCK)*γ₂Is given by/2 pi, wherein gamma₂Is the gain of the second integrator.

In this embodiment, the gain values are set such that: turning point f₈₀Is at about 2Hz (12rad/s) and the turning point f₈₂Is at about 20kHz (120 krad/s).

Since the integrators are all first order integrators, the slope of the

jitter transfer function

80, 82, 84 is approximately 20dB/decade, except that the NCO transfer function 84 is at the lower turning point f₈₀The following has a slope of 40dB/decade, while the RCK transfer function 80 is at the upper turning point f₈₂The above has a slope of minus 40 dB/decade.

Thus, at the intermediate dither frequency-at two turning points f₈₀And f₈₂In between, the long time constant of the first integrator will tend to keep the output Nerr1 of the first integrator constant and thus very little jitter from the first clock signal DCK will propagate to the output, while the second integrator will have a high gain and thus the feedback loop comprising the second integrator and the frequency comparator 18 will control the NCO 24 such that the output CKout of the NCO 24 follows the second clock signal RCK despite the inherent jitter of the NCO 24.

Thus, at these intermediate frequencies, the jitter on the output clock CKout will tend to track the jitter on the second clock signal RCK, while the jitter on the first clock signal DCK will be attenuated by 6dB at 4Hz and more at higher frequencies.

As a result, the circuit shown in fig. 2 is particularly useful for situations where there are two clock signals available, one having a frequency that is intended to be used as a basis for generating the output clock signal CKout but which is of relatively low quality (i.e. it has a relatively high jitter), and the other having a relatively high quality (low jitter) but an inappropriate frequency. In that case, a relatively high jitter clock signal may be used as the first input clock signal DCK to the circuit 10, while a relatively low jitter clock signal may be used as the second input clock signal RCK.

This means that the output clock signal CKout can be generated from the first input clock signal DCK with the desired exact frequency ratio value by suitably selecting the value of P, but also that the jitter on the output clock signal CKout (within the frequency band of interest) depends only on a low level of jitter on the high quality second input clock signal RCK, provided that the gain of the integrator is properly set.

As mentioned above, in this illustrated embodiment, the first integrator is designed to have a much longer time constant than the second integrator. However, the first integrator may have a shorter time constant than the second integrator.

As mentioned above, the integrators are all first order integrators in this embodiment. However, it will be appreciated that higher order integrators may be used, or indeed other filters dependent on the expected jitter spectrum of the input clock or the desired jitter spectrum at the output may be used. For example, it may be desirable to notch out a known interference frequency (notch out), in which case filter 16 may be a notch filter and filter 22 a bandpass filter, with the parameters designed to maintain the stability of both feedback loops.

As described above, the integrator settles to a value equal to f_CKout/f_RCKAverage value of (a). At start-up, typically all circuitry will be reset to zero, so such low bandwidth integrators may take some time to ramp up to the required value.

Fig. 4 shows an alternative frequency generator 90 in which many of the component modules are identical to those of the frequency generator 10. These component modules are denoted in fig. 4 by the same reference numerals as in fig. 1 and 2 and are not described further.

In the frequency generator 90 shown in fig. 4, the count (CNT2) output of the second counter 18 is applied to a first input of a third subtractor 92, and f_CKout/f_RCKIs applied to a second input of the third subtractor 92 to be subtracted from CNT 2. As a result of this subtraction, a frequency comparison signal CNT2X is obtained and applied to the second subtractor 20 to be subtracted from the filtered error signal Nerr 1.

In operation, the output value CNT2 of the second counter 18 must still be equal to f on average_CKout/f_RCKHowever, if RCK is close to the desired frequency, then subtracting Q from CNT2 will give a value close to 0. The new error signal CNT2X forwarded to the second subtractor will now be small, so the first integrator only needs to ramp up to settle to a much smaller value, i.e. only the error in the estimated Q (f;)_CKout/f_RCK-Q), rather than the entire amount of Q. Thus, the time taken to settle to an acceptable accuracy may be greatly reduced.

As an equivalent alternative, rather than using an explicit subtractor 92, the second counter 18 may be preset to a count value-Q such that it subsequently ramps up to a value close to zero during each RCLK cycle. As another equivalent alternative, the output of the integrator may be preset to Q at start-up.

Fig. 5 shows another alternative frequency generator 110 in which many of the component modules are identical to those of the frequency generator 10. These component modules are denoted in fig. 5 by the same reference numerals as in fig. 1 and 2 and are not described further.

In the frequency generator 110 shown in fig. 5, the output clock CKout is not passed directly to the first counter 12 and the second counter 18, but is passed through a common frequency divider 116 and then through a first frequency divider 112 and a second frequency divider 114, respectively. Common divider 116 receives a common division ratio N₀And at a frequency f_CKout/N₀The common divided clock signal CKout0 is generated. The first frequency divider 112 receives a first frequency dividing ratio N₁And at a frequency f_CKout/N₀N₁The first divided clock signal CKout1 is next generated, which is supplied by the first frequency divider to the Clock (CK) input of the first counter 12. Similarly, the second frequency divider 114 receives a second division ratio N₂And at a frequency f_CKout/N₀N₂A second divided clock signal CKout2 is generated which is supplied by the second frequency divider to the Clock (CK) input of the second counter 18.

The common frequency divider 116, the first frequency divider 112 and the second frequency divider 114 may be fixed frequency dividers and they have the effect that the first counter 12 and the second counter 18 may run slower than if the first counter 12 and the second counter 18 were directly supplied to output the clock CKout, which has the advantage that: the power consumption is reduced and it is only required that the

counters

12, 18 are able to count to smaller values without seriously affecting the frequency f of the output clock CKout_CKoutOr jitter accuracy. If desired, the common divided clock signal CKout0, the first divided clock signal CKout1, and/or the second divided clock signal CKout2 may be provided as clock signals to other blocks of a larger circuit. One or more of the

dividers

112, 114, 116 may be unnecessary and omitted, as desired.

Alternatively, one or more of these dividers may be configurable during operation to provide different input clock frequencies or different system requirements for different operating modes by altering the values of N1 and/or N2. The frequency divider may be implemented as multiple chains (chains) of "divided-by-2 stages" to implement 2^NA form of frequency division ratio or may be a counter that includes decoding and appropriate reset logic or other similar techniques as is known.

In some applications, one or both of the input clock signals (DCK, RCK) may not always be present. It is desirable to still maintain some output clock in the above situation to allow at least some of the portions of the host system to continue to operate.

In the implementation described above, if the first input clock signal DCK disappears while the second input clock signal RCK is still present, the filtered error signal Nerr1 becomes constant and NCO 24 is only controlled by the loop including the second counter 18. This loop will keep the output frequency at one frequency based on the freeze value of Nerr1 and the frequency of RCK.

Alternatively, if in the above described embodiment the second input clock signal RCK disappears, the second digital filter 22 will become unlocked and therefore the output Nerr2 of this filter will remain at its last value. This will result in the NCO output frequency becoming constant at a frequency corresponding to this value.

Fig. 6 shows another alternative frequency generator 130 in which the component modules are many of the same as the component modules of the frequency generator 10. These component modules are denoted in fig. 6 by the same reference numerals as in fig. 1 and 2 and are not described further.

In the frequency generator 130 shown in fig. 6, a first clock detector 132 is connected to an input receiving a first clock signal DCK and is used to control a first limiter block 134. Similarly, a second clock detector 136 is connected to an input that receives a second clock signal RCK and is used to control a second slicer module 138.

Clock detectors

132, 136 and

limiter modules

134, 138 are provided to handle problems that may arise if the input clock becomes temporarily unavailable. For example, if the first clock signal DCK disappears, there will be a slightly different frequency when it reappears (possibly because the frequency of the upstream clock generator has drifted with temperature changes, or possibly even because the signal is being obtained from a different clock source). If the second clock RCK disappears, the NCO 24 runs open loop for a period of time and the frequency of the NCO 24 may have drifted before the time the RCK signal reappears. A step change in the effective input clock frequency due to the sudden re-imposition of the clock may result in a large step transient in the frequency comparison signal, which may excite the feedback loop to produce a significant output frequency transient overshoot.

The frequency generator 130 shown in fig. 6 helps alleviate these problems because the

clock detectors

132, 136 detect when the respective clock signals DCK, RCK are not present, and then detect when the respective clock signals DCK, RCK reappear.

Clock detectors

132, 136 next limit the input of respective

digital filters

16, 22 during a recovery period after the clock signal reappears to help reduce any large signal transient overshoot within the loop, and thus reduce any transient overshoot in the output frequency.

The Numerically Controlled Oscillator (NCO)24 may take many possible forms. Fig. 2 shows the NCO 24, which NCO 24 includes a voltage output DAC70 that drives a voltage controlled oscillator 72. As an alternative, fig. 7(a) shows an NCO in the form of a simple RC oscillator 440, the RC oscillator 440 having a digitally programmable resistor element 442 and a capacitor element 444, while fig. 7(b) shows an NCO in the form of a transconductance/capacitor (Gm-C) ring oscillator 446, also having digitally

programmable resistor elements

448a, 448b, 448C and

capacitor elements

450a, 450b, 450C.

Fig. 7(c) shows in more detail one possible form of the

programmable capacitor element

444 or 450a, 450b, 450c with a plurality of

capacitors

452a, 452b, 452c connectable in parallel combination by means of switches 454a, 454b, 454c comprising MOS transistors or other suitable active devices. In other embodiments, some or all of the capacitors comprising the programmable capacitor element can be connectable in series to other capacitors.

Fig. 7(d) shows in more detail the form of the programmable resistor element 442 with a plurality of

resistors

456a, 456b, 456c, 456d connectable in series or in a parallel combination by means of switches comprising MOS transistors or other suitable active devices.

Thus, in fig. 7(c) and 7(d), the respective bits of the binary signal representing or derived from the numerical input can control which of the capacitors and resistors are connected and thus can control the frequency of the oscillator.

Fig. 7(e) shows an alternative NCO in which the oscillator element is a ring oscillator 458, in which case the source current is digitally controllable. (similarly, the source voltage or other bias voltage of the ring oscillator may be digitally controllable.) thus, in figure 7(e), the ring oscillator 458 comprises three

inverter stages

460a, 460b, 460c (possibly simple CMOS inverter stages), although of course any suitable number of such inverters may be provided. Three

PMOS transistors

462a, 462b, 462c are arranged in an array to represent a binary of the value inputThe corresponding bit of the control signal may control whether the gate of the PMOS transistor is connected to the appropriate bias voltage V_BOr source voltage V_DD. Is connected to a bias voltage V_BCan be used to drive the total current I of the inverter chain_ctrlContributes and thus controls the source voltage V of the ring oscillator 458_ctrlAnd an output frequency.

However, the output of a digital filter will typically be 20 to 30 bits wide, however, it is not practical to provide enough passive components to provide such high resolution directly. To alleviate this problem, word length reduction techniques may be used.

Fig. 7(f) shows one possible form of a Numerically Controlled Oscillator (NCO)140 that can be used in place of the Numerically Controlled Oscillator (NCO)24 described above. The Numerically Controlled Oscillator (NCO)140 includes a digital-to-analog converter (DAC)70 and a Voltage Controlled Oscillator (VCO)72, which have the same functions as the blocks denoted by the same reference numerals in fig. 2, and these will not be described further. In the Numerically Controlled Oscillator (NCO)140, the values output by the second digital filter 22 are first passed to a Word Length Reduction (WLR) circuit 142, such as a noise shaper or delta-sigma modulator. This helps to ensure that any noise resulting from quantizing this value is pushed out to higher frequencies where the noise will not have any significant effect on the output jitter at low and intermediate frequencies. The output of the word size reduction (WLR) circuit 142 is then passed to a digital-to-analog converter (DAC) 70.

The output of the digital-to-analog converter (DAC)70 may be passed to an analog low pass filter 144 to further help attenuate quantization noise introduced by the DAC70 and help decouple any other high frequency noise from the local ground of the VCO. The filtered low pass signal is then passed to a Voltage Controlled Oscillator (VCO)72 to generate an output signal CKout at a frequency corresponding to the value of the integrator output.

This allows a relatively low resolution (possibly 6 bits) DAC to have a much finer effective dc resolution (e.g. 16 bits) in terms of the average applied to the VCO and the corresponding output frequency accuracy.

Similarly, the word length reduction circuit may be used to control programmable resistor and/or capacitor elements in the structure shown in fig. 7(a) or 7(b), or PMOS transistors in the structure shown in fig. 7 (e). In the example of FIG. 7(e), capacitor C_filtWill act as a low pass filter element.

To this end, the value P applied to the frequency control input FC has been assumed to be constant over time, or at least to change slowly over time compared to any generated frequency or loop bandwidth, so that the frequency of the output clock tracks a slowly varying desired value corresponding to P.

Alternatively, the change may be fast enough, that is, exceeding the FLL loop bandwidth, such that the effect of the first and second low pass filters 16, 22 is to cause the output clock f to be_CKoutIs dependent on the average value of P and any modulation for this frequency is insignificant. For example, P may alternate rapidly between two or more adjacent values such that the average of the two or more adjacent values represents the ideal frequency, or the input value P applied to the first input of the first subtractor 14 may be any sequence or stream of values having the ideal characteristics in terms of average value and quantization noise spectrum, and may for example be a stream of multi-or single-bit words output from a multi-or single-bit delta-sigma modulator.

Fig. 8 shows another alternative frequency generator 120, in which inputs having values "a" and "b" are input to a modulator 122, such as a delta-sigma modulator, to generate a stream of output values having an average value a/b. An accurate fractional average output value can be obtained by supplying the integer values a and b. The stream of output values is supplied to the frequency generator submodule 124 for use as a frequency control word applied to the input FC. The frequency generator submodule 124 may take the form of any of the frequency generators described herein (i.e.,

frequency generators

10, 90, 110, 130), and the stream of output values is supplied as the input ideal value P of the frequency ratio. Thus, if it is desired to generate an output clock signal at a frequency that is an exact fractional multiple of the available clock frequency, the modulator 122 may be used to generate an ideal value for the multiple by selecting the appropriate values of a and b, and this value may be supplied as the ideal multiplication factor P to the frequency generator sub-module 124 in the form of a stream of modulator output values.

Fig. 9 illustrates a first order delta sigma modulator 330 for use as the modulator 122 in one embodiment of the invention. The delta-sigma modulator 330 comprises a first input terminal 331 for receiving a first input value a. The adding element 332 (which may be an adder) receives the first input value a from the first input terminal 331. A memory element 334 is coupled to the output of the summing element 332 and maintains the cumulative count. The output of the memory element 334 is coupled to a modulo element (moduluselement)336 and a comparison element 338, which comparison element 338 may be a comparator. The delta-sigma modulator 330 also comprises a second input terminal 335 for receiving a second input value b, which is provided to the modulo element 336 and the comparison element 338. The comparing element 338 provides a first output m on one output line 339 and the modulo unit 336 provides a second output on a second output line 340, which is also fed back to the adding element 332.

Thus, the delta-sigma modulator 330 has two

input terminals

331, 335 for receiving a first input value a and a second input value b. Input a represents the numerator of the fractional input and input b represents the denominator of the fractional input. The first input value a and the second input value b are thus selected such that a/b is P.

Preferably, although not necessarily, the input values a and b are selected such that they are relatively prime, i.e., they have no other common factor than 1, to eliminate tones in the output of the delta-sigma modulator 330. If the input values a and b are not relatively prime, the tones present in the output may sacrifice performance, especially in audio systems. However, other non-audio systems may be able to tolerate such a sacrifice.

The value b may be represented by a binary word, and in particular the binary word may have more than one non-zero bit, and thus b need not be 2^NIn the form of (1).

In the delta-sigma modulator 330, the addition element 332 adds the first input value a to the accumulated count until the comparison unit 338 determines that the accumulated count held in the memory element 334 is greater than or equal to the threshold value b. When the accumulated count is greater than or equal to threshold b, an output pulse is generated at output 339 and the counter is reset by modulo element 336. That is, the modulo element performs a modulo operation on its input, subtracting the value b from the count value received from the memory element 334, repeatedly subtracting if necessary, until the result is less than b. Therefore, in the delta-sigma modulator 330, the threshold is set by the second input value b, which sets the modular point (modulated point) of the delta-sigma modulator.

The modulo point or roll over point (rolover point) of the delta sigma modulator is a threshold b which, when exceeded by the accumulated count, causes a pulse to be output at output 339 and the count to be reset.

The ability to set the modulo point to the second input value b enables the delta sigma modulator to synthesize according to the basis b. Thus, the average of the pulse density of the output 339 is exactly equal to a/b, since the composite is quantized to b, which is the denominator of the input a/b. Use does not have 2^NThe ability to form b values allows for the precise synthesis of a wider range of frequencies, rather than having ratios that are rounded to a certain number of binary digits.

In the case where the accumulated count exceeds the threshold, an excess amount by which the accumulated count is larger than the threshold is dumped (rolled out) as a remainder at the start of the next addition cycle.

The output terminal 340 outputs the error value of the delta-sigma modulator 330. The error value is reduced in higher order delta-sigma modulators because it is cascaded to the following delta-sigma modulation stages. In a first order delta-sigma modulator (such as the delta-sigma modulator 330 shown in fig. 9), the error values are discarded.

The invention is not limited to first order delta sigma modulators and may also be used in higher order modulators. Higher order modulators contain at least two delta-sigma modulation stages and a recombination stage at the output of each stage to combine the outputs to produce a pulse density modulated output.

Conventionally, modulo operations (such as performed by modulo unit 336) are computationally expensive. Fig. 10 shows an alternative delta-sigma modulator 341 for use in an embodiment of the invention, in which the modulo units are simplified into a multiplexer 342 and a subtractor 344.

The delta-sigma modulator 341 operates in a similar manner as described with respect to the delta-sigma modulator 330 of fig. 9. The first input value a from the input terminal 331 is added to the accumulated count held in the memory unit 334 by the addition element 332. The accumulated count is input to the multiplexer 342 together with the accumulated count from the subtractor 344 minus the input value b input from the input terminal 335. The multiplexer 342 selects an output from one of the inputs based on whether the compare element 338 determines that the accumulated count is greater than or equal to the input value b. If the compare element 338 determines that the cumulative count is greater than or equal to the input value b, the compare element 338 outputs a pulse at output 339 that is also passed to the multiplexer 342 indicating that the multiplexer 342 should select the output with the cumulative count minus the input value b for feedback to the add element 332. This simplified circuit is an acceptable alternative to the circuit shown in figure 9 if the relationship between the values a and b is known such that the value b is not required to be subtracted repeatedly. As a simplified circuit, this will have a smaller chip area and therefore a lower cost, and in addition has the advantage of lower power consumption.

Fig. 11 illustrates an example of a third order delta-sigma modulator 400 according to an embodiment of the invention. The delta-sigma modulator 400 comprises a first input terminal 401 for receiving a first input value a. The adding element 402 receives a first input value a from a first input terminal 401. Coupled to the output of the summing element 402 is a first delta-sigma modulation stage 404, which first delta-sigma modulation stage 404 may take the form of the delta-sigma modulator 330 shown in fig. 9 or the delta-sigma modulator 341 shown in fig. 10. The first output 405 of the first delta-sigma modulation stage 404 is coupled to the recombination stage 420, the first output 405 being a pulse density modulated signal, the average of which is

A first delta sigma modulation stage 404The two outputs 406 are the error of the first delta-sigma modulation stage 404₁The second output 406 is coupled to an input of a second delta-sigma modulation stage 407, which may take the form of the delta-sigma modulator 330 shown in fig. 9 or the delta-sigma modulator 341 shown in fig. 10. The first output 408 of the second delta-sigma modulation stage 407 is coupled to the recombination stage 420, the first output 408 being a pulse density modulated signal, the average of which is

The second output 409 of the second delta-sigma modulation stage 407 is the error of the second delta-sigma modulation stage 407₂The second output 409 is coupled to an input of a third delta-sigma modulation stage 410, which may take the form of the delta-sigma modulator 330 shown in fig. 9 or the delta-sigma modulator 341 shown in fig. 10. The output 411 of the third delta-sigma modulation stage 410 is coupled to the recombination stage 420, the output 411 being a pulse density modulated signal, the average of which is

The delta-sigma modulator 400 further comprises a second input terminal 434 for receiving a second input value b. Although not shown in fig. 11, the second input value b is provided to the delta-sigma modulation stages 404, 407, 410. As previously discussed, the second input value b determines the modulo point of the delta-sigma modulation stage.

The recombination stage 420 will output from the three

modulation stages

404, 407, 410, respectively

And

combined to produce an output 432 in a manner known per se to those skilled in the art and therefore not described further herein.

A dither unit 430 (which receives a dither control signal) applies dither to the adding element 402. The dither is a form of intentionally applied noise that is applied in order to randomize the quantization error and prevent or at least substantially reduce tones that form within the output of the delta-sigma modulator 400. Dither is introduced for cancelling tones in the power/frequency response of the delta-sigma modulator in a manner known per se to the person skilled in the art and will therefore not be described further here.

Thus a clock generator has been described which has a number of advantageous characteristics.

Such a clock generator as described above is useful in consumer/host devices that include audio rendering or other audio signal processing, such as, but not limited to, smart phones, game consoles, tablets, laptop computers, desktop computers, hi-fi systems, and the like. In such applications, it is necessary to use a clock with low jitter and exactly the same frequency as the rate of incoming data (or a multiple thereof) for good audio reproduction to avoid losing or increasing data samples.

Fig. 12 shows a known audio processing channel 150, which in this case may be an audio reproduction channel that accepts input digital data and outputs an analog signal suitable for driving a speaker or headphone directly or indirectly. Incoming data is transmitted according to one or more clocks (e.g., a frame clock or a bit clock in the case of a serial data format). One of these clocks is used to capture incoming data in the Audio Interface (AIF) 151. This Data is then subjected to some digital signal processing (e.g., interpolation or decimation) in a digital signal processing module (DSP)152 to produce processed Data "Data '(Data')", and then output through a delta-sigma DAC 154, the DAC and DSP being clocked according to some processing clock or clocks.

The processing clock may be just a (buffered) version of one of the interface clocks (as indicated by dashed line 155) or may be a frequency generator 156, for example multiplying an incoming frame clock LRCLK at say 48kHz to a higher speed clock (e.g. 3072kHz) CKsys which can be used to clock the output DAC 154.

However, the incoming clock may suffer from some jitter due to distortion or noise added in the transmission, or the clock generator available on the digital processor chip may be of low quality. This jitter, when present at the sampling clock of the DAC, may cause noise, distortion, or spurious intermodulation products (spurrious modulation products).

Fig. 13 shows an alternative audio processing channel 150 in which the DAC clock CKsys is derived from a local clock generator 157. However, especially in systems with multiple channels from multiple sources, the local clock CKsys may not be synchronized to the incoming clock, or may not have the same actual frequency as the incoming clock, even if it is the same nominal frequency. To cope with possible asynchrony between incoming data and the local clock, it is necessary to include an asynchronous sample rate converter module 158 in the signal chain, for example to interpolate or upsample the input data to a very high sample rate, smooth the input data through a filter, and then decimate or downsample the input data to the desired sample rate. This costs considerable digital hardware and power consumption and may degrade audio quality, especially if the input data is companded or otherwise encoded non-linearly.

When the audio processing device 150 is used in a consumer device (such as a smartphone, PDA, or digital camera), the consumer device may include a good quality, low jitter clock for other functions of the device, for example from a crystal that generates a clock signal at 19.2MHz or 12 MHz.

Fig. 14 shows one configuration of an audio processing channel 150 that may be advantageously used in the above scenario, including a frequency generator 159, which frequency generator 159 may take the form of any of the frequency generators described herein (i.e.,

frequency generators

10, 90, 110, 130) or the like.

In this case, the input data is accompanied by a low quality clock CKIN, e.g. an audio word clock LRCLK, whose nominal frequency is 1/P part of the frequency of the output clock CKout. The clock CKIN may then be supplied to a first clock (DCK) input of the frequency generator 159, while the high quality clock from the crystal (XTAL) may be supplied to a second clock (RCK) input of the frequency generator 159. As described above, by suitable selection of the input values, the frequency generator 159 may be caused to generate such a clock signal CKout: this clock signal is synchronized to the long-term frequency of the incoming LRCLK but retains the bass band jitter of the clock signal from the crystal (XTAL). This clock signal may then be supplied to each DSP 152 and DAC 154 that decodes each audio data channel. At least on this one channel or any other channel synchronized to this channel, e.g. the other of the stereo pair, or other channels with a common LRCLK, it is not necessary to provide an Asynchronous Sample Rate Converter (ASRC). As a result, this configuration is advantageous in terms of power, area, etc., compared to alternatives that require low-jitter clocking of the DAC and/or require asynchronous sample rate conversion to allow a different clock basis to maintain accurate frequency and avoid missing data samples.

In practice, the clock delivered to the DAC and/or DSP may actually be a divided down version of the frequency generator output, but such possible dividers are omitted from the figure for simplicity.

Fig. 15 shows an alternative form of bi-directional audio processing channel 160. Thus, when the Audio Interface (AIF)161 receives digital data, it passes the digital data to the digital signal processing module (DSP)162 to produce processed data "data'" which is output through the DAC 164, an ADC 163 receives the analog data, the ADC 163 converts the analog data to digital form, which is then processed in the DSP 162 and output via the AIF 161. The ADC 163 and the DSP 162 and DAC 164 are clocked using a clock signal CKsys output from the frequency generator 159.

Fig. 16 shows the use of a frequency generator as described in a system having multiple audio channels and associated clocks. In particular, fig. 16 shows an audio hub (audio hub) circuit 202, which may be implemented as an integrated circuit, as used in a consumer host device 203, such as a smartphone or portable audio convergence device.

The mobile telephone signals to and from the RF front end 204 are coupled through first processing circuitry (e.g., a cellular communications ("comms") processor 206) that includes an Audio Interface (AIF)207 to communicate these signals to and from a first audio interface 208 on the audio hub 202 in the form of a stream of sampled digital audio data. The "communications" processor 206 includes clock generation circuitry 210, which clock generation circuitry 210 is synchronized to the RF receive/transmit channel, i.e., to the external telephone network. Thus, the sampling rate of the audio data stream between the communication processor and the audio hub is synchronized to the external network.

The consuming/host device 203 may also play back or record audio signals stored in a local memory or removable medium 224 that is coupled to a second interface 226 on the audio hub 202 via second processing circuitry, such as an application ("apps") processor 228, having associated clock circuitry 230 and including an audio interface 232 to transmit these signals to and from the second interface in the form of a stream of sampled digital audio data. The sample rate associated with clocking audio data into and out of the storage medium 224 does not necessarily need to be synchronized to any external reference clock: the sampling rate need only be accurate and stable enough that one does not notice pitch errors. Thus, there is no need to synchronize the sample rate of the audio data stream between the application processor and the audio hub to any external network or other external source.

The host/consumer device 203 may also have other sources of audio data, such as a bluetooth transceiver, FM radio, Wi-Fi transceiver, or high fidelity multimedia interface (HDMI), S/PDIF interface, or USB interface, represented in this example by a PHY module 234 that is directed through further processing circuitry 236, the further processing circuitry 236 including an audio interface 238 to communicate the audio data to and from a third audio interface 240 on the audio hub 202 in the form of a stream of sampled digital audio data. In some cases, these additional audio channels may need to be synchronized to external circuitry or networks, in other cases, this may not be necessary. Thus, the sample rate of the audio data stream between the PHY module and the audio hub may need to be synchronized to an external network or other external source in some usage scenarios, but not in others.

The audio hub 202 also includes a DSP mixer module 260 that may include signal routing, mixing, adaptation, and other DSP functions. Signals from

audio interfaces

208, 226, 240 or from

ADC analog interfaces

268a, 270a, 272a (possibly after processing by optional

dedicated DSP modules

262a, 264a, 266 a) may be mixed, adapted, or otherwise processed by DSP module 260, with the resulting signals being output via

audio interfaces

208, 226, 248 or from

DACs

268b, 270b, 272b (possibly after processing via optional

dedicated DSP modules

262b, 264b, 266 b).

The mixer 260, DSP blocks 262, 264, 266, and DAC/ADC analog interfaces 268, 270, and 272 are clocked by (or may be a clock signal divided or otherwise derived from) a clock signal CKsys generated by a clock generator 256, which clock generator 256 may be included on the same audio hub integrated circuit.

The processing of the entire audio data stream within the DSP module 260 preferably must be synchronized to a common clock CKsys, despite the variety of audio data sample rate synchronization requirements arising from the various differently connected digital audio sources. Thus, preferably, the frequency generator circuit 256 may take the form of any of the frequency generators described herein, i.e.,

frequency generators

10, 90, 110, 130 or the like.

In the embodiment illustrated herein, the clock signal generated by the communication processor 206 and the clock signal generated by the application processor 228 are passed to a multiplexer 258 (or equivalent arrangement). When the device receives a cellular telephone call, the multiplexer 258 is controlled so that the clock signal generated by the clock generator 210 on the communication processor 206 is passed to the DCK input of the frequency generator 256. The frequency generator output clock CKsys is used to process data coupled through the communication processor to maintain data synchronization with the external network. It may also be desirable to simultaneously join data from the local memory 224 via the application processor 228, for example, for recording incoming calls, possibly as a local voicemail function. Because the sample rate of this data need not be synchronized to any external clock reference, this data stream may also be based on the same clock CKsys, rather than using some clock generated, for example, on the application processor, which may require asynchronous sample rate conversion of the audio data stream to be processed in synchronization with CKsys.

The telephony communication type device may, for example, process the audio data stream also when not receiving a network call (e.g., for Mp3/Mp4 file playback). In this case, the cellular communication processor 206 is preferably turned off to conserve power, and the master clock for this system may be generated on the application processor 228 or possibly on some other chip in the system (e.g., power management ic (pmic) 280). Thus, in this case, the multiplexer 258 is controlled such that the clock signal generated or used by the application processor 228 is passed to the DCK input of the frequency generator 256.

The communication-type device may also be required to process audio data streams to/from the other processor 236. In the embodiment of fig. 16, to allow for a usage scenario where these data streams must be synchronized to some external network or external clock source while the audio hub clock CKsys remains audio synchronized with the cellular network based on, for example, a communication processor module, the audio interface 240 includes an Asynchronous Sample Rate Converter (ASRC)242 to generate or accept audio data streams that are synchronized to the CKsys clock from the asynchronous clock used by the processor 236.

In alternative embodiments, this ASRC may be separate from the audio interface, and the audio hub may include routing circuitry to route audio data streams from other audio interfaces through this ASRC, while allowing a path directly between the interface 240 and the DSP module 260, possibly with a third input to the multiplexer 258 to pass the clock from the processor 236 to the clock generator 256, for the following scenarios: where it is desirable to base CKsys on a clock from the processor 236 and possibly convert the sample rate of some other channel, or where audio data passing through the processor 236 does not require synchronization to some external reference. Alternate embodiments may have fewer or more channels, each of which may be substantially similar to one of the three channels already described.

The communication processor 206 and the application processor 228 are large, complex digital circuits, and therefore any clocks emanating from them are likely to be corrupted by on-chip digital crosstalk and thus have high jitter. As mentioned above, the frequency generator 256 has the advantage of reducing this jitter to allow better audio quality. In an application similar to this, with multiple possible master clock sources, there is the additional advantage that when the DCK input is switched to a different source, there may be no glitches in the output clock and the output frequency will not change abruptly because it is locked to the RCK, whereas the input to the NCO 24 in the frequency generator will only change slowly with a time constant on the order of the sub-audio bandwidth of the external loop. Thus, the transition from one system clock to another, for example, if an incoming voice message is recorded to a local voice mailbox while playing certain MP3 music, will be inaudible to the listener.

In other system modes it may be desirable to even turn the application processor 228 off or at least run it at a very slow duty cycle, just to keep the system in some kind of standby mode. In such a mode, the DCK input to the frequency generator may be disabled all together, or at least periodically. As described above, the frequency generator will then continue to generate a clock close to the nominal frequency, based on Nerr1 and the hold value of the RCK frequency. Again, a transition into or out of this standby mode will occur, or appear and disappear periodically with the DCK, without sudden changes in the phase or frequency of the output clock.

Note also that even if RCK were to disappear temporarily, the NCO would continue to oscillate at a frequency corresponding to the holding value of Nerr2, so some clock would still be available to hold some function in the system. This frequency will still be fairly accurate, within the resolution or error of the holding value of Nerr2, although drift may eventually result due to any changes in temperature or source voltage.

FIG. 17 shows a device 170 in which data is supplied from a USB source 172. This data is supplied to the audio and/or video codec 174 via the interface 173 of the device 170. The USB source 172 provides bursts of data, for example, every 1ms or so. Typically, the data is buffered in temporary storage circuitry 175 such as, for example, a FIFO. The buffered data is passed to a digital-to-analog converter (DAC)177 whose analog output can be used, for example, to drive audio from speakers 178 internal to the device, or from speakers external to the device or headphones 179.

The USB source 172 also provides a clock, typically at a frequency of 12 MHz. This clock may be present as long as the USB source 172 is available and connected to the codec 174, or it may disappear between bursts of data. When this clock is only periodically available from the USB source 172, a stable local clock is still needed to provide continuous output data transitions by means of the DAC 177. It is also necessary to avoid glitches when the USB clock is periodically returned to avoid audible artifacts.

When the device 170 is a consumer/host device such as, for example, a smartphone or laptop computer, the device may include a good quality, low jitter clock, for example from a crystal that generates a clock signal at a known frequency, for other functions of the device. In such a case, a frequency generator or clock generator 176 may be advantageously used. The frequency generator 176 may take the form of any of the frequency generators described herein, i.e.,

frequency generators

10, 90, 110, 130 or the like.

The USB clock may then be supplied to a first clock (DCK) input of the frequency generator 176, while the clock from the crystal (XTAL) may be supplied to a second clock (RCK) input of the frequency generator 176. A Frequency Control (FC) word P is also supplied to the frequency generator 176.

This has the effect that the clock signal CKout supplied to the codec 174 can be derived from the USB clock. However, when the USB clock and associated data burst are not present, the output of the integrator in frequency generator 176 will remain constant, and thus the output frequency f_CKoutWill remain at the same fixed ratio as the frequency of the clock from the crystal (RCK). Therefore, the clock signal CKout supplied to the codec 174 will remain close to the desired frequency f_CKout。

There may be small errors in the frequency of the output clock CKout between each burst. The filtered first error signal Nerr1 will typically vary slightly from one DCK cycle to the next due to the finite resolution of the digital filter (i.e., quantization noise) plus any noise that is possibly injected into the loop by any delta-sigma modulation of P or cycle-by-cycle variation of the synchronization of DCK to CKout. To achieve an error of one quarter of a 12MHz DCK period over a 1ms interval between bursts of USB data, Nerr1 is required to have an accuracy of 1/48000. If Nerr1 could be, say, 1/16 at full scale (fullscale) under certain conditions, this requires 20 bits of resolution in Nerr 1. The size of the storage circuitry 175 may be increased slightly to allow temporary storage of a cache of data to accommodate temporary or short term changes in the output clock frequency; the long term frequency will be accurate and therefore errors in the clock will not accumulate so this storage will never overflow if sized appropriately.

In some applications, it is undesirable to use off-chip components, such as, for example, a crystal (XTAL), in order to save space and reduce material cost, and it is therefore desirable to use full on-chip circuitry to generate the required accurate and low jitter clocks.

It is difficult to design a full on-chip oscillator capable of outputting a clock signal having a stable frequency and low jitter characteristics without having to design a complex circuit that requires a large Integrated Circuit (IC) chip area and/or requires a relatively large amount of power to operate. Such IC design difficulties are due to the following factors: IC manufacturing tolerances in doping levels and structure dimensions; and variations in the operating temperature or source voltage of the IC, for example, in subsequent use.

To overcome these problems, a solution has been devised in which a clock generator is provided with a plurality of clock signals generated entirely on-chip.

Fig. 18 illustrates one embodiment of an integrated circuit 180 that includes a clock generator 182 and first and second on-

chip oscillators

186, 184. The clock generator 182 may be any clock generator previously described herein, i.e., a

frequency generator

10, 90, 110, 130 or the like.

The first oscillator 186 may be specifically designed to have an output frequency that is insensitive to temperature and source voltage, but with little concern for jitter. This oscillator may be, for example, a fully on-chip RC-based oscillator, using a temperature-stable on-chip capacitance (as is commonly available) and a zero temperature coefficient resistance. A zero temperature coefficient resistance can be achieved by a suitably designed mesh structure comprising a mix of various types of on-chip resistors, possibly with positive and negative temperature coefficients. To obtain initial absolute frequency accuracy, one or more of the components of first oscillator 186 may be trimmed, i.e., adjusted, during or after manufacturing, so that first oscillator 186 outputs a very accurate desired frequency. Once trimmed, such a time-constant type oscillator will have a relatively stable, i.e. relatively accurate, output frequency, but will have high jitter characteristics.

This first oscillator 186 may be one of the types discussed above and illustrated in fig. 7(a), 7(b), or 7(e), including digitally programmable resistors, capacitors, or other elements whose control digital bits may be stored within on-chip non-volatile memory such as ROM or fusible elements.

The first oscillator 186 is connected to the clock generator 182 such that the output of the first oscillator 186 is supplied as the first input clock signal (DCK) of the clock generator 182. The first input clock signal DCK is therefore a clock signal of relatively accurate frequency but with a relatively high degree of jitter.

The second oscillator 184 should be designed to produce a low jitter clock compared to the first oscillator, but with less concern for frequency accuracy or stability. The second oscillator 184 may be constituted by an oscillator including a full on-chip resonance circuit, for example, an LC type oscillator including an on-chip inductor L and an on-chip capacitor C. Without the impracticability of resorting to designing complex circuits as discussed above, a relatively low power resonant oscillator can be designed using on-chip inductors to provide an output clock signal with low jitter characteristics, but it is difficult to provide an output frequency that is at the same time very insensitive to temperature and source voltage. The difficulty is even more increased for a full on-chip LC oscillator, since in the prior art the resonant circuit comprising the on-chip inductor (L) has a lower Q-factor than an equivalent resonant circuit comprising an off-chip inductor. The second oscillator will thus generate a clock with low jitter but with a time varying frequency.

The second oscillator 184 is connected to the clock generator 182 such that the output of the second oscillator 184 is supplied as a second input clock signal (RCK) of the clock generator 182. The second input clock signal RCK is a relatively low jitter clock signal but with relatively poor frequency accuracy.

As discussed above, the clock generator 182 functions to generate an output clock signal having the frequency accuracy of the clock signal provided by the first oscillator 186, but having the low jitter characteristics of the clock signal provided by the second oscillator 184.

Designing two separate oscillators, each focusing on a respectively different performance aspect, is much easier than trying to meet all requirements with a single oscillator, and such a design provides less complex and therefore cheaper circuits and consumes less power despite the additional circuitry of the clock generator.

The circuit shown in fig. 18 is therefore particularly useful in situations where it is not desirable or possible to use off-chip components for any reason in generating a stable (i.e., accurate) output clock (CKout) with low jitter.

In generating the two clock signals in a fully on-chip manner, one of the clock signals (DCK) having a suitable (i.e. ideal) frequency and being relatively accurate over time but having a relatively high jitter, and the other clock signal (RCK) having an unsuitable (i.e. relatively inaccurate) frequency but having a relatively low jitter characteristic, and using the two clock signals as clock inputs to the clock generator described above, there is an optimum characteristic of each of the two on-chip generated clock signals (RCK, DCK) in the clock generator output signal (CKout).

This means that by a suitable choice of the value of P, the output clock signal CKout can be generated from the second input clock signal DCK at a desired exact frequency ratio, but the jitter on the output clock signal CKout (within the frequency band of interest) depends only on a low degree of jitter on the second input clock signal RCK.

It is noted that the second oscillator may alternatively be constituted by some other relatively high-Q resonant element, for example by means of a MEMS (micro electro mechanical system) type oscillator as part of an integrated circuit.

Thus, a frequency generator for generating a signal at a desired frequency is provided with advantageous properties.

Claims

1. An integrated circuit, the integrated circuit comprising:

a clock generator for generating a continuous output clock signal, said clock generator comprising:

a first clock signal input for receiving a first input clock signal; and

a second clock signal input for receiving a second input clock signal;

a digital-to-analog converter for reconstructing analog audio data based on the received digital audio data;

wherein the audio data clock is provided to the clock generator as a first input clock signal and an output clock signal of the clock generator is used as a clock for the digital-to-analog converter; and

wherein the received digital audio data and the accompanying audio data clock are received by the device in burst mode, and the digital-to-analog converter is continuously supplied with an output clock signal of the clock generator, and the output clock signal of the clock generator is based on a first input clock signal and a second input clock signal.

2. The integrated circuit of claim 1, comprising a first digital audio interface for receiving the first digital audio data stream and an accompanying first audio data clock and a second digital audio interface for receiving the second digital audio data stream and an accompanying second audio data clock, wherein either the first audio data clock or the second audio data clock can be selectively provided to the clock generator as the first input clock signal.

3. The integrated circuit of claim 2, comprising a multiplexer connected to receive the first audio data clock and the second audio data clock, wherein an output of the multiplexer is connected to the clock generator to provide the first input clock signal.

4. The integrated circuit of claim 2, wherein the first digital audio interface and the second digital audio interface are connected to the application processor and the communication processor.

5. The integrated circuit of claim 2, further comprising a third digital audio interface for receiving a third digital audio data stream.

6. The integrated circuit of claim 1, wherein the received digital audio data and accompanying audio data clock are received from a USB source.

7. The integrated circuit of claim 1, further comprising storage circuitry to store the received digital audio data and to pass the received digital audio data to a digital-to-analog converter.

8. The integrated circuit of claim 1, further comprising an output terminal that provides the reconstructed analog audio data as an output of the integrated circuit.

9. The integrated circuit of claim 1, wherein the clock generator further comprises:

10. The integrated circuit of claim 1, wherein the integrated circuit comprises an audio and/or video codec.

11. An apparatus comprising an integrated circuit, wherein the integrated circuit comprises:

a clock generator for generating a continuous output clock signal, said clock generator comprising: a first clock signal input for receiving a first input clock signal; and a second clock signal input for receiving a second input clock signal;

wherein the received digital audio data and an accompanying audio data clock are received by the device in burst mode, and the digital-to-analog converter is continuously supplied with an output clock signal of the clock generator, and the output clock signal of the clock generator is based on a first input clock signal and a second input clock signal.

12. The apparatus of claim 11, further comprising a crystal oscillator connected to a second clock signal input of the clock generator.

13. The apparatus of claim 11, further comprising a speaker connected to an output terminal of the integrated circuit.

14. The apparatus of claim 11, wherein the integrated circuit includes a first digital audio interface for receiving a first digital audio data stream and an accompanying first audio data clock and a second digital audio interface for receiving a second digital audio data stream and an accompanying second audio data clock, wherein either the first audio data clock or the second audio data clock is selectively provided to the clock generator as the first input clock signal.

15. The device of claim 14, comprising an application processor and a communication processor connected to the first digital audio interface and the second digital audio interface.

16. The apparatus of claim 15, further comprising RF front-end circuitry connected to the communication processor.

17. The apparatus of claim 14 wherein said integrated circuit includes a third digital audio interface for receiving a third digital audio data stream.

18. The apparatus of claim 17, further comprising a bluetooth transceiver, FM radio, Wi-Fi transceiver, high resolution multimedia interface, S/PDIF interface, or USB interface connected to a third digital audio interface of the integrated circuit.

19. The device of claim 11, wherein the device is a smartphone, a gaming console, a tablet, a laptop computer, a desktop computer, or a hi-fi system.