GB2451474A

GB2451474A - Word length reduction circuit

Info

Publication number: GB2451474A
Application number: GB0714889A
Authority: GB
Inventors: John Paul Lesso
Original assignee: Wolfson Microelectronics PLC
Current assignee: Cirrus Logic International UK Ltd
Priority date: 2007-07-31
Filing date: 2007-07-31
Publication date: 2009-02-04
Anticipated expiration: 2027-07-31
Also published as: GB0714889D0; GB2451474B; WO2009016337A1

Abstract

A word length reduction circuit comprises an input, a word length reduction block 103, a signal processing block 111 and an adder 102. The word length reduction block 103 generates an output signal and an error signal from a modified input signal, the output signal having a smaller number of bits than the modified input signal. The signal processing block 111 comprises an unstable feedback loop and receives the error signal to generate a random dither signal. The adder 102 generates the modified input signal from the input and the random dither signal. The circuit may be used in audio and video devices.

Description

This invention relates generally to word length reduction and particularly, but not exclusively, to dither generation

BACKGROUND

In digital systems, word length reduction is the process by which a signal with a high number of bits is reduced to a representative signal with a lower number of bits.

There are many different methods for achieving this reduction. The most simple method is known as truncation, whereby one or more of the least significant bits (LSB5) of the signal are simply discarded. This method is crude, however, as the average value of the output words will in general not equal the input words.

Figure 1 is a graph showing the average value of the output word versus the input word. The continuous line represents the output of the truncation method. Thus the truncation results in poor-resolution "step" profile, where a large number of different input words are all approximated by the same output word.

Truncation may be improved by adding dither to the signal prior to truncating. Dither is a white noise signal that is intentionally added to the signal to make the average output more accurate. For example, consider an input word that is equal to 4.8. The truncation block only recognizes integers, and so ordinarily will discard 0.8 and output 4. However, if a random dither signal in the range of -0.5 to +0.5 were added to the input word before truncation, sometimes the input to the truncation block would be above 5. On average, the output word is a lot closer to 4. 8 with dither than without.

An alternative method of word length reduction is sigma-delta modulation. Sigma-delta modulators (SDMs) operate according to the principle shown in Figure 2. In the example shown, a 20-bit input is fed to an integrator 10 (i.e. "sigma"), and the output from the integrator 10 fed to a 1-bit quantizer 20. The quantizer output is output from the system, but also fed back and subtracted from the input signal in a subtracting element 30 (i.e. "delta"). This difference is fed to the integrator 10, and the loop continues in this way, summing the differences, outputting the quantized sum, and subtracting the output from the input. Thus, the output from the SDM is a stream of is a p and Os (in the one-bit output case) which averages accurately to the 20-bit input signal.

The input/output profile of a SDM is shown as a dashed line in Figure 1.

A similar technique to sigma-delta modulation is noise shaping. Figure 3a shows a schematic diagram of a noise shaper 40. In the example shown, a 20-bit input signal is quantized to a 1-bit output signal by a quantizer 42. The quantization error, i.e. the value of the bits that have been discarded as a result of the quantization, is determined by subtracting the output signal from the input signal in a subtracting element 44. The quantization error is fed back through a delay 46 to an adding element 48, where it is added to the next sample of the input signal.

Figure 3b shows an alternative realization of a noise shaper 50, using a split 52. In the 1-bit example shown, the split 52 takes the MSB and outputs it. The remaining LSBs are fed back through a delay 54 to an adding element 56 which adds the LSBs to the input signal. Thus the noise shaper 50 in Figure 3b is exactly equivalent to the noise shaper 40 in Figure 3a.

The problem with noise shapers is that they are prone to misbehaving. For example, if a constant signal is input to a 6-bit noise shaper, the system will "limit cycle" at least every 26 bits. This cyclic behaviour creates a tone at the frequency of F,)26, where F is the frequency of the input signal. Generally speaking, where there are 2N digital states then the system will repeat at a rate determined by N. Such tones are undesirable as they may cause unwanted effects in other components of the system.

In audio applications, the tones may even be audible to an end user.

To overcome this tone misbehaviour, dither is added to the input signal to slightly randomize the output and eradicate the tone. Thus, in almost every word length reduction technique, dither is used to improve the output of the system by removing unwanted cycles or by improving its accuracy.

Previously, dither was added using a linear feedback shift register (LFSR), as will be known to those skilled in the art. However, LFSRs do not eradicate the problem of limit cycling; rather they increase the period over which the cycles occur. For example, a 12-bit LFSR dither added to the 6-bit signal mentioned above will increase the limit cycle to every 218 bits, but the cycle will still be present, albeit at lower frequencies. In practical audio applications, in order to lower the limit cycle frequency such that it is inaudible to the human ear, a 12-bit LFSR at least is required. Such LFSRs consume a relatively large amount of power and occupy an increased space on the die.

SUMMARY OF INVENTION

According to a first embodiment of the present invention there is provided a word length reduction circuit. The word length reduction circuit comprises an input, for receiving an input signal; a word length reduction block, for receiving a modified input signal having a first number of bits, for generating a first output signal having a second number of bits, the second number of bits being smaller than the first number of bits, and for generating an error signal; a signal processing block, for receiving the error signal as a respective input signal and for generating a second output signal, the signal processing block comprising an unstable feedback loop such that the second output signal is randomized; and a first adder, connected to receive the second output signal and the input signal, in order to generate the modified input signal.

According to a second embodiment of the present invention there is provided a method for reducing the word length of an input signal. The method comprises the steps of receiving an input signal; generating a modified input signal with a first number of bits; generating an output signal and an error signal from the modified input signal, the output signal having a second number of bits, wherein the second number of bits is smaller than the first number of bits; and inputting the error signal to a signal processing block having an unstable feedback loop, the signal processing block generating a random dither signal. The random dither signal is added to the input signal to generate the modified input signal.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example, to the following drawings, in which: Figure 1 is a graph showing average word output versus word input for different word reduction techniques; Figure 2 is a schematic diagram of a sigma-delta modulator; Figure 3a is a schematic diagram of a noise shaper; Figure 3b is a schematic diagram of an alternative realization of a noise shaper; Figure 4 is a schematic diagram of a noise shaper with chaotic dither; Figure 5 is a schematic diagram of an exemplary high pass filter; Figure 6 is a schematic diagram of a second-order word length reduction circuit with chaotic dither; and Figure 7 is a schematic diagram of a frequency-locked loop where the word length reduction circuit may be applied.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In descriptions of a noise shaper hereinafter, the delay element is shown in the forward branch rather than the return branch. This is because it may be advantageous in certain circumstances to delay the output signal so as, for example, to allow re-synchronization after an addition. Therefore, rather than provide two delay elements, one in each branch after the split, it is more efficient to provide a single delay element in the forward branch prior to the split so that both signals are delayed by the same delay element. However, it will be apparent that these two possibilities are equivalent Figure 4 is schematic block diagram of a word length reduction circuit 100 according to a first embodiment of the invention.

In the word length reduction circuit 100, dither is added to an input signal to generate a modified input signal. The modified input signal is then input 10 a first-order noise shaper 103 largely as described in Figure 3b. The first-order noise shaper 103 generates a quantized output signal and a quantization error signal. Advantageously, the quantization error signal of the first-order noise shaper 103 is used to create the dither signal (Dither) that is added to the input signal (In). This is achieved by inputting the quantization error signal to a second noise shaper 111 that has an unstable feedback loop. The unstable feedback loop has the effect of randomizing the output signal of the second noise shaper 111. The randomized output signal of the second noise shaper 111 can then be used to dither the input signal.

Dither is added to the input signal in an adding element 102, to generate an N-bit modified input signal. The modified input signal is added to a fed back signal in a further adding element 104. The output of the adding element 104 is fed through a delay element 106, before being separated into Q MSBs and (N -0) LSBs at a split 108. The Q MSBs are output from the word length reduction circuit 100 as the quantized (i.e. reduced word length) output signal. The (N -Q) LSBs are fed back and added to the modified input signal in the adding element 104. Hereinafter, the (N -Q) LSBs are referred to as the "quantization error".

As aforementioned, the output of the second noise shaper 111 is essentially random, i.e its output is largely independent from its input. However, as the input to the second noise shaper 111 is generated from the input signal, there may under certain processing circumstances be some dependence on the input signal. This could lead to unwanted interference in the output signal.

in order to minimize this effect, optionally the quantization error signal or the dither or any signal in between may be scrambled in a scrambler 110. Figure 4 shows three possible arrangements for the scrambler 110: scrambling the quantization error signal output from the first-order noise shaper 103; scrambling the output of the second-order noise shaper 111; and scrambling the dither signal just before it is added to the input signal in the adder 102. However, further positions for the scrambler 110 may be thought of by one skilled in the art without departing from the scope of the invention.

The purpose of this step is to introduce a random signal such as noise, white noise for example, such that the dither signal has even less dependence on the input signal.

The technique of introducing noise into a signal is also known as "spectral conditioning'. Alternative methods of scrambling include introducing one or more non-linear filters or providing crossover switches that reverse the bit significance. Further, one or more of these scramblers may be used in combination.

Thus an M-bit signal is input to the second noise shaper 111. If there is no noise-whitening stage, M = (N -0) and the signal is the quantization error of the first noise shaper 103. The M-bit signal is added to a fed-back signal in an adding element 112.

The combined signal is fed through a delay element 1 14, and to a split 116. At the split 116 the signal is separated into D MSBs and (M -0) LSBs. The LSBs are fed back through a feedback path to the adding element 112. The feedback path contains a signal processing element 118 whose function is to make the feedback path containing it part of an unstable loop. The signal processing element 118 may be made unstable, for example, by means of a gain element, or by a delay element, or by any other non-linear element, or by a combination of these elements. The signal processing element 118 may add a number of bits a to the signal, where a = log2(Gain), for the example where the signal processing element 118 comprises a gain element.

The 0 MSBs are used as the dither signal added to the input signal in the adding element 102. Optionally, the D MSBs may be high-pass filtered to remove any systematic offset in the dither For example, in the 1-bit case (i.e., D =1), as the output will be a random stream of is and Os, the average output of the second noise shaper lii is 1/2. Were this signal added directly as the dither signal to the input, the average output of the circuit 100 would be increased by'A also. A high-pass filter 120 can be simply designed by one skilled in the art to remove this offset. However, in systems that are DC signal tolerant, the high-pass filter 120 may be dispensed with.

An example of a high-pass filter 120 for use in the word length reduction circuit 100 is shown schematically in Figure 5. The input signal is fed to a subtracting element 122 where it is added to an inverted fed-back signal. The combined signal is then delayed in a delay element 124 and fed back to the subtracting element 122. Thus, the possible outputs of the high-pass filter 120 are increased to -1, 0 and +1, and the average output reduced to 0.

There are many alternative embodiments of the word length reduction circuit 100 that one skilled in the art may think of without departing from the scope of the invention.

For example, the optional nature of the scrambler 110 and the high-pass filter 120 has already been discussed.

The first noise shaper 103 may be replaced with an alternative word reduction circuit or block, such as a truncation, or a sigma-delta modulator Such circuits by definition generate a quantized output and an associated quantization error, and therefore the second noise shaper 111 can still be used in the same manner to create the dither signal. ( a

Further, the circuit 100 as described with reference to Figure 4 uses the most significant bits of the second noise shaper 111 to generate the dither signal. However, as the unstable feedback loop combines with the input signal to generate a random combined signal, the entire signal in the forward branch of the noise shaper 111 is random. Therefore, any of the bits in the combined signal may be used to generate the dither signal. Further, the split 116 may not separate the signal into most-and least-significant bits, but rather may feed the whole signal back through the unstable feedback loop; further, the whole signal may be used to generate the dither signal, and thus in this instance the second noise shaper 111 does not act as a word length reduction block at all.

Figure 6 shows a second-order noise shaper 200.

The second-order noise shaper 200 comprises two first order noise shapers 210, 220, an error recombination block 230 to recombine the output signals of the two first-order noise shapers 210, 220, and a further noise shaper 240 with an unstable feedback loop to create the dither signal.

The first noise shaper 210 operates as described earlier with respect to Figure 3b, and will not be described in further detail. A modified (i.e. dithered) input signal is quantized and the quantized output and quantization error are output from the noise shaper 210.

Thus, the signal at the point labelled A in Figure 6 is the core signal minus the quantization error.

The quantization error is output from the first noise shaper 210 to the second noise shaper 220. The quantization error is added to a fed-back signal in an adding element 222. The combined signal is fed through a delay element 224 to a split 226 which separates the signal into one or more MSBs and the remaining LSBs. The MSBs are output from the second noise shaper 220, and the LSBs fed back to the adding element 222. Therefore, the signal at the point labelled B in Figure 8 is the quantized first-order quantization error: the first-order error minus a second- order error.

The second-order error may then be used as the input to the noise shaper 240, with a structure similar to the noise shaper 111, that has unstable feedback in order to generate the dither signal as described previously with respect to Figure 4. I h

The outputs of the two first-order noise shapers 210, 220 are combined in the error recombination block 230 in order to output a signal with reduced quantization error.

The output of the first noise shaper 210 is first delayed by a delay element 231. The delayed output of the first noise shaper 210 is then added to the output of the second noise shaper 220 in an adding element 232. This combined output is then fed to a further delay element 233.

The output of the second noise shaper 220 is then delayed by two delay elements 234, 235 The delayed output of the second noise shaper 220 is then added to the delayed combined output of the delay element 233 in a further adding element 236. The output of the adding element 236 is the core signal plus the second-order quantization error; the first-order quantization error has been corrected for.

Throughout all of the above description, delay elements are considered to have the same delay effect on a signal. However, a person skilled in the art would fully appreciate that the periods of delay could be varied from delay element to delay element, as long as the signals were synchronized correctly.

Figure 7 is a schematic diagram of a frequency-locked loop 300 where the word length reduction circuit according to the present invention may be applied.

A digital signal having a frequency F, is input to a frequency detector 332. The frequency detector 332 detects the frequency of the input signal, compares it with the frequency of a fed-back signal, and outputs a signal that is indicative of the difference in the two frequencies. This signal is input to a loop filter 334, which has an integrating function. In other embodiments, alternative components to the loop filter 334 may be used. The only requirement is that the component has an integrating function. The loop filter 334 outputs an integrated signal with a high number of bits. This signal is input to a word-length reduction (WLR) circuit 336. The WLR circuit 336 outputs a signal to a digital-to-analogue converter (DAC) 338, which converts it to analogue. The analogue signal is then used to control a VCO 340, and this outputs a signal at a frequency The signal output from the VCO 340 is sampled, and its frequency F0 fed to a �N block 342. The frequency F0 is divided by a factor N, which is chosen by the designer of the system, and this divided frequency fed back to the frequency detector 332. In this way the system converges to an output signal with a frequency of F01 = N x F1.

The WLR block 336 operates to reduce the word length of the signal output from the loop filter 334, in order to reduce the complexity of the DAC. For example, the signal input to the WLR block 336 may be 20 bits. The WLR block 336 may then operate to reduce this to a lower number of bits, say 5. A 5-bit DAC is much easier to design than a 20-bit DAC, and therefore the word-length reduction results in a large saving in terms of the complexity of the system.

In the FLL 300, the output from the WLR block 336 is averaged by the low-pass filter effect of the DAC 338 so as to avoid, or at least mitigate, the modulation of the frequency of the output signal Furthermore, an optional extra low pass filter may be added after the DAC 338 to increase this averaging behaviour and stabilize the loop. For example, a capacitor 344 may be added as shown in Figure 7 or alternatively an RC network. The capacitor 344 is connected at one terminal between the DAC 338 and the VCO 340, and at the other terminal to ground. In this way, the average value of the WLR output is taken rather than the instantaneous value.

The foregoing description is based on frequency-locked loops (FLLs). However, the present invention is equally applicable to phase-locked loops (PLLs). A person skilled in the art will readily understand how the embodiments described above may be adapted to PLLs: for example, the blocks described as "frequency detectors" may be easily replaced with "phase detectors" Further minor modifications may be necessary, but the invention as described applies equally to FLLs and PLLs, and as such the invention is not to be considered as limited to the specific examples described.

The word length reduction circuits described herein are preferably included in frequency-locked loops or phase-locked loops that are preferably incorporated in an integrated circuit. For example, the integrated circuit may be part of an audio and/or video system, such as an MP3 player, a mobile phone, a camera or a satellite navigation system, and the system can be portable (such as a battery-powered handheld system) or can be mains-powered (such as a hi-fl system or a television receiver) or can be an in-car, in-train, or in-plane entertainment system.

The skilled person will recognise that the above-described apparatus and methods may be embodied as processor control code, for example on a carrier medium such as a disk, CD-or DVD-ROM, programmed memory such as read only memory (firmware), or on a data carrier such as an optical or electrical signal carrier. For many applications, embodiments of the invention will be implemented on a DSP (digital signal processor), ASIC (application specific integrated circuit) or FPGA (field programmable gate array). Thus the code may comprise conventional program code or microcode or, for example code for setting up or controlling an ASIC or FPGA. The code may also comprise code for dynamically configuring re-configurable apparatus such as re-programmable logic gate arrays. Similarly the code may comprise code for a hardware description language such as Verilog TM or VHDL (very high speed integrated circuit hardware description language). As the skilled person will appreciate, the code may be distributed between a plurality of coupled components in communication with one another. Where appropriate, the embodiments may also be implemented using code running on a field-(re-)programmable analogue array or similar device in order to configure analogue/digital hardware.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising' does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

1. A word length reduction circuit, comprising: an input, for receiving an input signal, a word length reduction block, for receiving a modified input signal having a first number of bits, for generating a first output signal having a second number of bits, the second number of bits being smaller than the first number of bits, and for generating an erTor signal; a signal processing block, for receiving the error signal as a respective input signal and for generating a second output signal, the signal processing block comprising an unstable feedback loop such that the second output signal is randomized; and a first adder, connected to receive the second output signal and the input signal, in order to generate the modified input signal.

2. A word length reduction circuit as claimed in claim 1, wherein the unstable feedback loop comprises one or more non-linear signal processing elements.

3. A word length reduction circuit as claimed in claim 2, wherein the one or more non-linear signal processing elements comprises a gain element.

4. A word length reduction circuit as claimed in claim 2 or 3, wherein the one or more non-linear signal processing elements comprises a delay element.

5 A word length reduction circuit as claimed in any one of the preceding claims, the word length reduction block comprising: a forward signal path for receiving the modified input signal and outputting the first output signal; and a feedback signal path for feeding back the error signal and outputting the error signal; the forward signal path comprising: a second adder for adding the error signal to the modified input signal, for generating a summed signal; a delay element for delaying the summed signal; and a split for receiving the delayed summed signal, outputting one or more most significant bits of the delayed summed signal as the first output signal, and outputting one or more least significant bits of the delayed summed signal to the feedback signal path, as the error signal.

6. A word length reduction circuit as claimed in any one claims 1 to 3, wherein the word length reduction block comprises: a first word length reduction sub-block for receiving the modified input signal, for generating a first intermediate output signal, and for generating an intermediate error signal, a second word length reduction sub-block for receiving the intermediate error signal, for generating a second intermediate output signal, and for generating the error signal of the word length reduction block; and an error correction block for receiving the first intermediate output signal and the second intermediate output signal, and generating the first output signal.

7. A word length reduction circuit as claimed in claim 6, wherein the error correction block comprises: a first delay element for delaying the first intermediate output by a first amount; a third adder for adding the delayed first intermediate output to the second intermediate output, thereby generating a combined intermediate output; a second delay element for delaying the combined intermediate output by a second amount; a third delay element for delaying the second intermediate output by a third amount; a fourth delay element for receiving and delaying the output of the third delay element by a fourth amount; and a fourth adder for adding the delayed combined intermediate output and the output of the fourth delay element, to generate the first output signal.

8. A word length reduction circuit as claimed in claim 7, wherein the first amount, the second amount, the third amount and the fourth amount are the same.

9. A word length reduction circuit as claimed in any one of the preceding claims, further comprising: a scrambler for scrambling the error signal.

10. A word length reduction circuit as claimed in claim 9, wherein the scrambler comprises a spectral conditioner.

11 A word length reduction circuit as claimed in claim 1, wherein the word length reduction block is a truncation.

12 A word length reduction circuit as claimed in claim 1, wherein the word length reduction block is a sigma-delta modulator

13. A word length reduction circuit as claimed in any one of the preceding claims, further comprising: a high-pass filter for receiving the second output signal and outputting a filtered second output signal to the first adder.

14. A circuit for receiving an input signal having a first frequency, and outputting a signal having a second frequency, said circuit comprising: a word length reduction circuit as claimed in any one of claims ito 13.

An integrated circuit, comprising a word length reduction circuit as claimed in any of claims ito 13.

16. An audio system, comprising an integrated circuit as claimed in claim 15.

17. An audio system as claimed in claim 16, wherein the audio system is a portable device.

18. An audio system as claimed in claim 16, wherein the audio system is a mains-powered device.

19. An audio system as claimed in claim 16, wherein the audio system is an in-car, in-train, or in-plane entertainment system.

20. A video system, comprising an integrated circuit as claimed in claim 15.

21. A video system as claimed in claim 20, wherein the video system is a portable device.

22. A video system as claimed in claim 20, wherein the video system is a mains-powered device.

23. A video system as claimed in claim 20, wherein the video system is an in-car, in-train, or in-plane entertainment system.

24. A method for reducing the word length of an input signal, the method comprising.

receiving an input signal; generating a modified input signal with a first number of bits; generating an output signal and an error signal from the modified input signal, the output signal having a second number of bits, wherein the second number of bits is smaller than the first number of bits; and inputting the error signal to a signal processing block having an unstable feedback loop, the signal processing block generating a random dither signal; wherein the random dither signal is added to the input signal to generate the modified input signal.

25. A method as claimed in claim 24, wherein the random dither signal is generated by means of one or more non-linear signal processing elements in the unstable feedback loop.

26. A method as claimed in claim 25, wherein the random dither signal is generated by means of a gain element in the one or more non-linear signal processing elements.

27 A method as claimed in claim 25 or 26, wherein the random dither signal is generated by means of a delay element in the one or more non-linear signal processing elements.

28. A method as claimed in any one of claims 24 to 27, wherein the step of generating the output signal and the error signal comprises: adding the modified input signal and the error signal and generating a summed signal; delaying the summed signal; outputting one or more most significant bits of the delayed summed signal as the output signal; and outputting one or more least significant bits of the delayed summed signal as the error signal.

29. A method as claimed in any one of claims 24 to 27, wherein the step of generating the output signal and the error signal comprises: generating a first intermediate output signal and an intermediate error signal; receiving the intermediate error signal and generating a second intermediate output signal and the error signal; and combining the first intermediate output signal and the second intermediate output signal to generate the output signal.

30. A method as claimed in any one of claims 24 to 29, further comprising: high-pass filtering the random dither signal

31. A method as claimed in any one of claims 24 to 30, further comprising: scrambling the error signal.

32. A method as claimed in any one of claims 24 to 31, further comprising: scrambling the random dither signal.

33. A method as claimed in claim 24, wherein the step of generating the output signal and the error signal comprises truncating the modified input signal.