CN107346780B - Microelectronic structure and method of forming the same - Google Patents

Microelectronic structure and method of forming the same Download PDF

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Publication number
CN107346780B
CN107346780B CN201610293052.1A CN201610293052A CN107346780B CN 107346780 B CN107346780 B CN 107346780B CN 201610293052 A CN201610293052 A CN 201610293052A CN 107346780 B CN107346780 B CN 107346780B
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electrode
graphene layer
layer
microelectronic
insulating layer
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CN107346780A (en
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肖德元
张汝京
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Zing Semiconductor Corp
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Zing Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66045—Field-effect transistors

Abstract

The invention discloses a microelectronic structure and a forming method thereof. The method for forming the microelectronic structure comprises the steps of forming a plurality of doped regions on a substrate, and selectively forming a graphene layer on the doped regions. The graphene layer comprises at least one layer of graphene structure and has an energy gap larger than 300 meV. The microelectronic structure obtained by the method can improve the electronic characteristics of the microelectronic structure by applying the graphene material with high energy gap.

Description

Microelectronic structure and method of forming the same
Technical Field
The present invention relates to the field of microelectronic fabrication, and more particularly, to a microelectronic structure and a method of forming the same.
Background
At present, the application of graphene is increasingly emphasized in the field of microelectronic manufacturing, so that graphene with low resistivity and a light and thin structure is expected to be applied to the graphene, which is helpful for improving the electronic moving speed and the miniaturization of the size of a microelectronic component. In the prior art, the development of applying graphene to manufacture microelectronic components is very rapid, and several models have been proposed. Referring to the schematic structure shown in fig. 1, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)1 uses a graphene layer 140 formed on a silicon substrate 120 as a channel layer connected between a source 160 and a drain 150, and a silicon dioxide layer 130 as an insulating layer, and the back gate 110 controls the flow of electrons in the channel layer. Although such a mosfet can be manufactured by the conventional manufacturing process, it has an excessive parasitic capacitance, and cannot be integrated with other devices, so that it cannot meet the requirement of industrial manufacturing.
Referring to fig. 2 and fig. 3, the metal oxide semiconductor field effect transistor 2 in fig. 2 is formed by doping the back surface of a silicon substrate 220 covered with silicon dioxide 230 to form a back gate 210, and the front surface thereof is fabricated by chemical lift-off (chemical lift-off) or by fabricating a graphene layer 240 on a metal such as nickel or copper, and the metal oxide semiconductor field effect transistor 3 in fig. 3 is formed by forming a graphene layer 330 on a silicon carbide substrate 310 by epitaxial growth (epitaxial growth) and oxidizing to form a silicon dioxide layer 320. Next, an upper gate insulating layer and upper gates 270 and 360 are formed, and whether a channel is conducted between the sources 260 and 350 and the drains 250 and 340 is controlled by the upper gates 270 and 360. However, the energy gap of the graphene layers 240 and 330 in the top gate type mosfets 2 and 3 is insufficient, so that the channels cannot be cut off after being turned on, and the important function of the mosfets is lost.
Therefore, there is a need to develop a microelectronic structure using graphene that exhibits good device functions and meets the requirements of industrial fabrication.
Disclosure of Invention
The invention aims to provide a novel microelectronic structure and a forming method thereof, which apply the excellent superconducting property of graphene to the microelectronic structure and improve the electronic characteristics of a microelectronic component.
In accordance with one aspect of the present invention, there is provided a microelectronic structure comprising: a substrate on which a plurality of microelectronic elements are formed, wherein the microelectronic elements respectively include a graphene layer, a first electrode, a second electrode and a third electrode, wherein the first electrode and the second electrode directly contact two ends of the graphene layer, the graphene layer and the substrate are separated by a first insulating layer, the third electrode and the graphene layer are separated by a second insulating layer, the graphene layer has an energy gap larger than 300meV, and the second insulating layer includes a plurality of isolation layers defining the range of the microelectronic elements.
According to another aspect of the present invention, there is provided a method of forming a microelectronic structure, comprising: forming a plurality of doped regions on a substrate; selectively forming a graphene layer on the doped regions, wherein the graphene layer comprises at least one graphene layer structure and has an energy gap larger than 300 meV; oxidizing to form a first insulating layer, and enabling the graphene layer to be spaced from the substrate by the first insulating layer; forming a second insulating layer on the graphene layer, wherein the second insulating layer comprises a plurality of isolation layers defining a range of a plurality of microelectronic components; and a first electrode, a second electrode and a third electrode are respectively formed in the microelectronic assemblies on the second insulating layer, so that the first electrode and the second electrode are directly contacted with two ends of the graphene layer, and the third electrode and the graphene layer are separated by the second insulating layer.
The invention may be varied selectively, here exemplified but not limited to: the substrate may alternatively be any substrate, such as a silicon substrate; the graphene layer may optionally include any number of layers of graphene, one layer being exemplified herein; the first insulating layer and the second insulating layer are selectively formed by using an oxide of a substrate material or a high dielectric film, and preferably, the first insulating layer is formed by oxidizing the substrate by passing oxygen through the graphene layer, and the second insulating layer is a high dielectric film; the first electrode, the second electrode and the third electrode can be metal electrodes selectively. For example, if the microelectronic device formed is a double-gate field effect transistor, the first, second, and third electrodes may be a source, a drain, and a first gate, respectively, and the substrate may be a second gate.
Next, in the method for forming a microelectronic structure provided by the present invention, the step of forming a plurality of doped regions on a substrate may additionally include the steps of doping a dopant into the doped regions on the substrate by an ion implantation technique and a Rapid Thermal annealing (Rapid Thermal annealing) process. For example, the dopant may be nickel ions, and the rapid thermal annealing may be performed at a temperature of 400 to 1200 ℃ for 1 to 1000 seconds, which is not limited herein. Second, the dopant in the doped regions preferably acts as a catalyst to assist in the selective formation of a graphene layer on the doped regions.
Compared with the prior art, the invention provides a brand-new microelectronic structure and a forming method thereof, the graphene material is applied in the microelectronic structure, and the energy gap of the graphene material is improved, so that the electronic characteristic of the microelectronic structure is greatly improved, and a plurality of doped regions are formed in advance before the graphene layer is formed in the manufacturing process, so that the graphene layer with the consistent size and shape is manufactured, and the requirement of mass production of the microelectronic structure is met.
Drawings
FIGS. 1-3 are schematic structural views of a prior art microelectronic structure;
FIG. 4 is a schematic structural diagram of a microelectronic structure in accordance with one embodiment of the invention;
FIGS. 5-9 are schematic structural views of a microelectronic structure during formation thereof, in accordance with one embodiment of the present invention;
fig. 10 is a flow chart of a method of forming a microelectronic structure according to one embodiment of the invention.
Detailed Description
The microelectronic structures and methods of forming the same of the present invention will now be described in greater detail with reference to the schematic drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the beneficial results of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention provides a microelectronic structure and a forming method thereof. The method comprises the following steps: forming a plurality of doped regions on a substrate; selectively forming a graphene layer on the doped regions, wherein the graphene layer comprises at least one graphene layer structure and has an energy gap larger than 300 meV; oxidizing to form a first insulating layer, and enabling the graphene layer to be spaced from the substrate by the first insulating layer; forming a second insulating layer on the graphene layer, wherein the second insulating layer comprises a plurality of isolation layers defining a range of a plurality of microelectronic components; and a first electrode, a second electrode and a third electrode are respectively formed in the microelectronic assemblies on the second insulating layer, so that the first electrode and the second electrode are directly contacted with two ends of the graphene layer, and the third electrode and the graphene layer are separated by the second insulating layer. Therefore, the graphene material is applied to the microelectronic structure, and the electronic characteristics of the microelectronic component are improved.
Referring now to fig. 4, a microelectronic structure and method of forming the same according to the present invention will be described in detail, wherein the microelectronic device is illustrated as a dual gate field effect transistor, although the invention is not limited to the specific structure illustrated in fig. 4. FIG. 10 is a flow chart of a method of forming a microelectronic structure of the present invention; fig. 5-9 are schematic structural views of a microelectronic structure of the present invention during formation.
Referring to fig. 4 in conjunction with fig. 10, a method of forming a microelectronic structure 4 includes:
first, as shown in fig. 5, step S100 is performed to form a plurality of doped regions 411 and 412 on a substrate 410. In this embodiment, for example, a silicon substrate is selectively used, the substrate 410 is properly cleaned, a layer of photoresist is uniformly coated, the photoresist is patterned by exposure, development and etching, and the doped regions 411 and 412 are formed by ion implantation. In detail, the ion implantation is performed by using nickel ions as the dopant and implanting the dopant into the doped regions 411, 412 at a concentration of 1-100 keV and 1E 15-1E 18 ions/cm, but the invention is not limited to the parameters and materials herein, and other parameters may be designed or other materials, such as copper, silver, gold, etc., may be selected according to the actual requirements. For the present example, after the nickel ions are implanted into the doped regions 411, 412, a Rapid thermal annealing (Rapid thermal annealing) process is performed. The rapid thermal annealing treatment is performed at a temperature of 400 to 1200 ℃ for 1 to 1000 seconds, for example, without limitation. After the rapid thermal annealing process, the silicon atoms of the doped regions 411, 412 are bonded to the nickel atoms, and the nickel-silicon compound preferably continues the lattice orientation of the silicon material of the substrate 410.
Next, in step S200, as shown in fig. 6, a graphene layer 430 is selectively formed on the doped regions 411 and 412, wherein the graphene layer 430 includes at least one graphene layer and has an energy gap greater than 300 meV. The graphene layer 430 formed herein may be a large-area extended graphene structure or a graphene structure composed of a plurality of nano-ribbons (nano-ribbons), and may include one or more graphene layers, and a film layer of other materials may be additionally included between the graphene layer 430 and the substrate 410 as required. Since the dopants in the doped regions 411 and 412 can serve as a reaction catalyst for forming the graphene layer 430, the selective formation of a graphene layer on the doped regions 411 and 412 can be facilitated, which helps to facilitate the aggregation of graphene nanoribbons and control the shape and boundary of the graphene layer 430 to be well-defined, thereby fabricating the graphene layer 430 with a desired size and shape.
After this step, next in step S300, as shown in fig. 7, a first insulating layer 420 is formed by oxidation, and the graphene layer 430 is spaced from the substrate 410 by the first insulating layer 420. The first insulating layer 420 is formed by oxidizing the substrate 410, illustratively by placing the structure shown in fig. 6 in an oxygen-containing environment, passing oxygen through the graphene layer 430. For the present example, oxygen oxidizes the silicon substrate 410 to silicon dioxide to form the first insulating layer 420.
Next, as shown in fig. 8, step S400 is performed to form a second insulating layer 460 on the graphene layer 430; specifically, the second insulating layer 460 can be any high dielectric film formed by any film forming technique, such as: hafnium oxide (HfO)2) Zirconium dioxide (ZrO)2) Alumina (Al)2O3) Titanium dioxide (TiO)2) And tantalum pentoxide (Ta)2O5) And hafnium oxide is preferred, and an example of hafnium oxide formed by Atomic Layer Deposition (ALD) is given here.
This combination of patterning steps including photoresist coating, exposure, development, etching, etc., defines a plurality of isolation layers 461 within the second insulating layer 460, such isolation layers 461 disposed between the microelectronic elements and the microelectronic elements A, B (shown in fig. 9) as insulating layers and defining the extent of each microelectronic element A, B.
Then, referring to fig. 9, step S500 is performed to form a first electrode 450, a second electrode 440, and a third electrode 470 in the microelectronic assemblies A, B on the second insulating layer 460, so that the first electrode 450 and the second electrode 440 directly contact two ends of the graphene layer 430, and the third electrode 470 is spaced apart from the graphene layer 430 by the second insulating layer 460. The manner of forming the first electrode 450, the second electrode 440, and the third electrode 470 can be varied, for example, a metal layer, such as aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, gold, silver, nickel, and alloys thereof, is formed by sputtering metal, atomic layer deposition, or other thin film forming methods, and the other regions except the region to be etched are covered by photoresist, and the metal layer is removed by wet etching to define the first electrode 450, the second electrode 440, and the third electrode 470, or by polishing. Since the microelectronic device A, B is a double-gate field effect transistor, the first electrode 450 serves as a source, the second electrode 440 serves as a drain, the third electrode 470 serves as a first gate, such as a top gate (top gate), and the substrate 410 serves as a second gate, such as a back gate (back gate). Thus, microelectronic structure 4 has top and back gates that cooperate to control the conduction of the channel therein, and the presence of the top gate can significantly reduce the parasitic capacitance, so that microelectronic assembly A, B can operate efficiently.
With continued reference to fig. 9, through the above steps, the present invention obtains a microelectronic structure 4, including: a substrate 410 on which a plurality of microelectronic devices A, B are formed, and a graphene layer 430, a first electrode 450, a second electrode 440, and a third electrode 470 are formed on the microelectronic devices A, B, respectively, wherein the first electrode 450 and the second electrode 440 directly contact two ends of the graphene layer 430, the graphene layer 430 is separated from the substrate 410 by a first insulating layer 420, the third electrode 470 is separated from the graphene layer 430 by a second insulating layer 460, the graphene layer 430 has an energy gap larger than 300meV, and the second insulating layer 460 includes a plurality of isolation layers 461 defining a range of the microelectronic devices A, B.
The microelectronic structure obtained by the process has the advantages that the energy gap of the graphene material is improved, so that the electronic characteristics of the microelectronic component are greatly improved, and the graphene layer with the consistent size and shape is manufactured by a proper doping process in the manufacturing process, so that the requirement of mass production of the microelectronic structure is met.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (10)

1. A microelectronic structure, comprising:
a substrate, on which a plurality of microelectronic components are formed, and the microelectronic components respectively include a graphene layer, a first electrode, a second electrode and a third electrode, wherein the first electrode and the second electrode are located on the graphene layer and directly contact two ends of the graphene layer, the graphene layer and the substrate are separated by a first insulating layer, the third electrode and the graphene layer are separated by a second insulating layer, the graphene layer has an energy gap larger than 300meV, and the second insulating layer includes a plurality of isolation layers defining the range of the microelectronic components.
2. The microelectronic structure of claim 1, wherein the graphene layer comprises at least one layer of graphene structure.
3. The microelectronic structure of claim 1, wherein said first electrode, said second electrode, and said third electrode are metal electrodes.
4. The microelectronic structure of claim 1, wherein said first insulating layer is an oxide of said substrate and said second insulating layer is a high dielectric film.
5. The microelectronic structure of claim 1, wherein said microelectronic structure is a double gate field effect transistor, said first, second and third electrodes are a source, a drain and a first gate, respectively, and said substrate is a second gate.
6. A method of forming a microelectronic structure, comprising:
forming a plurality of doped regions on a substrate;
selectively forming a graphene layer on the doped regions, wherein the graphene layer comprises at least one graphene layer structure and has an energy gap greater than 300meV, and the dopant in the doped regions can be used as a reaction catalyst for forming the graphene layer to assist in selectively forming a graphene layer on the doped regions;
oxidizing to form a first insulating layer, and enabling the graphene layer to be spaced from the substrate by the first insulating layer;
forming a second insulating layer on the graphene layer, wherein the second insulating layer comprises a plurality of isolation layers defining a plurality of microelectronic component ranges; and
and respectively forming a first electrode, a second electrode and a third electrode in the microelectronic assemblies on the second insulating layer, so that the first electrode and the second electrode are positioned on the graphene layer and directly contact with two ends of the graphene layer, and the third electrode and the graphene layer are separated by the second insulating layer.
7. The method of claim 6, wherein the step of forming a plurality of doped regions on a substrate further comprises:
doping a dopant in the doped regions on the substrate by ion implantation; and
a rapid thermal annealing treatment is performed.
8. The method of claim 7, wherein the dopant is nickel ions and the rapid thermal anneal is performed at a temperature of 400-1200 ℃ for 1-1000 seconds.
9. The method of claim 6, wherein the step of selectively forming a graphene layer over the doped regions is performed using the dopant in the doped regions as a catalyst.
10. The method of claim 6, wherein the first insulating layer is formed by oxidizing the substrate by passing oxygen through the graphene layer.
CN201610293052.1A 2016-05-05 2016-05-05 Microelectronic structure and method of forming the same Active CN107346780B (en)

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Citations (1)

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Publication number Priority date Publication date Assignee Title
CN103258850A (en) * 2012-02-15 2013-08-21 西安电子科技大学 Grapheme nano-ribbon field effect transistor and preparation method thereof

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US20110006837A1 (en) * 2009-06-02 2011-01-13 Feng Wang Graphene Device, Method of Investigating Graphene, and Method of Operating Graphene Device
EP2667417A1 (en) * 2012-05-23 2013-11-27 Imec Graphene-based semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103258850A (en) * 2012-02-15 2013-08-21 西安电子科技大学 Grapheme nano-ribbon field effect transistor and preparation method thereof

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