CN107331609A - Wafer control slice and its manufacture method - Google Patents
Wafer control slice and its manufacture method Download PDFInfo
- Publication number
- CN107331609A CN107331609A CN201610278144.2A CN201610278144A CN107331609A CN 107331609 A CN107331609 A CN 107331609A CN 201610278144 A CN201610278144 A CN 201610278144A CN 107331609 A CN107331609 A CN 107331609A
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- CN
- China
- Prior art keywords
- wafer
- manufacture method
- control slice
- polysilicon
- coating
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
Abstract
The invention provides a kind of wafer control slice and its manufacture method, the manufacture method includes step：One polysilicon handle wafer is provided；Silicon fiml coating is formed on the surface of the polysilicon handle wafer；By forming silicon fiml coating on the surface of polysilicon handle wafer, it ensure that the crushing resistance of wafer control slice, it will not be ruptured because of outside pressure, and use polysilicon handle wafer, not only save the cost of wafer control slice, and avoid introduce other the problem of and have influence on testing result, it is ensured that the accuracy of testing result.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of wafer control slice and its manufacture method.
Background technology
In the prior art, it is necessary to pass through multiple processing steps in crystal column surface when forming semiconductor devices.
If the adjustment control of one processing step of any of which is improper, then the semiconductor devices to be formed can be caused to occur
Quality problems, cause scrapping for wafer.Therefore, in actual production line, whenever processing step
Each parameter adjustment is completed, and wafer control slice (dummy wafer) can be tested using this processing step, is passed through
Detection and analysis verifies that can this processing step properly form semiconductor devices.For example, carrying out depositing operation
Before, to cause the film thickness and uniform degree of deposition to meet the requirement of semiconductor devices, or in depositing operation
Produced particle first can deposit the film whether in allowed band on wafer control slice, it is to be confirmed just
Just film formation is being actually subjected on the wafer for manufacturing semiconductor devices after really.
But, because wafer control slice uses monocrystalline silicon wafer crystal, its cost is high, and wafer control slice is continuous
Using that can increase the cost that semiconductor devices is manufactured, general use reuses wafer control slice in the prior art
Method comes cost-effective, for example：(HF or HNO is used by carrying out acidic chemical processing to wafer control slice3)、
Alkali electroless processing (uses NH4) and the reuse to wafer control slice is realized in surface grinding OH.But
It is that reuse can be such that the thickness of wafer control slice constantly reduces, and the number of times of reuse is limited.
Japan Patent (JP H8-316283) in Japan Patent (JP H9-139329) with having recorded a kind of use
Glass flake or vitreous carbon replace monocrystalline silicon wafer crystal as the method for wafer control slice.Japan Patent (JP
H5-160240) Al is used with describing one kind in Japan Patent (JP H8-17888)2O3Potsherd carrys out generation
For method of the monocrystalline silicon wafer crystal as wafer control slice.Japan Patent (JP H5-283306) provides a kind of use
SiC ceramic piece replaces the method that monocrystalline silicon wafer crystal completes CVD deposition.But wafer can not instead of piece
It is complete to be used instead of monocrystalline silicon wafer crystal as wafer control slice, for example：These wafers replace piece in thermal shock
During can be very fragile；Al2O3Potsherd or SiC ceramic sheet weight are too heavy, it can be influenceed to transmit.
Therefore, searching is a kind of had not only saved control wafer cost but also will not introduce other problemses and influence the crystalline substance of verification the verifying results
Circle control wafer is those skilled in the art's technical problem urgently to be resolved hurrily.
The content of the invention
It is an object of the invention to provide a kind of wafer control slice and its manufacture method, cost was not only saved but also had not influenceed
The Detection results of wafer control slice.
The technical scheme is that a kind of manufacture method of wafer control slice, comprises the following steps：
Step S01：One polysilicon handle wafer is provided；
Step S02：Silicon fiml coating is formed on the surface of the polysilicon handle wafer.
Further, in the manufacture method of the wafer control slice, the polysilicon handle wafer is by multiple polysilicons
Die combinations are formed.
Further, in the manufacture method of the wafer control slice, the polysilicon handle wafer includes more than 30%
<111>The polysilicon grain of crystal orientation.
Further, in the manufacture method of the wafer control slice, the size range of the polysilicon handle wafer is
1.5 inches~15 inches, the roughness that the polysilicon handle wafer is used for the one side for forming semiconductor devices is less than
0.5nm, the microwave of the polysilicon handle wafer is less than 10nm, and the edge grinding degree of the polysilicon handle wafer is less than
10nm。
Further, in the manufacture method of the wafer control slice, the method for forming the silicon fiml coating is：
By the solvent for including CPS or/and CHS in polysilicon handle wafer surface progress rotary coating, enter simultaneously
Row treatment with ultraviolet light；Coating proceeds ultraviolet light after completing；Finally it is heat-treated.
Further, in the manufacture method of the wafer control slice, also include before step S02：To institute
State polysilicon handle wafer and carry out first time cmp.
Further, in the manufacture method of the wafer control slice, in addition to step S03：To the silicon fiml
Coating carries out second of cmp.
Further, in the manufacture method of the wafer control slice, in addition to step S04：In the silicon fiml
The second silicon fiml coating is formed on coating.
Further, in the manufacture method of the wafer control slice, the grinding of the cmp twice
Liquid includes grinding agent and acid flux material.
Further, in the manufacture method of the wafer control slice, second of cmp is ground
The content of grinding agent is less than the content of the grinding agent of the first time cmp.
Further, in the manufacture method of the wafer control slice, the polysilicon handle wafer is used to be formed partly to lead
The thickness of the silicon fiml coating of the one side of body device is 10nm~3000nm.
The present invention also provides a kind of wafer control slice, is manufactured using the manufacture method of above-mentioned wafer control slice, described
Wafer control slice includes polysilicon handle wafer and the silicon fiml coating positioned at the polysilicon handle wafer surface.
Further, in the wafer control slice, the surface of the polysilicon handle wafer is formed with silicon described in two layers
Membrane coat.
Compared with prior art, the present invention is provided wafer control slice and its manufacture method, by polycrystalline silicon wafer
Round surface forms silicon fiml coating, it is ensured that the crushing resistance of wafer control slice, will not occur because of outside pressure
Rupture, and polysilicon handle wafer is used, the cost of wafer control slice is not only saved, and avoid introducing other
The problem of and have influence on testing result, it is ensured that the accuracy of testing result.
Brief description of the drawings
Fig. 1 is the flow chart of the manufacture method of wafer control slice in one embodiment of the invention.
Fig. 2~4 be one embodiment of the invention in wafer control slice manufacture method in different step structural representation.
Embodiment
A kind of manufacture method of wafer control slice is recorded in Japan Patent (JP 2009-38220), using polycrystalline
Silicon Wafer, comprises the following steps：First, cmp is carried out to the polysilicon handle wafer；Then,
In polysilicon handle wafer surface deposition silica (SiO2)；Then, chemistry is carried out to the silica
Mechanical lapping；Finally, silica is deposited again.Silicon dioxide layer is formed on the surface of polysilicon handle wafer to use
In replacing existing monocrystalline silicon wafer crystal control wafer, but the wafer control slice being consequently formed bears the effect ratio of pressure
It is poor, easily cause the rupture of wafer.
After further research, a kind of wafer control slice and its manufacture method are inventors herein proposed.
A kind of wafer control slice and its manufacture method provided below in conjunction with the drawings and specific embodiments the present invention enters
One step is described in detail.According to following explanation and claims, advantages and features of the invention will become apparent from.
It should be noted that, accompanying drawing is using very simplified form and uses non-accurately ratio, only to it is convenient,
Lucidly aid in illustrating the purpose of the embodiment of the present invention.
The present invention core concept be：By forming silicon fiml coating on the surface of polysilicon handle wafer, it is ensured that brilliant
The crushing resistance of circle control wafer, will not rupture because of outside pressure, and use polysilicon handle wafer, not only
Save the cost of wafer control slice, and avoid introduce other the problem of and have influence on testing result, it is ensured that
The accuracy of testing result.
Fig. 1 is the flow chart of the manufacture method of wafer control slice in one embodiment of the invention, as shown in figure 1, this
Invention proposes a kind of manufacture method of wafer control slice, comprises the following steps：
Step S01：One polysilicon handle wafer is provided；
Step S02：Silicon fiml coating is formed on the surface of the polysilicon handle wafer.
Fig. 2~4 are the structural representation of each step of manufacture method of wafer control slice in one embodiment of the invention, please
With reference to shown in Fig. 1, and Fig. 2~4 are combined, describe a kind of manufacture method for wafer control slice that the present invention is provided in detail：
In step S01, the polysilicon handle wafer 10 is combined by multiple polysilicon grains 11, please be joined
According to shown in Fig. 2, the size and crystal orientation of the multiple polysilicon grain 11 can be the same or different, described
The crystal orientation of multiple polysilicon grains 11 includes<100>、<110>And<111>.In the present embodiment, the polycrystalline
Silicon Wafer 10 includes more than 30%<111>The polysilicon grain 11 of crystal orientation.
The size range of the polysilicon handle wafer 10 be 1.5 inches~15 inches, such as 3 inches, 5 inches,
10 inches, 15 inches；The roughness that the polysilicon handle wafer 10 is used for the one side for forming semiconductor devices is small
In 0.5nm, such as 0.2nm, 0.3nm, 0.4nm；The microwave (micro waviness) of the polysilicon handle wafer 10
Less than 10nm, such as 2nm, 5nm, 8nm；The edge grinding degree (Roll off) of the polysilicon handle wafer 10
Less than 10nm, such as 3nm, 6nm, 9nm.It is the size of the polysilicon handle wafer 10, roughness, micro-
The concrete numerical value of ripple, edge grinding degree etc., can determine according to the requirement of technique, be not limited thereto.
It should be noted that the edge grinding degree of the polysilicon handle wafer refers to during grinding wafer, it is brilliant
Rounded edge and the difference in height of crystal circle center.
The step also includes：First time cmp is carried out to the polysilicon handle wafer 10.Described first
The lapping liquid that secondary cmp is used includes grinding agent and acid flux material, wherein, the acid flux material is used
In making the silicon on polysilicon handle wafer surface occur oxidation generation silica, to prevent grinding for polysilicon handle wafer surface
Mill is uneven.
In step S02, silicon fiml coating 12 is formed on the surface of the polysilicon handle wafer 10, such as Fig. 3 is formed
Shown wafer control slice 20,.Specifically, the method for forming the silicon fiml coating 12 is：CPS will be contained
(CycloPentaSilane, Si5H10) or/and CHS (CycloHexaSilane, Si6H12) solvent in institute
The surface for stating polysilicon handle wafer 10 carries out rotary coating, while carrying out treatment with ultraviolet light；It is follow-up that coating is completed
It is continuous to carry out ultraviolet light；Finally the silicon fiml coating of formation is heat-treated.
Also include step S03：Second of cmp is carried out to the silicon fiml coating 12.Described second
The lapping liquid that secondary cmp is used also includes grinding agent and acid flux material, and second of chemistry
The content of the grinding agent of mechanical lapping is less than the content of the grinding agent of the first time cmp, due to
First time cmp make it that polysilicon handle wafer surface is more smooth, therefore relative can reduce second
The content of grinding agent in the lapping liquid of secondary cmp, with cost-effective.
Also include step S04：The second silicon fiml coating 13 is formed on the silicon fiml coating 12, such as Fig. 4 is formed
Shown wafer control slice 20.In the present embodiment, the polysilicon handle wafer 10 is used to form the one of semiconductor devices
The total thickness of the silicon fiml coating in face is 10nm~3000nm, such as the total thickness of described silicon fiml coating be 50nm,
100nm、1000nm、2000nm。
In the present embodiment, two layers of silicon fiml coating is formed on the polysilicon handle wafer surface, for increasing wafer control
The crushing resistance of piece, in other embodiments, if dried layer silicon fiml coating can be formed on polysilicon handle wafer surface,
Need to determine the number of plies of silicon fiml coating according to actual process requirements, or directly in the polysilicon handle wafer
One layer of silicon fiml coating of thickness needed for surface is formed.
, will not by forming silicon fiml coating on the surface of polysilicon handle wafer, it is ensured that the crushing resistance of wafer control slice
Because outside pressure ruptures, and uses polysilicon handle wafer, the cost of wafer control slice is not only saved,
And avoid introduce other the problem of and have influence on testing result, it is ensured that the accuracy of testing result.
Accordingly, the present invention also provides a kind of wafer control slice, using manufacturer's legal system of above-mentioned wafer control slice
Make, the wafer control slice includes polysilicon handle wafer and the silicon fiml coating positioned at the polysilicon handle wafer surface.
It refer to shown in Fig. 4, the surface of the polysilicon handle wafer 10 is formed with silicon fiml coating described in two layers, i.e. silicon fiml
Coating 12 and silicon fiml coating 13, the thickness of total silicon fiml coating is 10nm~3000nm.
In summary, the present invention is provided wafer control slice and its manufacture method, pass through the table in polysilicon handle wafer
Face forms silicon fiml coating, it is ensured that the crushing resistance of wafer control slice, will not be ruptured because of outside pressure,
And the problem of using polysilicon handle wafer, not only save the cost of wafer control slice, and avoid introducing other
And have influence on testing result, it is ensured that the accuracy of testing result.
Foregoing description is only the description to present pre-ferred embodiments, not to any limit of the scope of the invention
Calmly, the those of ordinary skill in field of the present invention does according to the disclosure above content any change, modification, belong to
In the protection domain of claims.
Claims (13)
1. a kind of manufacture method of wafer control slice, it is characterised in that comprise the following steps：
Step S01：One polysilicon handle wafer is provided；
Step S02：Silicon fiml coating is formed on the surface of the polysilicon handle wafer.
2. the manufacture method of wafer control slice as claimed in claim 1, it is characterised in that the polycrystalline silicon wafer
Circle is combined by multiple polysilicon grains.
3. the manufacture method of wafer control slice as claimed in claim 2, it is characterised in that the polycrystalline silicon wafer
Circle includes more than 30%<111>The polysilicon grain of crystal orientation.
4. the manufacture method of wafer control slice as claimed in claim 1, it is characterised in that the polycrystalline silicon wafer
Round size range is 1.5 inches~15 inches, and the polysilicon handle wafer is used for the one side for forming semiconductor devices
Roughness be less than 0.5nm, the microwave of the polysilicon handle wafer is less than 10nm, the side of the polysilicon handle wafer
Edge lapping degree is less than 10nm.
5. the manufacture method of wafer control slice as claimed in claim 1, it is characterised in that form the silicon fiml
The method of coating is：The solvent for including CPS or/and CHS is revolved on the polysilicon handle wafer surface
Turn coating, while carrying out treatment with ultraviolet light；Coating proceeds ultraviolet light after completing；Finally carry out
Heat treatment.
6. the manufacture method of wafer control slice as claimed in claim 1, it is characterised in that step S02 it
It is preceding also to include：First time cmp is carried out to the polysilicon handle wafer.
7. the manufacture method of wafer control slice as claimed in claim 6, it is characterised in that also including step S03：
Second of cmp is carried out to the silicon fiml coating.
8. the manufacture method of wafer control slice as claimed in claim 7, it is characterised in that also including step S04：
The second silicon fiml coating is formed on the silicon fiml coating.
9. the manufacture method of wafer control slice as claimed in claim 8, it is characterised in that the chemistry twice
The lapping liquid of mechanical lapping includes grinding agent and acid flux material.
10. the manufacture method of wafer control slice as claimed in claim 9, it is characterised in that described second
The content of the grinding agent of cmp is less than the content of the grinding agent of the first time cmp.
11. the manufacture method of the wafer control slice as described in any one of claim 10, it is characterised in that described
The thickness that polysilicon handle wafer is used to form the silicon fiml coating of the one side of semiconductor devices is 10nm~3000nm.
12. a kind of wafer control slice, it is characterised in that using the crystalline substance as any one of claim 1~11
The manufacture method manufacture of circle control wafer, the wafer control slice includes polysilicon handle wafer and positioned at the polycrystalline silicon wafer
The silicon fiml coating of circular surfaces.
13. wafer control slice as claimed in claim 12, it is characterised in that the surface of the polysilicon handle wafer
It is formed with silicon fiml coating described in two layers.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610278144.2A CN107331609A (en) | 2016-04-28 | 2016-04-28 | Wafer control slice and its manufacture method |
| TW105129402A TWI600070B (en) | 2016-04-28 | 2016-09-09 | Dummy wafer and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610278144.2A CN107331609A (en) | 2016-04-28 | 2016-04-28 | Wafer control slice and its manufacture method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107331609A true CN107331609A (en) | 2017-11-07 |
Family
ID=60193139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610278144.2A Pending CN107331609A (en) | 2016-04-28 | 2016-04-28 | Wafer control slice and its manufacture method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107331609A (en) |
| TW (1) | TWI600070B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1457085A (en) * | 2002-04-22 | 2003-11-19 | 精工爱普生株式会社 | High-level silane composition and silicon film forming method utilizing it |
| JP2009038220A (en) * | 2007-08-02 | 2009-02-19 | Shin Etsu Chem Co Ltd | Dummy wafer |
| US20130341622A1 (en) * | 2011-03-15 | 2013-12-26 | Jx Nippon Mining & Metals Corporation | Polycrystalline Silicon Wafer |
-
2016
- 2016-04-28 CN CN201610278144.2A patent/CN107331609A/en active Pending
- 2016-09-09 TW TW105129402A patent/TWI600070B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1457085A (en) * | 2002-04-22 | 2003-11-19 | 精工爱普生株式会社 | High-level silane composition and silicon film forming method utilizing it |
| JP2009038220A (en) * | 2007-08-02 | 2009-02-19 | Shin Etsu Chem Co Ltd | Dummy wafer |
| US20130341622A1 (en) * | 2011-03-15 | 2013-12-26 | Jx Nippon Mining & Metals Corporation | Polycrystalline Silicon Wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201738949A (en) | 2017-11-01 |
| TWI600070B (en) | 2017-09-21 |
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Application publication date: 20171107 |
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