CN107316858B - High dielectric film layer structure and its application and preparation method - Google Patents
High dielectric film layer structure and its application and preparation method Download PDFInfo
- Publication number
- CN107316858B CN107316858B CN201710520577.9A CN201710520577A CN107316858B CN 107316858 B CN107316858 B CN 107316858B CN 201710520577 A CN201710520577 A CN 201710520577A CN 107316858 B CN107316858 B CN 107316858B
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric
- film layer
- thickness
- inhibition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 516
- 230000005764 inhibitory process Effects 0.000 claims abstract description 67
- 230000005641 tunneling Effects 0.000 claims abstract description 20
- 239000002356 single layer Substances 0.000 claims abstract description 15
- 230000000694 effects Effects 0.000 claims abstract description 12
- 239000003990 capacitor Substances 0.000 claims description 44
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 claims description 35
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical group O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 17
- MEYZYGMYMLNUHJ-UHFFFAOYSA-N tunicamycin Natural products CC(C)CCCCCCCCCC=CC(=O)NC1C(O)C(O)C(CC(O)C2OC(C(O)C2O)N3C=CC(=O)NC3=O)OC1OC4OC(CO)C(O)C(O)C4NC(=O)C MEYZYGMYMLNUHJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000004408 titanium dioxide Substances 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 239000010955 niobium Substances 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000002243 precursor Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims 1
- 150000005837 radical ions Chemical class 0.000 claims 1
- 230000001629 suppression Effects 0.000 claims 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical group O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 25
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical group [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 23
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 22
- 238000010586 diagram Methods 0.000 description 8
- SHPBBNULESVQRH-UHFFFAOYSA-N [O-2].[O-2].[Ti+4].[Zr+4] Chemical group [O-2].[O-2].[Ti+4].[Zr+4] SHPBBNULESVQRH-UHFFFAOYSA-N 0.000 description 7
- 230000008859 change Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910052593 corundum Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- HFLAMWCKUFHSAZ-UHFFFAOYSA-N niobium dioxide Inorganic materials O=[Nb]=O HFLAMWCKUFHSAZ-UHFFFAOYSA-N 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 229910052789 astatine Inorganic materials 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Abstract
The present invention provides a kind of high dielectric film layer structure and application and preparation method, structure includes: LAM type dielectric structure, including at least one layer of first dielectric layer and at least one layer of second dielectric layer, the forbidden bandwidth of second dielectric layer is greater than the forbidden bandwidth of the first dielectric layer, the thickness of the second dielectric layer of single layer is less than or equal to the thickness of the first dielectric layer of single layer, and quantum tunnel inhibition layer, it is set on the surface of LAM type dielectric structure, or between the first dielectric layer and the second dielectric layer of LAM type dielectric structure, the dielectric constant of quantum tunneling inhibition layer is greater than the dielectric constant of the first dielectric layer and is greater than the dielectric constant of the second dielectric layer.Scheme through the invention, high dielectric film layer structure can be in the case where capacitance dielectric layer thickness be constant, reduce the thickness of equivalent oxide, it can also be while keeping or reducing equivalent oxide thickness, there are enough physical thickness to limit the influence of quantum tunneling effect, prevents leakage current from increasing so as to cause component failure.
Description
Technical field
The invention belongs to semiconductor device processing technology fields, more particularly to a kind of high dielectric film layer structure and its system
Preparation Method and a kind of capacitor arrangement and preparation method thereof containing the high dielectric film layer structure.
Background technique
Capacitor is a kind of passive electronic components with electrostatic format of field storage energy.In simplest form, capacitor
It is isolated including two conductive plates, and between two conductive plates by being referred to as dielectric insulating materials.The capacitor of capacitor
It is directly proportional to the surface area of pole plate, between pole plate at a distance from be inversely proportional.The capacitor of capacitor additionally depends on the object of separation pole plate
The dielectric constant of matter.The standard unit of capacitor is method (farad, referred to as F), this is a big unit, and more common unit is
Microfarad (microfarad, abbreviation μ F) and pico farad (picofarac, abbreviation PF), wherein 1 μ F=10-6F, 1pF=10-12F。
Capacitor can be manufactured on integrated circuit (IC) chip.In dynamic random access memory (dynamic
Random access memory, abbreviation DRAM) in, capacitor is commonly used in connecting with transistor.Capacitor, which helps to maintain, to be deposited
The content of reservoir.Due to its small physical size, these components have low capacitor.They must be with thousands of frequencies per second
It recharges, otherwise, DRAM will lose data.The basic structure of capacitor is sandwich structure, comprising bottom crown, high K dielectric and
Top crown.For DRAM capacitor, high K dielectric is key factor.
Currently, as the semiconductor devices such as dynamic random access memory (DRAM) are with the continuous contracting of device feature size
Small, oxidated layer thickness has been approached the limitation of quantum tunneling effect (Quantum tunneling effect), cause leakage current with
Oxide thickness reduction is exponentially increased.And high dielectric constant oxide can maintain enough driving currents, and can protect
Increase the reality of oxide layer in the case where holding same equivalent oxidated layer thickness (equivalent oxide thickness, EOT)
Physical thickness, the sub- tunneling effect of effective inhibitory amount.In the prior art, some materials dielectric constant with higher, but its forbidden band
Narrower width has the shortcomings that high electric leakage, and in order to solve electrical leakage problems, the thickness of capacitance dielectric layer must just increase, such one
Come, the capacitance of part can be sacrificed instead；Other material dielectric constants are lower, and forbidden bandwidth is wider, excellent with Low dark curient
Point, but excessive material layer will lead to effective dielectric constant decline, thus limit its charge storage capacity.
Therefore, the film layer structure and its capacitor of high K dielectric how are designed, so that device feature size is maintaining driving electricity
It can continue to be reduced under conditions of stream, and prevent leakage current increase from having become urgently to be resolved one of those skilled in the art
Important technological problems.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of high dielectric film layer structure and
It is applied and preparation method, for solving the problems, such as that magnitude of the stored charge in the prior art is small, leakage current is high.
In order to achieve the above objects and other related objects, the present invention provides a kind of high dielectric film layer structure, comprising:
LAM type dielectric structure, including at least one layer of first dielectric layer and at least one layer of second dielectric layer, described second is situated between
The forbidden bandwidth of electric layer is greater than the forbidden bandwidth of first dielectric layer, and the thickness of the second dielectric layer described in single layer is less than or equal to
The thickness of first dielectric layer described in single layer；And
Quantum tunnel inhibition layer is set on the surface of the LAM type dielectric structure, or is located at the LAM type dielectric
Between first dielectric layer and second dielectric layer of structure, the dielectric constant of the quantum tunneling inhibition layer is greater than described
The dielectric constant of first dielectric layer and the dielectric constant for being greater than second dielectric layer.
As a preferred solution of the present invention, the quantum tunnel inhibition layer is titanium dioxide layer.
As a preferred solution of the present invention, first dielectric layer is titanium dioxide zirconium layer, and second dielectric layer is
Aluminum oxide layer.
As a preferred solution of the present invention, the LAM type dielectric structure is selected from zirconium dioxide and aluminum oxide
The LAM type structure and three that LAM type structure, zirconium dioxide and the aluminum oxide and zirconium dioxide being sequentially stacked are sequentially stacked
One of in the group that the LAM type structure that Al 2 O and zirconium dioxide and aluminum oxide are sequentially stacked is constituted.
As a preferred solution of the present invention, first dielectric layer has the dielectric constant more than or equal to 10, described
Second dielectric layer has the forbidden bandwidth more than or equal to 8.
As a preferred solution of the present invention, doped in silicon nitride and silicon oxynitride in the LAM type dielectric structure
At least one.
As a preferred solution of the present invention, the high dielectric film layer structure with a thickness of 4~10nm.
As a preferred solution of the present invention, the high dielectric film layer structure further includes electric leakage barrier layer, and described
The quantity of LAM type dielectric structure is at least two, wherein the electric leakage barrier layer is between the LAM type dielectric structure.
As a preferred solution of the present invention, the material on the electric leakage barrier layer includes silica, and the electric leakage
The thickness on barrier layer is less than the thickness of the second dielectric layer described in single layer in the LAM type dielectric structure.
The present invention also provides a kind of capacitor arrangements, comprising:
Bottom crown is connected with lower electrode；
Top crown is connected with top electrode；And
High dielectric film layer structure as described in any one of the above scheme, be located at the top crown and the bottom crown it
Between.
As a preferred solution of the present invention, the quantum tunnel inhibition layer is located at the LAM type dielectric structure and institute
It states between bottom crown.
As a preferred solution of the present invention, the quantity of the LAM type dielectric structure is 4, by zirconium dioxide and three
The LAM type dielectric structure that Al 2 O is sequentially stacked is constituted, and 4 LAM type dielectric structures are sequentially stacked from bottom to top；
The quantity of the quantum tunnel inhibition layer is 2 layers, is respectively arranged between the bottom crown and the titanium dioxide zirconium layer of bottom, and
Between the aluminum oxide layer and the top crown of top layer.
As a preferred solution of the present invention, at least one section of the bottom crown is U-shaped, the high dielectric film
The corresponding section of layer structure and the top crown is M type, constitutes double sided capacitor structure.
The present invention also provides a kind of preparation method of high dielectric film layer structure, the high dielectric film layer structure is by N
The structure that tunic layer is constituted, wherein N is the integer more than or equal to 3, and the preparation method includes:
At least one LAM type dielectric structure is formed, and the LAM type dielectric structure includes at least one layer of first dielectric layer
And at least one layer of second dielectric layer, the forbidden bandwidth of second dielectric layer are greater than the forbidden bandwidth of first dielectric layer, and
The unit thickness of second dielectric layer is less than or equal to the unit thickness of first dielectric layer；And
At least one layer of quantum tunnel inhibition layer is formed, and on its surface for being formed in the LAM type dielectric structure, or
It is formed between first dielectric layer of the LAM type dielectric structure and second dielectric layer, and the quantum tunneling presses down
The dielectric constant of preparative layer is greater than the dielectric constant of first dielectric layer and is greater than the dielectric constant of second dielectric layer.
As a preferred solution of the present invention, the quantum tunnel inhibition layer is titanium dioxide layer, first dielectric
Layer is titanium dioxide zirconium layer, and second dielectric layer is aluminum oxide layer.
As a preferred solution of the present invention, the mistake for the high dielectric film layer structure being made of N tunic layer is formed
Include the steps that being formed second layer film layer in journey to n-th layer film layer, specific steps include:
One layer of hydroxide ion layer is formed in the upper surface of provided first layer film layer, and makes the hydroxide ion layer
Simple substance corresponding with oxide contained by the second layer film layer is reacted, to form the second layer film layer；And
One layer of hydroxide ion layer is formed in the upper surface for being formed by N-1 tunic layer, and makes the hydroxide ion
Layer simple substance corresponding with oxide contained by n-th layer film layer is reacted, to form n-th layer film layer.
As a preferred solution of the present invention, during forming the second layer film layer and n-th layer film layer, processing procedure
Gas is made selected from least one of zirconium (Zr), silicon (Si), aluminium (Al), niobium (Nb), hafnium (Hf) and titanium (Ti) constituted group
Stroke pressure is 0.1~2 support, and process temperatures are 200~400 DEG C.
As a preferred solution of the present invention, which is characterized in that the method for forming the hydroxide ion layer include:
In reacting furnace, it is selected from one of vapor and ozone to be passed through gas, and the mode heated is to hydroxyl to be formed
The structure of sheath is handled, with the upper surface of the structure of the hydroxide ion layer to be formed formed one layer of hydroxyl from
Sublayer.
The present invention also provides a kind of preparation methods of capacitor arrangement, include the following steps:
1) bottom crown is provided；
2) one layer of hydroxide ion layer is formed in the bottom crown upper surface, makes the hydroxide ion layer and the first tunic
The corresponding simple substance of oxide contained by layer is reacted, to form first layer film layer；
3) second layer is prepared to N according to the method as described in any one of the above scheme in the first layer film surface
Tunic layer, to form the high dielectric film layer structure being made of N tunic layer, wherein N is the integer more than or equal to 3；And
4) top crown is formed in the obtained body structure surface of step 3).
As described above, high dielectric film layer structure of the invention and its application and preparation method, have the advantages that
1) high dielectric film layer structure of the invention can reduce equivalent oxygen in the case where capacitance dielectric layer thickness is constant
Change the thickness of layer；
2) high dielectric film layer structure of the invention can have enough while keeping or reducing equivalent oxide thickness
Physical thickness limit the influence of quantum tunneling effect, prevent leakage current from increasing so as to cause component failure.
Detailed description of the invention
Fig. 1 to Fig. 5 is shown as the schematic diagram of the high dielectric film layer structure of the offer of the embodiment of the present invention one.
Fig. 6 to Fig. 8 is shown as the schematic diagram of the LAM type dielectric structure of the offer of the embodiment of the present invention one.
The high dielectric film layer structure with earth leakage protective layer that Fig. 9 to Figure 11 is shown as the offer of the embodiment of the present invention one is shown
It is intended to.
Figure 12 to Figure 16 is shown as the structure of each step in capacitor arrangement preparation process provided by Embodiment 2 of the present invention
Schematic diagram.
Figure 17 to Figure 18 is shown as the schematic diagram of other two kinds of capacitor arrangements provided by Embodiment 2 of the present invention.
Figure 19 is shown as the comparison figure of each material dielectric constant.
Figure 20 is shown as the relation schematic diagram of each material dielectric constant and forbidden bandwidth.
Component label instructions
1 high dielectric film layer structure
11 LAM type dielectric structures
111 first dielectric layers
112 second dielectric layers
12 quantum tunnel inhibition layers
13 electric leakage barrier layers
2 capacitor arrangements
21 bottom crowns
22 top crowns
23 lower electrodes
24 top electrodes
25 insulating layers
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Figure 20.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout form may also be increasingly complex.
Embodiment one
The present invention provides a kind of high dielectric film layer structure, and as shown in Fig. 1~5, the high dielectric film layer structure 1 is wrapped
It includes:
LAM type dielectric structure 11, the LAM type dielectric structure include at least one layer of first dielectric layer 111 and at least one
The second dielectric layer 112 of layer, the forbidden bandwidth of second dielectric layer 112 are greater than the forbidden bandwidth of first dielectric layer 111, and
The thickness of second dielectric layer 112 described in single layer is less than or equal to the thickness of the first dielectric layer 111 described in single layer；And
Quantum tunnel inhibition layer 12 is set on the surface of the LAM type dielectric structure 11, or is located at the LAM type
Between first dielectric layer 111 and second dielectric layer 112 of dielectric structure 11, Jie of the quantum tunneling inhibition layer 12
Electric constant is greater than the dielectric constant of first dielectric layer 111 and is greater than the dielectric constant of second dielectric layer 112.
Specifically, in the present invention, K represents dielectric constant, high K represents dielectric constant greater than 3.9.In addition, being changed with described
For laminar dielectric structure 11 is only made of one layer of first dielectric layer 111 and one layer of second dielectric layer 112, the quantum tunnel
Inhibition layer 12 can be located at the lower surface or upper surface of the LAM type dielectric structure 11, at this point, the quantum tunnel inhibition layer
12 are in contact with one layer in the LAM type dielectric structure 11, i.e., the described quantum tunnel inhibition layer and the first dielectric layer 111
Or second dielectric layer 112 be in contact, as shown in Figure 1 and Figure 2, in addition, the quantum tunnel inhibition layer 12 can also be located at it is described repeatedly
Between each layer of laminar dielectric structure 11, i.e., the described quantum tunnel inhibition layer 12 can simultaneously with the first dielectric layer 111 and second
Dielectric layer 112 is in contact, as shown in figure 3, for the case where being in contact with two class film layers.
Further, when the quantity of the LAM type dielectric structure 11 is two or more, the quantum tunnel inhibits
Layer 12 can be situated between each LAM type dielectric structure 11 it is of course also possible to be located at two or more LAM types
The upper surface or lower surface for the laminated construction that electric structure 11 collectively forms, as shown in figure 4, being shown as multiple LAM type dielectric knots
Structure 11 is sequentially stacked, and the quantum tunnel inhibition layer 12 is located at the structural schematic diagram of its lower surface.
Meanwhile the quantity of the quantum tunnel inhibition layer 12 may be two or more layers, as shown in figure 5, being shown as more
The high dielectric film layer structure that layer quantum tunnel inhibition layer 12 and multiple LAM type dielectric structures 11 are constituted, it is laminated by one
Formula dielectric structure 11 and positioned at 11 lower surface of LAM type dielectric structure one layer of quantum tunnel inhibition layer 12 constitute one
Loop structure, two or more loop structures are sequentially stacked, and constitute the high dielectric film layer structure.
It should be noted that in other embodiments of the invention, in order to more effectively reduce the thickness of equivalent oxide
Degree, and have enough physical thickness while keeping or reducing equivalent oxide thickness to limit the shadow of quantum tunneling effect
It rings, prevents leakage current from increasing so as to cause component failure, the quantity of the LAM type dielectric structure 11 can be set according to actual demand
It sets, for example 3~100, in the present embodiment, preferably 4, the quantity of the quantum tunnel inhibition layer 12 may be to appoint
Layer of anticipating preferably 2 layers, it is of course also possible to be 3~100 layers, is not particularly limited herein in the present embodiment.
As an example, the quantum tunnel inhibition layer 12 is titanium dioxide layer.
Certainly, in other embodiments, the quantum tunnel inhibition layer 12 can also be hafnium oxide (HfO2) layer and two
Niobium oxide (NbO2At least one of) layer, on the one hand the quantum tunnel inhibition layer 12 may be used because it is with high dielectric constant
To provide enough capacitive energies for capacitance structure, on the other hand, the thickness of equivalent oxide can also be reduced, thus adapting to
Device feature size reduces element leakage situation in the case where reducing.
As an example, first dielectric layer 111 is titanium dioxide zirconium layer (ZrO2), second dielectric layer 112 is three oxygen
Change two aluminium layer (Al2O3)。
As an example, the LAM type dielectric structure 11 is selected from the LAM type that zirconium dioxide and aluminum oxide are sequentially stacked
Structure, as shown in fig. 6, being ZA type structure；The LAM type structure that zirconium dioxide and aluminum oxide and zirconium dioxide are sequentially stacked,
As shown in fig. 7, being ZAZ type structure；The LAM type structure that aluminum oxide and zirconium dioxide and aluminum oxide are sequentially stacked, such as
Shown in Fig. 8, be AZA type structure, in any one, certainly, in other embodiments, can also in above structure appoint
The combination of two kinds of meaning or more, wherein " any two kinds or more " refer to any two kinds of combination or any two or more
Combination.
As an example, first dielectric layer has the dielectric constant more than or equal to 10, second dielectric layer has big
In the forbidden bandwidth for being equal to 8.
Specifically, the quantum tunnel inhibition layer 12 includes but is not limited to titanium dioxide (TiO2) layer, hafnium oxide (HfO2)
Layer, columbium dioxide (NbO2) layer, it can be the arbitrarily quantum of the function of the realization quantum tunnel inhibition layer 12 in the present invention
Tunnel inhibition layer.Wherein, when the LAM type dielectric structure 11 is selected from zirconium dioxide/aluminum oxide structure, the quantum
Tunnel inhibition layer 12 can be located at only zirconium dioxide layer surface, or be only located at aluminum oxide layer surface, or be located at zirconium dioxide
Between layer and aluminum oxide layer；When the LAM type dielectric structure 11 is selected from zirconium dioxide/aluminum oxide/zirconium dioxide knot
When structure, the quantum tunnel inhibition layer 12 can be located at only zirconium dioxide layer surface, i.e. upper surface or lower surface；It can also be located at
Between titanium dioxide zirconium layer and aluminum oxide layer, at this point it is possible to be located at any one zirconium dioxide/aluminum oxide interface it
Between, it is possible to have the quantum tunnel inhibition layer 12 is respectively provided between all zirconium dioxides/aluminum oxide interface, other
Example is similar, numerous to list herein.
In addition, first dielectric layer have more than or equal to 10 dielectric constant, second dielectric layer have be greater than etc.
In 8 forbidden bandwidth, and the thickness of the second dielectric layer described in single layer is less than or equal to the thickness of the first dielectric layer described in single layer, at this
In embodiment, Al2O3Compared to ZrO2Its dielectric constant is lower, and forbidden bandwidth is wider, has the advantages that Low dark curient, but excessively
Al2O3It will lead to effective dielectric constant decline, thus limit its charge storage capacity, ZrO2Dielectric constant with higher, but its
Forbidden bandwidth is relatively narrow, has the shortcomings that high electric leakage, in order to solve electrical leakage problems, the thickness of capacitance dielectric layer must just increase, such as
This one, the capacitance of part can be sacrificed instead, the above-mentioned characteristic based on the two, carry out the present embodiment in the first dielectric layer
111 and second dielectric layer 112 setting, have a clear superiority in terms of the leakage current of capacitor and stability.
As an example, doped at least one of silicon nitride and silicon oxynitride in the LAM type dielectric structure 11.
Specifically, also doped in silicon nitride (SiN) and silicon oxynitride (SiON) in the LAM type dielectric structure 11
It is at least one.Wherein, the silicon nitride or silicon oxynitride of doping only occupy the sky of the part in titanium dioxide zirconium layer or aluminum oxide layer
Position, does not constitute complete film, and in the present invention, silicon nitride or silicon oxynitride doping in the LAM type dielectric structure 11 can
With the electric leakage being further reduced in the high K dielectric cycling element.
As an example, the high dielectric film layer structure 1 with a thickness of 4~10nm.
Specifically, the thickness of the high dielectric film layer structure 1 is preferably 6~9nm, it is selected as 8nm in the present embodiment,
In addition, the thickness of first dielectric layer 111 can be 1.5~10nm, 4nm is selected as in the present embodiment；Second dielectric
The thickness of layer 112 can be 0.1~5nm, be selected as 2nm in the present embodiment；The thickness of the quantum tunnel inhibition layer 12 can be with
For 0.1~8nm, preferably 0.2~5nm, it is selected as 2nm in the present embodiment, depending on actual demand capacitance demand,
This is not particularly limited, and the quantum tunnel inhibition layer 12 is intended to because it is with high dielectric constant, on the one hand can be capacitor
On the other hand structure, which provides enough capacitive energies, can also reduce the thickness of equivalent oxide, thus adapting to device feature
Element leakage situation is reduced in the case where size reduction.
As an example, the high dielectric film layer structure 1 further includes electric leakage barrier layer 13, and the LAM type dielectric structure
11 quantity is at least two, wherein the electric leakage barrier layer 13 is between the LAM type dielectric structure 11.
As an example, the material on the electric leakage barrier layer 13 includes silica, and the thickness on the electric leakage barrier layer 13
Less than the thickness of the second dielectric layer 112 described in single layer in the LAM type dielectric structure 11.
Specifically, the electric leakage flow barrier 13 can be the atomic layer of continuously or discontinuously form, it is preferred to use thermal diffusion
Discontinuous atomic layer, it is described electric leakage flow barrier 13 material include but is not limited to silica, silica taboo with higher
Bandwidth can be effectively prevented electric leakage, and the thickness range of the electric leakage flow barrier is 0.5~2.5nm.Such as the institute of Fig. 9~11
Show, the electric leakage barrier layer 13 is between the LAM type dielectric structure 11, including between the LAM type dielectric structure 11
The case where there is no when quantum tunnel inhibition layer 12, as shown in figure 9, further including shape between the LAM type dielectric structure 11
The case where Cheng Youyi layers of quantum tunnel inhibition layer 12, at this point, the electric leakage barrier layer 13 is located at the LAM type dielectric structure 11
Between and further between the quantum tunnel inhibition layer 12 and the LAM type dielectric structure 11 of layer disposed thereon, or
Positioned at the quantum tunnel inhibition layer 12 and between the LAM type dielectric structure 11 of its lower layer, certainly, in other embodiments
In, there is also a variety of schemes that the function may be implemented, and are not particularly limited herein.
The present invention also provides a kind of preparation methods of high dielectric film layer structure, wherein the preparation method is that preparation is originally
The method for inventing protected high dielectric film layer structure, specifically, the high dielectric film layer structure is to be made of N tunic layer
Structure, wherein N is integer more than or equal to 3, and the preparation method includes:
At least one LAM type dielectric structure 11 is formed, and the LAM type dielectric structure 11 includes that at least one layer first is situated between
Electric layer 111 and at least one layer of second dielectric layer 112, the forbidden bandwidth of second dielectric layer 112 are greater than first dielectric layer
111 forbidden bandwidth, and the unit thickness of second dielectric layer 112 is less than or equal to the unit thickness of first dielectric layer 111
Degree；And
Form at least one layer of quantum tunnel inhibition layer 12, and its surface for being formed in the LAM type dielectric structure 11
On, or be formed between first dielectric layer 111 of the LAM type dielectric structure 11 and second dielectric layer 112, and
The dielectric constant of the quantum tunneling inhibition layer 12 is greater than the dielectric constant of first dielectric layer 111 and is greater than described second and is situated between
The dielectric constant of electric layer 112.
Specifically, the high dielectric film layer structure 1 is using low-pressure chemical vapor deposition (LPCVD) or is also possible to original
Sublayer deposition (ALD) (being not limited to one chip or batch reaction chamber) mode is formed.
As an example, the quantum tunnel inhibition layer 12 is titanium dioxide layer, first dielectric layer 111 is zirconium dioxide
Layer, second dielectric layer 112 are aluminum oxide layer.
As an example, including forming second during forming the high dielectric film layer structure being made of N tunic layer
The step of tunic layer to n-th layer film layer, specific steps include:
One layer of hydroxide ion layer is formed in the upper surface of provided first layer film layer, and makes the hydroxide ion layer
Simple substance corresponding with oxide contained by second layer film layer is reacted, to form second layer film layer；And
One layer of hydroxide ion layer is formed in the upper surface for being formed by N-1 tunic layer, and makes the hydroxide ion
Layer simple substance corresponding with oxide contained by n-th layer film layer is reacted, to form n-th layer film layer.
Specifically, in the present embodiment, the first layer film layer can be provided directly, it can be aluminum oxide layer, two
Zirconium oxide layer or quantum tunnel inhibition layer, such as TiO2Layer.
As an example, during forming the second layer film layer and n-th layer film layer, process gas Zr, Si, Al,
At least one of Nb, Hf or Ti, process pressure are 0.1~2 support (torr), and preferably 0.1~1 support selects in the present embodiment
For 0.5torr, process temperatures are 200~400 DEG C, and preferably 250~350 DEG C, 300 DEG C are selected as in the present embodiment.
As an example, the method for forming the hydroxide ion layer includes: in reacting furnace, to be passed through H2O or O3And carry out
The mode of heating handles the structure of hydroxide ion layer to be formed, in the structure of the hydroxide ion layer to be formed
Upper surface formed one layer of hydroxide ion layer.
Specifically, the structure of hydroxide ion layer to be formed is placed in reacting furnace (such as boiler tube), and lead into reacting furnace
Enter H2O or O3, reacting furnace is heated, so that one layer of hydroxide ion layer is formed in body structure surface to be processed, then, then
It is passed through the corresponding simple substance of oxide contained in institute's film layer to be formed, is reacted as precursor with the hydroxide ion layer,
To form required oxide membranous layer.
Embodiment two
The present invention also provides a kind of capacitor arrangement, the capacitor arrangement includes high dielectric film described in embodiment one
Layer structure 1, as shown in Figure 16~18, comprising:
Bottom crown 21 is connected with lower electrode 23；
Top crown 22 is connected with top electrode 24；
High dielectric film layer structure 1, between the top crown 22 and the bottom crown 21, wherein the high electricity is situated between
Matter film layer structure 1 is the high dielectric film layer structure as described in above-mentioned any one scheme.
It should be noted that the calculation formula of capacitor capacitance are as follows: C=K εoA/tox(wherein, K: the dielectric of dielectric layer is normal
Number, εo: permittivity of vacuum, A: dielectric layer area, tox: medium thickness), in the case where not causing quantum tunneling effect,
Capacitor can be improved by reducing medium thickness or promoting dielectric layer constant.In addition, equivalent oxide thickness
(equivalent oxide thickness, EOT) are as follows: in the constant situation of dielectric layer with high dielectric constant holding capacitor, conversion
SiO with same units area capacitance2Medium thickness, specific reduction formula are as follows:
C=(Khigh kεoA)/(thigh kThe ε of)=3.9oA/teq；
EOT=teq=(3.9thigh k)/(Khigh k)；
Here, in thigh kIn the case that thickness is constant, due to the dielectric constant ratio SiO of dielectric layer with high dielectric constant2Greatly,
Then its EOT is small, and device feature size can be made to continue to be reduced under conditions of maintaining driving current, in the application, into
One step uses the quantum tunnel inhibition layer 12, such as TiO2Layer has very high dielectric constant, TiO2Dielectric constant be 80,
In the case where can also being able to maintain at the same time or reduce equivalent oxide thickness, enough physical thickness can be provided to limit
The influence of quantum tunneling effect, prevents leakage current from increasing, and then prevents component failure, specifically, the dielectric constant values of each material
Etc. parameters comparison it is as shown in FIG. 19 and 20, wherein Band Gap (eV) refers to the forbidden bandwidth of material, △ Ec (eV) to
Si refers to that the conduction band energy between the material and silicon is poor.
As an example, the quantum tunnel inhibition layer 12 be located at the LAM type dielectric structure 11 and the bottom crown 21 it
Between.
Certainly, in other embodiments, the quantum tunnel inhibition layer 12 can be located at the LAM type dielectric structure 11
Between the top crown 22 or the quantum tunnel inhibition layer 12 can also be located at each LAM type dielectric structure 11 it
Between, it can also be located between each first dielectric layer and the second dielectric layer of the LAM type dielectric structure 11, it is of course also possible to together
When two or more positions in above-mentioned position, be not particularly limited herein.
Specifically, the quantum tunnel inhibition layer 12 is located at the LAM type dielectric structure 11 and top crown or bottom crown
Between, it is in contact with upper bottom crown, holds to be further ensured that and obtain bigger charge storage using high dielectric film layer structure
Amount, advantageously reduces leakage current, to be conducive to the reduction of dynamic random access memory refreshing frequency, and improves dynamic random
Access the data retention of memory.
As an example, the quantity of the LAM type dielectric structure 11 is 4, successively folded by zirconium dioxide and aluminum oxide
The LAM type dielectric structure set is constituted, and 4 LAM type dielectric structures 11 are sequentially stacked from bottom to top；The quantum tunnel
The quantity of inhibition layer 12 is 2 layers, wherein the quantum tunnel inhibition layer 12 is respectively arranged at the bottom crown 21 and the two of bottom
Between zirconium oxide layer and between the aluminum oxide layer and the top crown 22 of top layer, as shown in figure 16.
As an example, described at least one section of bottom crown 21 be it is U-shaped, the high dielectric film layer structure and it is described on
The corresponding section of pole plate 22 is M type, constitutes double sided capacitor structure, as shown in figure 18.
Specifically, the high dielectric film layer structure 1 is formed simultaneously inner surface and outer surface in U-shaped bottom crown 21, institute
The outer surface that top crown 22 is formed in the high dielectric film layer structure 1 is stated, double sided capacitor structure is constituted, relative to single side electricity
Higher capacitance may be implemented in structure of container, double sided capacitor structure.Certainly, in other embodiments, the capacitor
Structure can also be designed according to actual needs, should not excessively be limited the scope of the invention herein.
The present invention also provides a kind of preparation methods of capacitor arrangement, as shown in Figure 12~17, wherein the preparation method
For the method for the capacitor arrangement that the preparation present invention is protected, include the following steps:
1) bottom crown 21 is provided, as shown in figure 12；
2) one layer of hydroxide ion layer is formed in 21 surfaces on the bottom crown, makes the hydroxide ion layer and first layer
The corresponding simple substance of oxide contained by film layer is reacted, to form first layer film layer, as shown in figure 13；
3) in the first layer film surface according to the high dielectric as described in a kind of any one scheme of above-described embodiment
The preparation method of film layer structure prepares the second layer to n-th layer film layer, to form the high dielectric film layer knot being made of N tunic layer
Structure, wherein N is the integer more than or equal to 3, as shown in Figure 14~17；
4) top crown 22 is formed in the obtained body structure surface of step 3), as shown in FIG. 16 and 17.
Specifically, being zirconium dioxide/aluminum oxide laminated construction with the LAM type dielectric structure 11, the quantum is satisfied
Wearing inhibition layer 12 is TiO2Layer, and the quantum tunnel inhibition layer 12 is located at the bottom crown 21 and each LAM type dielectric knot
Between structure between each LAM type dielectric structure and the top crown 22 for, in detail describe the present embodiment capacitor knot
The preparation method of structure first provides a bottom crown 21 in the preparation of capacitor arrangement, and in its surface formed one layer of hydroxyl from
Sublayer, then make it that Chemisorption occur with Ti and generate TiO2Layer, as the high dielectric film layer knot between upper bottom crown
The first layer of structure, then, according to the preparation method in embodiment one, in the TiO2Layer surface forms one layer of hydroxide ion
Layer, and make it that Chemisorption occur with Zr and generate titanium dioxide zirconium layer, as the second layer of high dielectric film layer structure, according to
It is secondary to analogize, continue to generate aluminum oxide/zirconium dioxide/aluminum oxide film layer, until completing the preparation of n-th layer film layer, most
Afterwards, top crown is deposited in the high dielectric film layer body structure surface, completes the preparation of capacitor arrangement.Certainly, other real
It applies in example, different high dielectric film layer structures can also be formed, be not particularly limited herein, wherein Figure 17 shows it
One of example.
In conclusion the present invention provides a kind of high dielectric film layer structure and its application and preparation method, the high electricity is situated between
Matter film layer structure includes: LAM type dielectric structure, including at least one layer of first dielectric layer and at least one layer of second dielectric layer, described
The forbidden bandwidth of second dielectric layer is greater than the forbidden bandwidth of first dielectric layer, and the thickness of the second dielectric layer described in single layer is small
In the thickness for being equal to the first dielectric layer described in single layer；And quantum tunnel inhibition layer, it is set to the one of the LAM type dielectric structure
On surface, or between first dielectric layer and second dielectric layer of the LAM type dielectric structure, the quantum
The dielectric constant of tunnelling inhibition layer is greater than the dielectric constant of first dielectric layer and normal greater than the dielectric of second dielectric layer
Number.Scheme through the invention, high dielectric film layer structure of the invention can in the case where capacitance dielectric layer thickness is constant,
The thickness of equivalent oxide is reduced, and while keeping or reducing equivalent oxide thickness, there are enough physical thickness to limit
The influence of quantum tunneling effect processed, prevents leakage current from increasing so as to cause component failure.So the present invention effectively overcome it is existing
Various shortcoming in technology and have high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (12)
1. a kind of high dielectric film layer structure characterized by comprising
LAM type dielectric structure, including at least one layer of first dielectric layer and at least one layer of second dielectric layer, second dielectric layer
Forbidden bandwidth be greater than first dielectric layer forbidden bandwidth, and the thickness of the second dielectric layer described in single layer be less than or equal to single layer
The thickness of first dielectric layer；And
Quantum tunnel inhibition layer, the dielectric constant of the quantum tunneling inhibition layer be greater than the dielectric constant of first dielectric layer and
Greater than the dielectric constant of second dielectric layer, first dielectric layer have more than or equal to 10 dielectric constant, described second
Dielectric layer have more than or equal to 8 forbidden bandwidth, the high dielectric film layer structure with a thickness of 4~10nm, the quantum is satisfied
Wear inhibition layer with a thickness of 0.2~5nm, to provide enough physical thickness while keeping or reducing equivalent oxide thickness
Limit quantum tunneling effect, the quantum tunnel inhibition layer is titanium dioxide layer, the quantum tunnel inhibition layer attaches contact
The bottom crown of capacitor arrangement, the first dielectric layer of the bottom of the LAM type dielectric structure, which attaches, contacts the quantum tunnel suppression
Preparative layer；
Wherein, during the quantum tunneling inhibition layer and the LAM type dielectric structure are formed, in structure table to be processed
Face forms one layer of hydroxide ion layer, then, then is passed through the corresponding simple substance of oxide contained in institute's film layer to be formed, as
Precursor is reacted with the hydroxide ion layer, thus oxide membranous layer required for being formed.
2. high dielectric film layer structure according to claim 1, which is characterized in that adulterated in the LAM type dielectric structure
There are at least one of silicon nitride and silicon oxynitride.
3. high dielectric film layer structure according to claim 1, which is characterized in that the high dielectric film layer structure is also wrapped
Electric leakage barrier layer is included, and the quantity of the LAM type dielectric structure is at least two, wherein the electric leakage barrier layer is located at described
Between LAM type dielectric structure.
4. high dielectric film layer structure according to claim 3, which is characterized in that it is described electric leakage barrier layer material include
Silica, and the thickness on the electric leakage barrier layer is less than the thickness of the second dielectric layer described in single layer in the LAM type dielectric structure
Degree.
5. a kind of capacitor arrangement characterized by comprising
Bottom crown is connected with lower electrode；
Top crown is connected with top electrode；And
High dielectric film layer structure as described in claim 1, between the top crown and the bottom crown.
6. capacitor arrangement according to claim 5, which is characterized in that the quantum tunnel inhibition layer is located at described laminated
Between formula dielectric structure and the bottom crown.
7. capacitor arrangement according to claim 5, which is characterized in that at least one section of the bottom crown be it is U-shaped,
The corresponding section of the high dielectric film layer structure and the top crown is M type, constitutes double sided capacitor structure.
8. a kind of preparation method of high dielectric film layer structure, which is characterized in that the high dielectric film layer structure is by N tunic
The structure that layer is constituted, wherein N is the integer more than or equal to 3, and the preparation method includes:
Form at least one layer of quantum tunnel inhibition layer；
At least one LAM type dielectric structure is formed, and the LAM type dielectric structure is including at least one layer of first dielectric layer and extremely
Few one layer of second dielectric layer, the forbidden bandwidth of second dielectric layer are greater than the forbidden bandwidth of first dielectric layer, and described
The unit thickness of second dielectric layer is less than or equal to the unit thickness of first dielectric layer；
Wherein, the dielectric constant of the quantum tunneling inhibition layer is greater than the dielectric constant of first dielectric layer and is greater than described the
The dielectric constant of two dielectric layers, first dielectric layer have the dielectric constant more than or equal to 10, and second dielectric layer has
Forbidden bandwidth more than or equal to 8, the high dielectric film layer structure with a thickness of 4~10nm, the quantum tunnel inhibition layer
With a thickness of 0.2~5nm, to provide enough physical thickness to limit quantum while keeping or reducing equivalent oxide thickness
Tunneling effect, the quantum tunnel inhibition layer are titanium dioxide layer, and the quantum tunnel inhibition layer attaches contacting capacitor structure
Bottom crown, the first dielectric layer of the bottom of the LAM type dielectric structure, which attaches, contacts the quantum tunnel inhibition layer；
Wherein, during the quantum tunneling inhibition layer and the LAM type dielectric structure are formed, in structure table to be processed
Face forms one layer of hydroxide ion layer, then, then is passed through the corresponding simple substance of oxide contained in institute's film layer to be formed, as
Precursor is reacted with the hydroxide ion layer, thus oxide membranous layer required for being formed.
9. the preparation method of high dielectric film layer structure according to claim 8, which is characterized in that formed by N tunic layer
Include the steps that being formed second layer film layer during the high dielectric film layer structure constituted to n-th layer film layer, specific step
Suddenly include:
One layer of hydroxide ion layer is formed in the upper surface of provided first layer film layer, and makes the hydroxide ion layer and institute
It states the corresponding simple substance of oxide contained by second layer film layer to be reacted, to form the second layer film layer；And
In be formed by N-1 tunic layer upper surface formed one layer of hydroxide ion layer, and make the hydroxide ion layer with
The corresponding simple substance of oxide contained by n-th layer film layer is reacted, to form n-th layer film layer.
10. the preparation method of high dielectric film layer structure according to claim 9, which is characterized in that form described second
During tunic layer and n-th layer film layer, process gas in zirconium, silicon, aluminium, niobium, hafnium and the constituted group of titanium extremely
Few one kind, process pressure are 0.1~2 support, and process temperatures are 200~400 DEG C.
11. the preparation method of high dielectric film layer structure according to claim 9, which is characterized in that form the hydrogen-oxygen
The method of radical ion layer includes: to be selected from one of vapor and ozone in reacting furnace to be passed through gas, and heated
Mode the structure of hydroxide ion layer to be formed is handled, in the upper of the structure of the hydroxide ion layer to be formed
Surface forms one layer of hydroxide ion layer.
12. a kind of preparation method of capacitor arrangement, which comprises the steps of:
1) bottom crown is provided；
2) one layer of hydroxide ion layer is formed in the bottom crown upper surface, makes the hydroxide ion layer and first layer film layer institute
The corresponding simple substance of the oxide contained is reacted, to form first layer film layer, wherein the first layer film layer includes the quantum
Tunnelling inhibition layer；
3) second layer is prepared to n-th layer film layer, with shape according to method according to claim 8 in the first layer film surface
At the high dielectric film layer structure being made of N tunic layer, wherein N is the integer more than or equal to 3；And
4) top crown is formed in the obtained body structure surface of step 3).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710520577.9A CN107316858B (en) | 2017-06-30 | 2017-06-30 | High dielectric film layer structure and its application and preparation method |
| CN201810415556.5A CN108538820B (en) | 2017-06-30 | 2017-06-30 | Capacitor arrangement and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710520577.9A CN107316858B (en) | 2017-06-30 | 2017-06-30 | High dielectric film layer structure and its application and preparation method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810415556.5A Division CN108538820B (en) | 2017-06-30 | 2017-06-30 | Capacitor arrangement and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107316858A CN107316858A (en) | 2017-11-03 |
| CN107316858B true CN107316858B (en) | 2018-12-14 |
Family
ID=60179820
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710520577.9A Active CN107316858B (en) | 2017-06-30 | 2017-06-30 | High dielectric film layer structure and its application and preparation method |
| CN201810415556.5A Active CN108538820B (en) | 2017-06-30 | 2017-06-30 | Capacitor arrangement and preparation method thereof |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810415556.5A Active CN108538820B (en) | 2017-06-30 | 2017-06-30 | Capacitor arrangement and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN107316858B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11049887B2 (en) * | 2017-11-10 | 2021-06-29 | Applied Materials, Inc. | Layer stack for display applications |
| CN108511425B (en) * | 2018-06-06 | 2023-07-04 | 长鑫存储技术有限公司 | Integrated circuit capacitor, method of manufacturing the same, and semiconductor device |
| US20210384197A1 (en) * | 2019-06-14 | 2021-12-09 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods of fabricating the same |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1469439A (en) * | 2002-07-20 | 2004-01-21 | ���ǵ�����ʽ���� | Deposition method for dielectric layer |
| CN1525562A (en) * | 2003-02-28 | 2004-09-01 | ��ʽ���綫֥ | Semiconductor device and method of manufacturing same |
| CN1828905A (en) * | 2005-01-07 | 2006-09-06 | 因芬尼昂技术股份公司 | DRAM with high K dielectric storage capacitor and method of making the same |
| CN103534807A (en) * | 2011-03-14 | 2014-01-22 | 英特尔公司 | Semiconductor structure having an integrated double-wall capacitor for embedded dynamic random access memory (EDRAM) and method to form the same |
| CN106356370A (en) * | 2015-07-13 | 2017-01-25 | 爱思开海力士有限公司 | Switched-capacitor dc-to-dc converters and methods of fabricating the same |
| CN106816434A (en) * | 2017-02-24 | 2017-06-09 | 合肥智聚集成电路有限公司 | High K dielectric film layer structure and its application and manufacture method |
-
2017
- 2017-06-30 CN CN201710520577.9A patent/CN107316858B/en active Active
- 2017-06-30 CN CN201810415556.5A patent/CN108538820B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1469439A (en) * | 2002-07-20 | 2004-01-21 | ���ǵ�����ʽ���� | Deposition method for dielectric layer |
| CN1525562A (en) * | 2003-02-28 | 2004-09-01 | ��ʽ���綫֥ | Semiconductor device and method of manufacturing same |
| CN1828905A (en) * | 2005-01-07 | 2006-09-06 | 因芬尼昂技术股份公司 | DRAM with high K dielectric storage capacitor and method of making the same |
| CN103534807A (en) * | 2011-03-14 | 2014-01-22 | 英特尔公司 | Semiconductor structure having an integrated double-wall capacitor for embedded dynamic random access memory (EDRAM) and method to form the same |
| CN106356370A (en) * | 2015-07-13 | 2017-01-25 | 爱思开海力士有限公司 | Switched-capacitor dc-to-dc converters and methods of fabricating the same |
| CN106816434A (en) * | 2017-02-24 | 2017-06-09 | 合肥智聚集成电路有限公司 | High K dielectric film layer structure and its application and manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108538820B (en) | 2019-05-10 |
| CN107316858A (en) | 2017-11-03 |
| CN108538820A (en) | 2018-09-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5094057B2 (en) | Capacitor manufacturing method for semiconductor device | |
| CN107316858B (en) | High dielectric film layer structure and its application and preparation method | |
| US20040141390A1 (en) | Capacitor of semiconductor device and method for manufacturing the same | |
| KR20000013654A (en) | Capacitor having an al2o3/aln mixed dielectric layer by using an atomic layer deposition and a manufacturing method thereof | |
| US8481384B2 (en) | Method for producing MIM capacitors with high K dielectric materials and non-noble electrodes | |
| US20070066012A1 (en) | Semiconductor device and method for fabricating the same | |
| CN108511424A (en) | Integrated-circuit capacitor and its manufacturing method, semiconductor devices | |
| US20170117282A1 (en) | DRAM Capacitors and Methods for Forming the Same | |
| CN111261774A (en) | Capacitor, method of manufacturing the same, and semiconductor device | |
| KR20110064269A (en) | Semiconductor device and method of fabricating the same, and semiconductor module, electronic circuit board and electronic system including the same | |
| US20110095396A1 (en) | Method and structure for silicon nanocrystal capacitor devices for integrated circuits | |
| KR100772099B1 (en) | Method for forming capacitor of semiconductor device | |
| KR100872876B1 (en) | Method for fabricating semiconductor device and semiconductor device fabricated thereby | |
| US20100164064A1 (en) | Capacitor and Method for Manufacturing the Same | |
| JP2009239047A (en) | Capacitor structure with zirconium nitride interface layer | |
| WO2010082605A1 (en) | Capacitor and process for manufacturing capacitor | |
| KR100596805B1 (en) | Method for forming capacitor of semiconductor device | |
| WO2012128960A1 (en) | Electrode treatments for enhanced dram performance | |
| KR100713906B1 (en) | Method for forming capacitor of semiconductor device | |
| CN106816434B (en) | High K dielectric film layer structure and its application and manufacturing method | |
| US11309383B1 (en) | Quad-layer high-k for metal-insulator-metal capacitors | |
| CN208225876U (en) | Integrated-circuit capacitor and semiconductor devices | |
| US10290700B2 (en) | Multilayer dielectric for metal-insulator-metal capacitor (MIMCAP) capacitance and leakage improvement | |
| CN111261775A (en) | Capacitor and method for manufacturing the same | |
| KR20090032971A (en) | Semiconductor device having insulating layer of cubic system or tetragonal system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20181008 Address after: 230601 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Applicant after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Applicant before: Ever power integrated circuit Co Ltd |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |