CN107302317B - The carrier wave implementation method of three-phase five-level inverter drain current suppressing - Google Patents

The carrier wave implementation method of three-phase five-level inverter drain current suppressing Download PDF

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CN107302317B
CN107302317B CN201710444049.XA CN201710444049A CN107302317B CN 107302317 B CN107302317 B CN 107302317B CN 201710444049 A CN201710444049 A CN 201710444049A CN 107302317 B CN107302317 B CN 107302317B
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CN107302317A (en
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王付胜
郑德佑
李祯
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Hefei University of Technology
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Hefei University of Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H02M1/123—Suppression of common mode voltage or current

Abstract

The invention discloses a kind of carrier wave implementation methods of three-phase five-level inverter drain current suppressing.Sampling three-phase raw modulation wave calculates intermediate zero-sequence component and excessive zero-sequence component according to its position, according to the size of intermediate zero-sequence component and excessive zero-sequence component, determines the zero-sequence component being superimposed needed for three-phase raw modulation wave.Three-phase raw modulation wave is added with zero-sequence component to obtain modulating wave among three-phase.Division zero-sequence component is calculated by modulating wave among three-phase and zero-sequence component.Three-phase is obtained by modulating wave among three-phase and division zero-sequence component and corrects modulating wave and three-phase division modulating wave.Three-phase is finally corrected into modulating wave and three-phase divides modulating wave compared with Three Phase Carrier Based, PWM wave is generated and controls five-electrical level inverter.The advantages that common-mode voltage is low, and striding capacitance voltage fluctuation is small, and leakage current is small may be implemented in the present invention；Due to being realized using carrier wave, realize that simply, control is convenient, is easily generalized in Practical Project.

Description

The carrier wave implementation method of three-phase five-level inverter drain current suppressing
Technical field
The present invention relates to photovoltaic technology field, more particularly to the carrier wave of a kind of three-phase five-level inverter drain current suppressing is real Existing method.
Background technology
Solar energy has the advantages that widely distributed, sustainable, free of contamination as a kind of regenerative resource.Photovoltaic generation skill Art is to efficiently use one of Basic Ways of solar energy resources.Currently, the various photovoltaic power generation technologies including grid-connected The support energetically of national governments is received.
In photovoltaic generating system, five-electrical level inverter has lower open for common three-level inverter Close loss and current ripples.It is identical with lower Current harmonic distortion rate in filter element.
Leakage current is always multi-electrical level inverter research and the emphasis and difficult point in design process, since photovoltaic array exists Direct-to-ground capacitance, high frequency common mode voltage act in parasitic capacitance, the resonance circuit that filter, electric network impedance and parasitic capacitance form Impedance very little, therefore the common mode current of high frequency, i.e. leakage current will be generated in not shielding system circuit.The presence of leakage current will drop The safety of low system, reliability easily cause electric shock and fire.And up to the present, rarely have patent and document to propose that this is asked The effective workaround of topic.
The size of leakage current is closely related with change frequency with common-mode voltage amplitude, and amplitude is bigger, and change frequency is higher, leakage Electric current is bigger, conversely, leakage current is smaller.
Five traditional level modulation strategies use space vector modulation (SVPWM), need first to carry out area to three dimensional vector diagram Domain divides, then calculates the action time of basic vector, will finally distribute to corresponding vector state action time, and process is complicated, Project Realization difficulty is big.
Document " A Novel SVPWM Algorithm for Five-Level Active Neutral-Neutral- point-Clamped Converter”,Zhan Liu,Yu Wang,Guojun Tan,Member IEEE,Hao Li,and Yunfeng Zhang,《IEEE Transactions on Power Electronics》,2016,31(5)3859-3866 (" a kind of research of the novel SVPWM control algolithms based on active neutral point clamp five-electrical level inverter ",《IEEE journals-electric power electricity Sub- periodical》, the 5th phase page 3859~3866 of volume 31 in 2016) and a kind of SVPWM algorithms of simplification are given, although greatly reducing Calculation amount, but it is still excessively cumbersome, there is certain realization difficulty, while the common-mode voltage amplitude of the modulation strategy is larger, reaches To total DC bus-bar voltage 1/6, change frequency is 6 times in a carrier cycle；On the other hand, leakage current is not also provided in text Inhibit the specific control program with striding capacitance balance；
Document " Capacitor Voltage Balancing of a Five-Level ANPC Converter UsingPhase-Shifted PWM ", Kui Wang, Member, IEEE, Lie Xu, Member, IEEE, Zedong Zheng, Member,IEEE,and Yongdong Li,Member,IEEE《IEEE Transactions on PowerElectronics》, 2015,30 (3), 1147-1156 (" the five level ANPC capacitances based on phase-shifting carrier wave modulator approach Voltage balancing control ",《IEEE journals-power electronics periodical》, the 3rd phase page 1147~1156 of volume 30 in 2015) and propose one The control method of the striding capacitance balance of voltage of the kind based on phase-shifting carrier wave, effectively realizes the balance control of striding capacitance voltage System, but common-mode voltage amplitude is identical with SVPWM, reaches the 1/6 of total DC bus-bar voltage, and change frequency is 6 times, is not also had in text Provide the specific control program of drain current suppressing；
Document " A novel SVPWM scheme for common-mode voltage reduction in five- Level active NPC inverters ", Quoc Anh Le, Member, IEEE, and Dong-Choon Lee, Member,IEEE,《2015 9th International Conference on Power Electronics and ECCE Asia(ICPE-ECCE Asia)》, 2015,281-287 (" a kind of five-level active clamp powder inverter common-mode voltage inhibits new Type SVPWM modulation strategies ",《9th Asia ICPE-ECCE international conference in 2015》, 2015 281-287 pages) propose one It is the 1/12 of total DC bus-bar voltage that kind common-mode voltage, which inhibits modulation strategy, suppression common mode voltage magnitude, and change frequency is 4 times, But still have certain optimization space, and the specific control program of drain current suppressing is not provided in text yet；
To sum up, existing five-electrical level inverter control still has following problem：
1) existing modulation algorithm common-mode voltage amplitude and change frequency are larger, and amplitude maximum is the 1/6 of DC bus-bar voltage, And change frequency is up to 6 times；
2) striding capacitance voltage balancing control difficulty is big；
3) analysis and effectively control are not carried out to system leakage current, and modulation strategy is realized using vector method, calculated Complexity is not easy Project Realization.
Invention content
The present invention is to solve the problems, such as the common-mode voltage, the striding capacitance balance of voltage and leakage current of five-electrical level inverter, is carried A kind of carrier wave implementation method of drain current suppressing is gone out, inverter can have been made in entire line by the modulator approach that carrier wave is laminated The amplitude of common-mode voltage is reduced to the 1/12 of total DC bus-bar voltage in sex work area, change frequency is reduced to 2 times, is realized and is flown It is controlled across the balance of capacitance, while ensureing the reduction of system leakage current, method is simple, is easy to engineer application.
The object of the present invention is achieved like this.The present invention provides a kind of three-phase five-level inverter drain current suppressings Carrier wave implementation method.
Topology is identical and for such as lower structure per circuitry phase for three-phase five-level inverter involved by this carrier wave implementation method：Directly Stream busbar total voltage is Vdc, DC side is provided with two concatenated capacitance C1With capacitance C2, capacitance C1Anode connection inverter input Anode, capacitance C1Cathode and capacitance C2Positive tie point is defined as inverter midpoint；Inverter includes 8 switching tubes per circuitry phase, That is switching tube Ski, i=1,2,3......8, k=a, b, c, wherein k indicate the three-phase circuit of inverter, i.e. a phases, b phases, c phases； Switching tube Sk1, switching tube Sk5, switching tube Sk7, switching tube Sk8, switching tube Sk6, switching tube Sk4It is in series, switching tube Sk1Emitter Connecting valve pipe Sk5Collector, switching tube Sk5Emitter connecting valve pipe Sk7Collector, switching tube Sk7Emitter connecting valve pipe Sk8Collector, switching tube Sk8Emitter connecting valve pipe Sk6Collector, switching tube Sk6Emitter connecting valve pipe Sk4Collector； Switching tube Sk1Collector connects capacitance C1Anode, switching tube Sk4Emitter connects capacitance C2Cathode, switching tube Sk7Collector with open Close pipe Sk8Emit interpolar parallel connection striding capacitance Cf, capacitance CfAnode and switching tube Sk7Collector is connected, switching tube Sk1Emitter with Paralleling switch pipe S between inverter midpointk2, switching tube Sk1Emitter and switching tube Sk2Collector be connected, switching tube Sk4Collector The paralleling switch pipe S between inverter midpointk3, switching tube Sk3Emitter and switching tube Sk4Collector is connected, switching tube Sk2Emitter With switching tube Sk3Collector is all connected with inverter midpoint；
This carrier wave implementation method includes the sampling to three-phase raw modulation wave, is included the following steps：
Step 1, sampling three-phase raw modulation wave Va、Vb、Vc, and according to three-phase raw modulation wave Va、Vb、VcPosition, meter Calculate intermediate zero-sequence component V01With excessive zero-sequence component V02, final to determine three-phase raw modulation wave Va、Vb、VcThe zero sequence of required superposition Component V0；
Region one：(0.66≤Va&&Vb≤-0.33&&Vc≤-0.33)||(0.33≤Va&&0.33≤Vb&&Vc≤- 0.66)||(Va≤-0.33&&0.66≤Vb&&Vc≤-0.33)||(Va≤-0.66&&0.33≤Vb&&0.33≤Vc)||(Va ≤-0.33&&Vb≤-0.33&&0.66≤Vc)||(0.33≤Va&&Vb≤-0.66&&0.33≤Vc)
Region two：Region other than region one,
Wherein, VmaxFor three-phase raw modulation wave Va、Vb、VcIn maximum value, VminFor three-phase raw modulation wave Va、Vb、Vc In minimum value, VmidFor three-phase raw modulation wave Va、Vb、VcIn median , ＆＆ indicate and operation, | | indicate or operation；
Step 2, superposition zero-sequence component V0Obtain modulating wave V among three-phasea *、Vb *、Vc *；
Va *=Va+V0, Vb *=Vb+V0, Vc *=Vc+V0；
Step 3, division zero-sequence component △ V are calculated according to step 1 subregion；
Region one：If V0=V01,
△ V=Vmax1+Vmin1,
If V0=V02,
Region two：
△ V=0,
Wherein, Vmax1For modulating wave V among three-phasea *、Vb *、Vc *In maximum value, Vmin1For modulating wave V among three-phasea *、 Vb *、Vc *In minimum value, Vmid1For modulating wave V among three-phasea *、Vb *、Vc *In median；
Step 4, superposition division zero-sequence component △ V obtain three-phase and correct modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc", superposition principle is as follows：
When | Vmax1|>|Vmin1|, if Vmin1For Va *, then Va'=Va *- △ V, Vb'=Vb *, Vc'=Vc *, Va"=△ V, Vb” =0, Vc"=0；If Vmin1For Vb *, then Va'=Va *, Vb'=Vb *- △ V, Vc'=Vc *, Va"=0, Vb"=△ V, Vc"=0；If Vmin1For Vc *, then Va'=Va *, Vb'=Vb *, Vc'=Vc *- △ V, Va"=0, Vb"=0, Vc"=△ V；
When | Vmax1|≤|Vmin1|, if Vmax1For Va *, then Va'=Va *- △ V, Vb'=Vb *, Vc'=Vc *, Va"=△ V, Vb” =0, Vc"=0；If Vmax1For Vb *, then Va'=Va *, Vb'=Vb *- △ V, Vc'=Vc *, Va"=0, Vb"=△ V, Vc"=0；If Vmax1For Vc *, then Va'=Va *, Vb'=Vb *, Vc'=Vc *- △ V, Va"=0, Vb"=0, Vc"=△ V；
Step 5, three-phase is corrected into modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc" compared with carrier wave, It generates PWM wave and controls inverter；Specifically include following steps：
1) Three Phase Carrier Based phase is determined；
The carrier wave is the triangular carrier of four stackings, is defined as follows with range：
One Tri of carrier wavek1, ranging from [- 1, -0.5)；Two Tri of carrier wavek2, ranging from [- 0.5,0)；Three Tri of carrier wavek3, range For [0,0.5)；Four Tri of carrier wavek4, range [0.5,1]；Five Tri of carrier wavek5, ranging from [- 1, -0.5)；Six Tri of carrier wavek6, range For [- 0.5,0)；K=a, b, c；
Wherein, Trik1、Trik2、Trik5、Trik6Phase is identical, Trik3、Trik4Phase is identical, Trik1、Trik3Phase phase Poor 180 °；
2) two adjacent carrier cycles are set and are divided into one group, first carrier cycle in every group is defined as T1, second A carrier cycle is defined as T2；1 indicates that switching tube is open-minded, and 0 indicates switching tube shutdown；
3) three-phase is corrected into modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc" it is expressed as Vk' and Vk", k =a, b, c；
4) by Vk'、Vk" be compared with carrier wave, and generate following pwm signal control inverter：
As 0.5≤VkWhen '≤1, work as Vk'≥Trik4When, K phase pwm signals PWMk=1, work as Vk'<Trik4When, PWMk=0；
As 0≤Vk'<When 0.5, work as Vk'≥Trik3When, K phase pwm signals PWMk=1, work as Vk'<Trik3When, PWMk=0；
As -0.5≤Vk'<When 0, work as Vk'≥Trik2When, K phase pwm signals PWMk=1, work as Vk'<Trik2When, PWMk=0；
As -1≤Vk'<When -0.5, work as Vk'≥Trik1When, K phase pwm signals PWMk=1, work as Vk'<Trik1When, PWMk=0；
As 0.5≤VkWhen "≤1, work as Vk”≥Trik4When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik4When, PWMFLk=0；
As 0≤Vk”<When 0.5, work as Vk”≥Trik3When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik3When, PWMFLk=0；
As -0.5≤Vk”<When 0, work as Vk”≥Trik6When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik6When, PWMFLk=0；
As -1≤Vk”<When -0.5, work as Vk”≥Trik5When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik5When, PWMFLk=0；
K phase drive signals Dk=PWMk⊙PWMFLk, wherein ⊙ indicate with or operation；
Work as VkWhen ' >=0, switching tube Sk1, Sk3It is always 1, Sk2, Sk4It is always 0；Work as Vk'<When 0, switching tube Sk1, Sk3Always It is 0, Sk2, Sk4It is always 1；
As 0.5≤VkWhen '≤1, in T1It is interior, Sk5It is always 1, Sk6It is always 0, Sk7For Dk, Sk8For (1-Dk)；In T2It is interior, Sk7It is always 1, Sk8It is always 0, Sk5For Dk, Sk6For (1-Dk)；
As 0≤Vk'<When 0.5, in T1It is interior, Sk7It is always 0, Sk8It is always 1, Sk5For Dk, Sk6For (1-Dk), in T2It is interior, Sk5 It is always 0, Sk6It is always 1, Sk7For Dk, Sk8For (1-Dk)；
As -0.5≤Vk'<When 0, in T1It is interior, Sk5It is always 1, Sk6It is always 0, Sk7For Dk, Sk8For (1-Dk)；In T2It is interior, Sk7It is always 1, Sk8It is always 0, Sk5For Dk, Sk6For (1-Dk)；
As -1≤Vk'<When -0.5, in T1It is interior, Sk7It is always 0, Sk8It is always 1, Sk5For Dk, Sk6For (1-Dk)；In T2It is interior, Sk5It is always 0, Sk6It is always 1, Sk7For Dk, Sk8For (1-Dk)。
Compared with the existing technology, beneficial effects of the present invention are as follows：
1, it is the 1/12 of DC bus-bar voltage effectively to inhibit the common-mode voltage amplitude of five-electrical level inverter, and change frequency It is 2 times, improves the reliability of system；
2, the balance control of striding capacitance voltage is realized；
3, it using multi-carrier modulation scheme, realizes simply, is easy to engineer application and reduces the leakage current of system.
Description of the drawings：
Fig. 1 is the carrier wave implementation method flow diagram of drain current suppressing proposed by the present invention.
Fig. 2 is the single-phase topological diagram of five-electrical level inverter according to the present invention.
Fig. 3 is three-phase middle tone of the carrier wave implementation method of drain current suppressing proposed by the present invention when modulation degree is 0.8 Wave V processedk *Oscillogram.Wherein, 3a is modulating wave oscillogram among A phases, and 3b is modulating wave oscillogram among B phases, and 3c is among C phases Modulating wave oscillogram.
Fig. 4 is three-phase amendment tune of the carrier wave implementation method of drain current suppressing proposed by the present invention when modulation degree is 0.8 Wave V processedk' and three-phase division modulating wave Vk" oscillogram, wherein 4a is that A phases correct modulating wave and division modulating wave oscillogram, thereon Figure is that A phases correct modulating wave oscillogram, and figure below is that A phases divide modulating wave oscillogram；4b is that B phases correct modulating wave and division is modulated Wave oscillogram, figure is that B phases correct modulating wave oscillogram thereon, and figure below is that B phases divide modulating wave oscillogram；4c is that C phases correct tune Wave processed and division modulating wave oscillogram, figure is that C phases correct modulating wave oscillogram thereon, and figure below is that C phases divide modulating wave oscillogram.
Fig. 5 is striding capacitance electricity of the carrier wave implementation method of drain current suppressing proposed by the present invention when modulation degree is 0.8 Pressure figure.
Specific implementation mode
Three-phase five-level inverter according to the present invention is identical per circuitry phase topology, and single-phase topological diagram is as shown in Figure 2. DC bus total voltage is Vdc, DC side is provided with two concatenated capacitance C1With capacitance C2, capacitance C1Anode connection inverter is defeated Enter anode, capacitance C1Cathode and capacitance C2Positive tie point is defined as inverter midpoint；It is opened comprising 8 in the every circuitry phase of inverter Guan Guan, i.e. switching tube Ski, the three-phase circuit of i=1,2,3......8, k=a, b, c, wherein k expression inverter, i.e. a phases, b phases, C phases；Switching tube Sk1, switching tube Sk5, switching tube Sk7, switching tube Sk8, switching tube Sk6, switching tube Sk4It is in series, switching tube Sk1Hair Emitter-base bandgap grading connecting valve pipe Sk5Collector, switching tube Sk5Emitter connecting valve pipe Sk7Collector, switching tube Sk7Emitter connection is opened Close pipe Sk8Collector, switching tube Sk8Emitter connecting valve pipe Sk6Collector, switching tube Sk6Emitter connecting valve pipe Sk4Collection Electrode；Switching tube Sk1Collector connects capacitance C1Anode, switching tube Sk4Emitter connects capacitance C2Cathode, switching tube Sk7Collector With switching tube Sk8Emit interpolar parallel connection striding capacitance Cf, capacitance CfAnode and switching tube Sk7Collector is connected, switching tube Sk1Transmitting Paralleling switch pipe S between pole and inverter midpointk2, switching tube Sk1Emitter and switching tube Sk2Collector be connected, switching tube Sk4Collection Paralleling switch pipe S between electrode and inverter midpointk3, switching tube Sk3Emitter and switching tube Sk4Collector is connected, switching tube Sk2Hair Emitter-base bandgap grading and switching tube Sk3Collector is all connected with inverter midpoint.
The flow chart of this carrier wave implementation method such as Fig. 1.Implementation method includes the sampling to three-phase raw modulation wave, feature It is to include the following steps：
Step 1, sampling three-phase raw modulation wave Va、Vb、Vc, and according to three-phase raw modulation wave Va、Vb、VcPosition, meter Calculate intermediate zero-sequence component V01With excessive zero-sequence component V02, final to determine three-phase raw modulation wave Va、Vb、VcThe zero sequence of required superposition Component V0。
Region one：(0.66≤Va&&Vb≤-0.33&&Vc≤-0.33)||(0.33≤Va&&0.33≤Vb&&Vc≤- 0.66)||(Va≤-0.33&&0.66≤Vb&&Vc≤-0.33)||(Va≤-0.66&&0.33≤Vb&&0.33≤Vc)||(Va ≤-0.33&&Vb≤-0.33&&0.66≤Vc)||(0.33≤Va&&Vb≤-0.66&&0.33≤Vc),
Region two：Region other than region one,
Wherein, VmaxFor three-phase raw modulation wave Va、Vb、VcIn maximum value, VminFor three-phase raw modulation wave Va、Vb、Vc In minimum value, VmidFor three-phase raw modulation wave Va、Vb、VcIn median , ＆＆ indicate and operation, | | indicate or operation.
Step 2, superposition zero-sequence component V0Obtain modulating wave V among three-phasea *、Vb *、Vc *。
Va *=Va+V0, Vb *=Vb+V0, Vc *=Vc+V0
Modulating wave V among three-phase when modulation degree is 0.8k *Waveform is as shown in Figure 3.Wherein, 3a is modulating wave wave among A phases Shape figure, 3b are modulating wave oscillograms among B phases, and 3c is modulating wave oscillogram among C phases.
Step 3, division zero-sequence component △ V are calculated according to step 1 subregion.
Region one：If V0=V01,
△ V=Vmax1+Vmin1
If V0=V02
Region two：
△ V=0,
Wherein, Vmax1For modulating wave V among three-phasea *、Vb *、Vc *In maximum value, Vmin1For modulating wave V among three-phasea *、 Vb *、Vc *In minimum value, Vmid1For modulating wave V among three-phasea *、Vb *、Vc *In median.
Step 4, superposition division zero-sequence component △ V obtain three-phase and correct modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc", superposition principle is as follows：
When | Vmax1|>|Vmin1|, if Vmin1For Va *, then Va'=Va *- △ V, Vb'=Vb *, Vc'=Vc *, Va"=△ V, Vb” =0, Vc"=0；If Vmin1For Vb *, then Va'=Va *, Vb'=Vb *- △ V, Vc'=Vc *, Va"=0, Vb"=△ V, Vc"=0；If Vmin1For Vc *, then Va'=Va *, Vb'=Vb *, Vc'=Vc *- △ V, Va"=0, Vb"=0, Vc"=△ V；
When | Vmax1|≤|Vmin1|, if Vmax1For Va *, then Va'=Va *- △ V, Vb'=Vb *, Vc'=Vc *, Va"=△ V, Vb” =0, Vc"=0；If Vmax1For Vb *, then Va'=Va *, Vb'=Vb *- △ V, Vc'=Vc *, Va"=0, Vb"=△ V, Vc"=0；If Vmax1For Vc *, then Va'=Va *, Vb'=Vb *, Vc'=Vc *- △ V, Va"=0, Vb"=0, Vc"=△ V；
Three-phase when modulation degree is 0.8 corrects modulating wave Vk' and three-phase division modulating wave Vk" waveform is as shown in Figure 4.Wherein, 4a is that A phases correct modulating wave and division modulating wave oscillogram, and figure is that A phases correct modulating wave oscillogram thereon, and figure below is that A phases divide Modulating wave oscillogram；4b is that B phases correct modulating wave and division modulating wave oscillogram, and figure is that B phases correct modulating wave oscillogram thereon, Figure below is that B phases divide modulating wave oscillogram；4c is that C phases correct modulating wave and division modulating wave oscillogram, and figure is that C phases are corrected thereon Modulating wave oscillogram, figure below are that C phases divide modulating wave oscillogram.
Step 5, three-phase is corrected into modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc" compared with carrier wave, It generates PWM wave and controls inverter；Specifically include following steps：
1) Three Phase Carrier Based phase is determined；
The carrier wave is the triangular carrier of four stackings, is defined as follows with range：
One Tri of carrier wavek1, ranging from [- 1, -0.5)；Two Tri of carrier wavek2, ranging from [- 0.5,0)；Three Tri of carrier wavek3, range For [0,0.5)；Four Tri of carrier wavek4, range [0.5,1]；Five Tri of carrier wavek5, ranging from [- 1, -0.5)；Six Tri of carrier wavek6, range For [- 0.5,0)；K=a, b, c；
Wherein, Trik1、Trik2、Trik5、Trik6Phase is identical, Trik3、Trik4Phase is identical, Trik1、Trik3Phase phase Poor 180 °；
2) two adjacent carrier cycles are set and are divided into one group, first carrier cycle in every group is defined as T1, second A carrier cycle is defined as T2；1 indicates that switching tube is open-minded, and 0 indicates switching tube shutdown；
2) three-phase is corrected into modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc" it is expressed as Vk' and Vk", k =a, b, c；
3) by Vk'、Vk" be compared with carrier wave, and generate following PWM wave control inverter：
As 0.5≤VkWhen '≤1, work as Vk'≥Trik4When, K phase pwm signals PWMk=1, work as Vk'<Trik4When, PWMk=0；
As 0≤Vk'<When 0.5, work as Vk'≥Trik3When, K phase pwm signals PWMk=1, work as Vk'<Trik3When, PWMk=0；
As -0.5≤Vk'<When 0, work as Vk'≥Trik2When, K phase pwm signals PWMk=1, work as Vk'<Trik2When, PWMk=0；
As -1≤Vk'<When -0.5, work as Vk'≥Trik1When, K phase pwm signals PWMk=1, work as Vk'<Trik1When, PWMk=0；
As 0.5≤VkWhen "≤1, work as Vk”≥Trik4When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik4When, PWMFLk=0；
As 0≤Vk”<When 0.5, work as Vk”≥Trik3When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik3When, PWMFLk=0；
As -0.5≤Vk”<When 0, work as Vk”≥Trik6When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik6When, PWMFLk=0；
As -1≤Vk”<When -0.5, work as Vk”≥Trik5When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik5When, PWMFLk=0；
K phase drive signals Dk=PWMk⊙PWMFLk, wherein ⊙ indicate with or operation.
Work as VkWhen ' >=0, switching tube Sk1, Sk3It is always 1, Sk2, Sk4It is always 0；Work as Vk'<When 0, switching tube Sk1, Sk3Always It is 0, Sk2, Sk4It is always 1；
As 0.5≤VkWhen '≤1, in T1It is interior, Sk5It is always 1, Sk6It is always 0, Sk7For Dk, Sk8For (1-Dk)；In T2It is interior, Sk7It is always 1, Sk8It is always 0, Sk5For Dk, Sk6For (1-Dk)；
As 0≤Vk'<When 0.5, in T1It is interior, Sk7It is always 0, Sk8It is always 1, Sk5For Dk, Sk6For (1-Dk), in T2It is interior, Sk5 It is always 0, Sk6It is always 1, Sk7For Dk, Sk8For (1-Dk)；
As -0.5≤Vk'<When 0, in T1It is interior, Sk5It is always 1, Sk6It is always 0, Sk7For Dk, Sk8For (1-Dk)；In T2It is interior, Sk7It is always 1, Sk8It is always 0, Sk5For Dk, Sk6For (1-Dk)；
As -1≤Vk'<When -0.5, in T1It is interior, Sk7It is always 0, Sk8It is always 1, Sk5For Dk, Sk6For (1-Dk)；In T2It is interior, Sk5It is always 0, Sk6It is always 1, Sk7For Dk, Sk8For (1-Dk)。
The MATLAB/Sinmulink simulation models of three-phase five-level inverter have been built according to algorithm proposed by the present invention, Emulation uses passive inverter, circuit parameter：Load R=10 Ω, L=1.5mH, switching frequency fc=10kHz, DC voltage Vdc= 200V, dc-link capacitance Cdc1=Cdc2=2000uF, striding capacitance Cf=1500uF, frequency of modulated wave fr=50Hz.
It in MATLAB/Sinmulink, writes S-Function and realizes algorithm proposed by the present invention, pass through system .m texts The carrier wave implementation method of drain current suppressing proposed by the present invention is verified in the operation of part, it is found that and first, it is modulating When degree is 0.8, phase-shifting carrier wave method and SVPWM common-mode voltage amplitudes areAnd amplitude changes 6 times in a carrier cycle, altogether Mode voltage inhibit modulation common-mode voltage amplitude beAmplitude changes 4 times, and the common-mode voltage amplitude of withdrawn deposit method herein ForAmplitude only changes 2 times；Second, the carried implementation method of the present invention is with the obvious advantage in terms of drain current suppressing, stream peak of leaking electricity Peak value is only 80mA.
Fig. 5 is striding capacitance electricity of the carrier wave implementation method of drain current suppressing proposed by the present invention when modulation degree is 0.8 Pressure figure, fluctuation peak-to-peak value are 1.2V, only the 2.5% of average value.

Claims (1)

1. a kind of carrier wave implementation method of three-phase five-level inverter drain current suppressing, the three-phase involved by this carrier wave implementation method Topology is identical and for such as lower structure per circuitry phase for five-electrical level inverter：DC bus total voltage is Vdc, DC side is provided with two Concatenated capacitance C1With capacitance C2, capacitance C1Anode connection inverter input anode, capacitance C1Cathode and capacitance C2Positive tie point It is defined as inverter midpoint；Inverter includes 8 switching tubes, i.e. switching tube S per circuitry phaseki, i=1,2,3......8, (k= A, b, c), wherein k indicates the three-phase circuit of inverter, i.e. a phases, b phases, c phases；Switching tube Sk1, switching tube Sk5, switching tube Sk7, open Close pipe Sk8, switching tube Sk6, switching tube Sk4It is in series, switching tube Sk1Emitter connecting valve pipe Sk5Collector, switching tube Sk5Hair Emitter-base bandgap grading connecting valve pipe Sk7Collector, switching tube Sk7Emitter connecting valve pipe Sk8Collector, switching tube Sk8Emitter connection is opened Close pipe Sk6Collector, switching tube Sk6Emitter connecting valve pipe Sk4Collector；Switching tube Sk1Collector connects capacitance C1Anode, Switching tube Sk4Emitter connects capacitance C2Cathode, switching tube Sk7Collector and switching tube Sk8Emit interpolar parallel connection striding capacitance Cf, Capacitance CfAnode and switching tube Sk7Collector is connected, switching tube Sk1Paralleling switch pipe S between emitter and inverter midpointk2, switch Pipe Sk1Emitter and switching tube Sk2Collector be connected, switching tube Sk4Paralleling switch pipe S between collector and inverter midpointk3, open Close pipe Sk3Emitter and switching tube Sk4Collector is connected, switching tube Sk2Emitter and switching tube Sk3Collector all in inverter Point is connected；
This carrier wave implementation method includes the sampling to three-phase raw modulation wave, which is characterized in that is included the following steps：
Step 1, sampling three-phase raw modulation wave Va、Vb、Vc, and according to three-phase raw modulation wave Va、Vb、VcPosition, in calculating Between zero-sequence component V01With transition zero-sequence component V02, final to determine three-phase raw modulation wave Va、Vb、VcThe zero-sequence component of required superposition V0；
Region one：(0.66≤Va&&Vb≤-0.33&&Vc≤-0.33)||(0.33≤Va&&0.33≤Vb&&Vc≤-0.66)|| (Va≤-0.33&&0.66≤Vb&&Vc≤-0.33)||(Va≤-0.66&&0.33≤Vb&&0.33≤Vc)||(Va≤-0.33&& Vb≤-0.33&&0.66≤Vc)||(0.33≤Va&&Vb≤-0.66&&0.33≤Vc),
Region two：Region other than region one,
Wherein, VmaxFor three-phase raw modulation wave Va、Vb、VcIn maximum value, VminFor three-phase raw modulation wave Va、Vb、VcIn Minimum value, VmidFor three-phase raw modulation wave Va、Vb、VcIn median , ＆＆ indicate and operation, | | indicate or operation；
Step 2, superposition zero-sequence component V0Obtain modulating wave V among three-phasea *、Vb *、Vc *,
Va *=Va+V0, Vb *=Vb+V0, Vc *=Vc+V0；
Step 3, division zero-sequence component △ V are calculated according to step 1 subregion,
Region one：If V0=V01,
△ V=Vmax1+Vmin1,
If V0=V02,
Region two：
△ V=0,
Wherein, Vmax1For modulating wave V among three-phasea *、Vb *、Vc *In maximum value, Vmin1For modulating wave V among three-phasea *、Vb *、Vc * In minimum value, Vmid1For modulating wave V among three-phasea *、Vb *、Vc *In median；
Step 4, superposition division zero-sequence component △ V obtain three-phase and correct modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、 Vb”、Vc", superposition principle is as follows：
When | Vmax1|>|Vmin1|, if Vmin1For Va *, then Va'=Va *- △ V, Vb'=Vb *, Vc'=Vc *, Va"=△ V, Vb"=0, Vc"=0；If Vmin1For Vb *, then Va'=Va *, Vb'=Vb *- △ V, Vc'=Vc *, Va"=0, Vb"=△ V, Vc"=0；If Vmin1For Vc *, then Va'=Va *, Vb'=Vb *, Vc'=Vc *- △ V, Va"=0, Vb"=0, Vc"=△ V；
When | Vmax1|≤|Vmin1|, if Vmax1For Va *, then Va'=Va *- △ V, Vb'=Vb *, Vc'=Vc *, Va"=△ V, Vb"=0, Vc"=0；If Vmax1For Vb *, then Va'=Va *, Vb'=Vb *- △ V, Vc'=Vc *, Va"=0, Vb"=△ V, Vc"=0；If Vmax1For Vc *, then Va'=Va *, Vb'=Vb *, Vc'=Vc *- △ V, Va"=0, Vb"=0, Vc"=△ V；
Step 5, three-phase is corrected into modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc" compared with carrier wave, it generates PWM wave controls inverter；Specifically comprise the following steps：
1) Three Phase Carrier Based phase is determined；
The carrier wave is the triangular carrier of four stackings, is defined as follows with range：
One Tri of carrier wavek1, ranging from [- 1, -0.5)；Two Tri of carrier wavek2, ranging from [- 0.5,0)；Three Tri of carrier wavek3, ranging from [0,0.5)；Four Tri of carrier wavek4, range [0.5,1]；(k=a, b, c)；
Wherein, Trik1、Trik2Phase is identical, Trik3、Trik4Phase is identical, Trik1、Trik3Phase differs 180 °；
2) two adjacent carrier cycles are set and are divided into one group, first carrier cycle in every group is defined as T1, second carrier wave Period definition is T2；1 indicates that switching tube is open-minded, and 0 indicates switching tube shutdown；
3) three-phase is corrected into modulating wave Va'、Vb'、Vc' and three-phase division modulating wave Va”、Vb”、Vc" it is expressed as Vk' and Vik" ', (k =a, b, c)；
4) by Vk'、Vk" be compared with carrier wave, and generate following pwm signal control inverter：
As 0.5≤VkWhen '≤1, work as Vk'≥Trik4When, K phase pwm signals PWMk=1, work as Vk'<Trik4When, PWMk=0；
As 0≤Vk'<When 0.5, work as Vk'≥Trik3When, K phase pwm signals PWMk=1, work as Vk'<Trik3When, PWMk=0；
As -0.5≤Vk'<When 0, work as Vk'≥Trik2When, K phase pwm signals PWMk=1, work as Vk'<Trik2When, PWMk=0；
As -1≤Vk'<When -0.5, work as Vk'≥Trik1When, K phase pwm signals PWMk=1, work as Vk'<Trik1When, PWMk=0；
As 0.5≤VkWhen "≤1, work as Vk”≥Trik4When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik4When, PWMFLk =0；
As 0≤Vk”<When 0.5, work as Vk”≥Trik3When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik3When, PWMFLk= 0；
As -0.5≤Vk”<When 0, work as Vk”≥Trik2When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik2When, PWMFLk =0；
As -1≤Vk”<When -0.5, work as Vk”≥Trik1When, K phase PWM heading signals PWMFLk=1, work as Vk”<Trik1When, PWMFLk =0；
K phase drive signals Dk=PWMk⊙PWMFLk, wherein ⊙ indicate with or operation；
Work as VkWhen ' >=0, switching tube Sk1, Sk3It is always 1, Sk2, Sk4It is always 0；Work as Vk'<When 0, switching tube Sk1, Sk3It is always 0, Sk2, Sk4It is always 1；
As 0.5≤VkWhen '≤1, in T1It is interior, Sk5It is always 1, Sk6It is always 0, Sk7For Dk, Sk8For (1-Dk)；In T2It is interior, Sk7Begin It is 1, S eventuallyk8It is always 0, Sk5For Dk, Sk6For (1-Dk)；
As 0≤Vk'<When 0.5, in T1It is interior, Sk7It is always 0, Sk8It is always 1, Sk5For Dk, Sk6For (1-Dk), in T2It is interior, Sk5Always It is 0, Sk6It is always 1, Sk7For Dk, Sk8For (1-Dk)；
As -0.5≤Vk'<When 0, in T1It is interior, Sk5It is always 1, Sk6It is always 0, Sk7For Dk, Sk8For (1-Dk)；In T2It is interior, Sk7Begin It is 1, S eventuallyk8It is always 0, Sk5For Dk, Sk6For (1-Dk)；
As -1≤Vk'<When -0.5, in T1It is interior, Sk7It is always 0, Sk8It is always 1, Sk5For Dk, Sk6For (1-Dk)；In T2It is interior, Sk5Begin It is 0, S eventuallyk6It is always 1, Sk7For Dk, Sk8For (1-Dk)。
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