CN1073020A - Interface circuit for numeric code converting timer control - Google Patents
Interface circuit for numeric code converting timer control Download PDFInfo
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- CN1073020A CN1073020A CN 91111346 CN91111346A CN1073020A CN 1073020 A CN1073020 A CN 1073020A CN 91111346 CN91111346 CN 91111346 CN 91111346 A CN91111346 A CN 91111346A CN 1073020 A CN1073020 A CN 1073020A
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Abstract
The invention relates to interface circuit for numeric code converting timer control.It comprises by amplifying, separating deposit, gating, coding are ternary drives circuit such as output, control, second signal output and 27 external connection end are formed.This interface circuit can directly link with various pairs of public electrode liquid crystal display formula electronic watch core circuits and all kinds of circuit thereof, convert clock signal amplification, field separation, four figures to the DCL current potential simultaneously, and have ternary controlled serial binary-coded decimal output, thereby constitute various real-time TT﹠C system.This interface circuit can be made into the special-purpose integrated package of standard biserial 28 pin encapsulation, reaches integrated, miniaturization.
Description
The invention relates to interface circuit for numeric code converting timer control, be specially adapted to liquid crystal display formula quartz watch as signal source of clock and then convert binary-coded decimal to through this interface circuit and remove to control other circuit or electrical equipment.
In some tests and control system, promptly need the data of record measurement automatically, also need to note the time relevant, with the corresponding system of in good time control with these data.The method that realizes in good time clock has multiple, adopts timer as time reference usually, cooperates the corresponding software of a cover to form real-time clock, and this is known as soft clock.For example: constitute the clock of electronic watch calendar day function with single-chip microcomputer, but will take a large amount of CPU time, program is complicated (being about 2KB) also.What be made of hardware is hardware clock, for example: MS M
5832, DS
1216Deng, though hardware clock is better than soft clock, the read-write operation complexity, the access speed that has is slower, when displaying calendar, time, also need mix keyboard-display circuit and corresponding program.
The liquid crystal digital show quartz electronic watches is a kind of high precision, low-power consumption, long-life, multi-functional, simple in structure, cheap all electronic wrist-watch.With time control, mostly be the control of once presetting, electronic watch, bell-controlling radio when making a noise.But because the restriction of structure, quartz watch is to be difficult to directly and the coupling mutually of all kinds of control system.To go to control sorts of systems as signal source of clock with electronic watch, just the electronic watch clock data must be converted to the number of standard.Prior art generally is to take directly to take from liquid crystal (LCD) field signal, and to each field signal an amplifying circuit amplification need be set all, subsequently again through field-BCD scrambler (for example: C
308, SC
278, BH
1308, CH
294Deng) change.But every scrambler can only be changed a bit clock number, just needs four scramblers as changing four calendars, clock data, also will add 20 cover amplifying circuits.So, not only volume is big, adds that element is many, cost is high, does not have what practical value.Bigger deficiency is, the liquid crystal display formula electronic watch core circuit of single public electrode that above-mentioned prior art can only land used early stage (backwardnesss), and can not be used for the liquid crystal display formula electronic watch core circuit with two public electrodes of the existing replacement at all.
For this reason, purpose of the present invention just is: one, design a kind of interface circuit for numeric code converting timer control that can convert four bit clock signals of the liquid crystal display formula quartz watch of two public electrodes simultaneously to controlled ternary binary-coded decimal output.Its two, this interface circuit should be able to link with all kinds of digital circuits or with microcomputer bus easily, to form the TT﹠C system of various difference in functionality effects.Its three, this interface circuit should be able to directly link with the quartz electronic watch core circuit of the liquid crystal display formula of two public electrodes.
The technical solution of interface circuit for numeric code converting timer control of the present invention includes: amplifying circuit, separate and to post (lock) and deposit ternary output circuit and control circuit, the second signal output apparatus that drives of circuit, gating circuit, coding, and with joining 27 external connection end of external circuit.This interface circuit is that a kind of clock signal to two public electrode liquid crystal display formula electronic watch core circuits is carried out: signal amplifies, field is separated, four figures while binary-coded decimal is changed, controlled ternary binary-coded decimal output, realize that the clock AC signal converts the DCL current potential to, and by 27 external connection end directly and electronic watch core circuit and all kinds of circuit link and constitute the interface circuit of various in good time TT﹠C system.Wherein:
1, amplifying circuit comprises by 16 input resistance [R
1～R
16] and 16 operational amplifier [I that play amplifications
1-1～I
1-16] 16 in-phase amplifiers constituting.This amplifying circuit can be amplified to the various signals that are taken from each drive output output of electronic watch core circuit by the input end input cmos circuit that is enough to promote in the next stage separation register circuit and change required logic current potential.
2, separate and to post (lock) and deposit circuit, according to liquid crystal (LCD) displaying principle: when the phase place of public electrode (being connected on the LCD back electrode) and field signal was opposite, then this field was with regard to demonstration; Otherwise when the phase place of public electrode and field signal was identical, this field did not then show.For the electronic watch core circuit that two public electrodes are arranged, each drive output on the watch core circuit is all controlled two fields, and two public electrodes communicate with two corresponding LCD back electrodes of field respectively.When the signal of drive output made the phase place of field and corresponding LCD back electrode opposite, pairing field just showed, if when the phase place of 2 fields is all identical with corresponding LCD back electrode phase place, then 2 fields do not show.Otherwise then all show.Principle design goes out separation register circuit of the present invention and comprises 22 XOR gate [I in view of the above
2-1～I
2-22] separation circuit that constitutes and by the ternary register [I of 6 four D types
3-1～I
3-6] register circuit that constitutes forms.Like this, behind this separation register circuit, promptly be convertible into corresponding logic current potential output by the interchange field shows signal of sending here after the amplifying circuit amplification.That is to say: when the input of the input end of amplifying circuit be when the signal that field shows is arranged, to handle the logic current potential of exporting the back be " 1 " through separating, depositing; Otherwise, when the input of the input end of amplifying circuit be no field show signal the time, be " 0 " through separating, deposit the logic current potential of exporting after handling.In like manner, the signal that the separation register circuit can show the various field that each drive output of electronic watch core circuit is sent here is handled, the conversion of signals that " having " or " nothing " field is shown becomes corresponding logic current potential " 1 " or " 0 ", converts the DCL current potential to thereby reach the AC signal that the field by each drive output output of electronic watch core circuit is shown.
3, gating circuit (referring to Fig. 8,9,10): because the quartz electronic watch core circuit of liquid crystal display formula has desk calendar type (A type), the noisy type (Type B) of platform and hangs to make a noise and go through the movement of three kinds of forms of type (C type), this A, B, three kinds of movements of C all have the lead-in wire of 2 public electrodes lead-in wires and 11 to 14 fields (combination).Because every decimal numeral field symbols (referring to Fig. 7) is formed by 7 fields " a, b, c, d, e, f, g ", wherein field " b, c, f, e " is combined on A, B, three kinds of movements of C all the same, therefore the signal that " having " or " nothing " field of these fields can be shown is deposited conversion output through separation, field b, f, the e(logic current potential of representative on corresponding output port) remain unchanged.And field " a, d, g " is combined in A, B, three kinds of movements of C are different ground, therefore the signal of " having " or " nothing " field of these fields demonstration is changed output after separation is deposited, field a, d, the g(logic current potential of representative on corresponding output port) change, be different and different with movement.So need to comprise by 16 analog switch [K by one
1a-1, K
1a-2, K
2a-1, K
2a-2, K
3a-1, K
3a-2, K
1d-1, K
1d-2, K
3d-1, K
3d-2, K
1g-1, K
1g-2, K
2g-1, K
2g-2, K
3g-1, K
3g-2] and 9 or [a F
4-1～F
4-9] the automatic gate action of the gating circuit that constitutes, realized no matter using A, B, any electronic watch core can both guarantee that conversion of signals that field " a, d, g " signal and other field signal show by " having " or " nothings " field becomes the rule of corresponding logic current potential " 1 " or " 0 ", normally carries out the conversion of the AC signal of field demonstration to the DCL electric potential signal in three kinds of movements of C.
4, the ternary output circuit that drives of coding: this circuit comprises by 3 seven sections to BCD scrambler [I
4-1～I
4-3] constitute, can convert the field code of input the coding circuit of binary-coded decimal to and by 4 ternary output driving circuit [I
5-1～I
5-4] constitute can be with binary-coded decimal through the driving output circuit of triple gate output in order to other circuit of drive controlling.
5, control circuit: this circuit is one and comprises by 2 homophase devices (level conversion) [F
1-1, F
1-2], 4 phase inverter [F
2-1, F
2-2, F
5-1, F
5-2] and a triple gate output control circuit [I
6] the above-mentioned separation of control that constitutes is deposited, gating and 3 circuit carries out work chronologically with state control circuits of the ternary output of coding.
6, a second signal output apparatus includes 1 or [a F
4-10] constitute.
7,27 external connection end include: other connects end can to meet end and 11 with 16 watch core circuit that each drive output of electronic watch core circuit lead-in wire joins, wherein:
It is respectively 2 " moon, Shi Shiwei " end [H that described 16 watch core circuit connect end
1, H
2], 4 " month, time position " holds [T
1～T
4], 4 " ten of day, branches " end [M
1～M
4], 4 " day, a branch position " end [N
1～N
4], 2 extreme [COM of common electrical
1, COM
2].
Described 11 other connect end and be respectively: 4 binary-coded decimal output terminal [Q
1～Q
4], 3 position control end [A
1～A
3], 1 gating end [ST], 1 output terminal second [S], 2 power ends [VDD, VSS].
Because interface circuit for numeric code converting timer control of the present invention adopted unique amplification, separate deposit, gating, ternary output circuit and the correspondent control circuits of driving of coding, thereby can successfully convert the AC signal that each drive output of the quartz electronic watch core circuit of liquid crystal display formula is exported to the DCL electric potential signal, and drive other electrical equipment or circuit working with the form output of three-state.Because gating circuit and the ingenious design that separates register circuit make this interface circuit be suitable for directly connecting use with the quartz electronic watch core circuit of liquid crystal display formula of existing various pairs of public electrodes, and need not to add element.This interface circuit can be used to convert calendar, four decimal datas of clock to four binary-coded decimals, and has ternary controlled serial binary-coded decimal output.Its peek required time is less than 1 μ s.Can constitute the digital spc clock and be used to various TT﹠C system with electronic watch core circuit.In addition, this interface circuit has only 27 external connection end, helps making the special-purpose integrated package of standard biserial 28 pin encapsulation like this, realizes integrated, miniaturization.
The following drawings and embodiment will be described in further detail technical solution of the present invention.
Fig. 1 is a schematic block circuit diagram of the present invention.
Fig. 2 is the total circuit theory diagrams of the present invention, also is the circuit theory diagrams of embodiment 1.
Fig. 3 is 6 ternary register [I of four identical D types among Fig. 2
3-1～I
3-6] circuit logic diagram.
Fig. 4 be among Fig. 23 identical seven sections to BCD scrambler [I
4-1～I
4-3] circuit logic diagram.
Fig. 5 is 4 identical ternary output driving circuit [I among Fig. 2
5-1～I
5-4] circuit diagram.
Fig. 6 is triple gate output control circuit [I among Fig. 2
6] adopt 1 the BCD-decimal system to translate device to make this control circuit [I
6] the circuit logic diagram of this part embodiment 5.
Above-mentioned Fig. 3,4,5,6 is respectively the circuit diagram of appropriate section embodiment of circuit 2,3,4,5 among the present invention.
Fig. 7 is every decimal numeral field symbols on existing various liquid crystal displays (numeral) the formula quartz watch liquid crystal board, and " a, b, c, d, e, f, g " wherein represents each the corresponding field in this field symbols respectively.
Fig. 8 is the join synoptic diagram of example (being embodiment 6) of the liquid crystal display formula electronic watch core circuit plate lead-in wire of the present invention and the two public electrodes of existing desk calendar type (A type).
Fig. 9 is the synoptic diagram that the present invention and the noisy liquid crystal display formula electronic watch core circuit plate lead-in wire of going through the two public electrodes of type (Type B) of existing platform connect example (being embodiment 7).
Figure 10 is the synoptic diagram that the present invention and the noisy liquid crystal display formula electronic watch core circuit plate lead-in wire of going through the two public electrodes of type (C type) of existing extension connect example (being embodiment 8).
Among above-mentioned Fig. 8,9,10: " a
1, b
1, c
1, d
1, e
1, f
1, g
1, " expression: the lead-in wire of " moon, Shi Shiwei " each field, " a
2, b
2, c
2... g
2, " lead-in wire of each field of expression " month, time ", " a
3, b
3, c
3... g
3, " lead-in wire of each field of expression " day, divide ten ", " a
4, b
4, c
4... g
4, " lead-in wire of each field of an expression " day, divide position ".
Figure 11 is after the present invention links with two public electrode liquid crystal display formula electronic watch core circuits, when receiving " month, time a position " field signal of electronic watch core circuit, element circuit figure that should " month, time " element circuit real work example (embodiment 9).
Figure 12 is the special-purpose ic chip synoptic diagram that the present invention makes the encapsulation of standard biserial 28 pin.
Figure 13 is triple gate output control circuit [I among Fig. 2
6] adopt 18 tunnels analogy transmitter (separation vessel) as triple gate output control circuit [I
6] the circuit diagram of this partial circuit embodiment 10.
Provide the specific embodiment of the embodiment of the invention and each appropriate section below with reference to accompanying drawing, and provide details of the present invention by the description of these embodiment.
Embodiment 1(is referring to Fig. 2): interface circuit for numeric code converting timer control of the present invention is designed to: 16 input resistance [R
1～R
16] 16 one ends meet end [H with 16 watch core circuit respectively
1, H
2, T
1～T
4, M
1～M
4, N
1～N
4, COM
1, COM
2] join these 16 input resistance [R
1～R
16] 16 other ends respectively with 16 operational amplifier [I
1-1～I
1-16] an input end of each operational amplifier join these 16 operational amplifier [I
1-1～I
1-16] another remaining input end is connected to power supply after all being connected together mutually and connects end [VSS], 2 operational amplifier [I
1-1～I
1-2] 2 output terminals respectively with 2 XOR gate [I
2-1～I
2-2] the A input end join.XOR gate [I
2-1] B end input end and 11 XOR gate [I
2-3～I
2-5, I
2-9～I
2-12, I
2-16～I
2-19] the B input end join after again with homophase device [F
1-2] output terminal join.XOR gate [I
2-2] B input end and 9 XOR gate [I
2-6～I
2-8, I
2-13～I
2-15, I
2-20～I
2-22] the B input end join after again with homophase device [F
1-1] output terminal join.3 operational amplifier [I
1-3～I
1-5] 3 output terminals respectively with 3 XOR gate [I
2-6～I
2-8] 3 A input ends join.Operational amplifier [I
1-6] output termination XOR gate [I
2-5] the A input end.2 operational amplifier [I
1-4, I
1-5] 2 output terminals respectively with 2 XOR gate [I
2-3, I
2-4] the A input end join.In like manner, 4 operational amplifier [I
1-7～I
1-10] 4 output terminals respectively with 4 XOR gate [I
2-9, I
2-12] the A input end join 3 operational amplifier [I
1-7～I
1-9] 3 output terminals respectively with 3 XOR gate [I
2-13～I
2-15] the A input end join.4 operational amplifier [I
1-11～I
1-14] 4 output terminals respectively with 4 XOR gate [I
2-16～I
2-19] the A input end join.3 operational amplifier [I
1-11～I
1-13] 3 output terminals respectively with 3 XOR gate [I
2-20～I
2-22] A end join.2 operational amplifier [I
1-15～I
1-16] 2 output terminals respectively with phase inverter [F
2-1] input end, homophase device [F
1-2] input end join phase inverter [F
2-1] output termination homophase device [F
1-1] input end.2 XOR gate [I
2-1, I
2-2] 2 output terminals respectively with register [I
3-1] D
4End, register [I
3-2] D
1End joins.3 XOR gate [I
2-3～I
2-5] 3 output terminals respectively with register [I
3-1] D
3, D
2, D
1End joins.3 XOR gate [I
2-6～I
2-8] 3 output terminals respectively with register [I
3-2] D
4, D
3, D
2End joins.4 XOR gate [I
2-9～I
2-12] 4 output terminals respectively with register [I
3-3] D
4～D
14 ends join.3 XOR gate [I
2-13～I
2-15] 3 output terminals respectively with register [I
3-4] D
4, D
3, D
2End joins.4 XOR gate [I
2-16～I
2-19] 4 output terminals respectively with register [I
3-5] D
4～D
14 ends join.3 XOR gate [I
2-20～I
2-22] 3 output terminals respectively with register [I
3-6] D
4, D
3, D
2End joins.6 register [I
3-1～I
3-6] 6 R end and connect after meet power end VSS.3 register [I
3-1, I
3-3, I
3-5] 3 CL end and connect after meet phase inverter [F
2-2] output terminal.3 register [I
3-2, I
3-4, I
3-6] 3 CL end and connect after meet phase inverter [F
2-1] input end.Register [I
3-1] Q
4Termination Sheffer stroke gate [F
3] the B input end, Q
3Termination scrambler [I
4-1] f end, Q
2End is through analog switch [K
1a-1] after be connected to or the door [F
4-3] the A input end, Q
2End is through analog switch [K
1a-2] be connected to or door [F
4-1] the A input end, Q
1Termination scrambler [I
4-1] b end.Register [I
3-2] Q
4End is through analog switch [K
1d-1] be connected to or door [F
4-1] the B input end, Q
4End is through analog switch [K
1d-2] be connected to or door [F
4-2] the A input end, Q
3Termination scrambler [I
4-1] e end.Q
2End is through analog switch [K
1g-1] be connected to or door [F
4-2] the B input end, Q
2End is through analog switch [K
1g-2] be connected to or door [F
4-3] the A input end, Q
1Termination Sheffer stroke gate [F
3] the A input end after be connected to driver [I
5-1] B end.Scrambler [I
4-1] a, d, a g3 end respectively with 3 or [a F
4-1, F
4-2, F
4-3] 3 output terminals join.8 analog switch [K
1a-1, K
1d-1, K
1g-1, K
2a-1, K
2g-1, K
3a-1, K
3d-1, K
3g-1] 8 control ends and connect after phase inverter [F
4-1] to gating end [ST].8 analog switch [K
1a-2, K
1d-2, K
1g-2, K
2a-2, K
2g-2, K
3a-2, K
3d-2, K
3g-2] 8 control ends and connect after meet phase inverter [F
4-2] output terminal, to phase inverter [F
4-1] output terminal and phase inverter [F
4-2] input end join; 2 register phase device [I
3-5, I
3-6] Q
4～Q
1End, scrambler [I
4-3], 3 or [a F
4-7～F
4-9], 6 analog switch [K
3a-1, K
3a-2, K
3d-1, K
3d-2, K
3g-1, K
3g-2] mutual connection with above-mentioned 2 register [I
3-1, I
3-2] and corresponding 3 or [a F
4-1～F
4-3], 6 analog switch [K
1a-1, K
1a-2, K
1d-1, K
1d-2, K
1g-1, K
1g-2] and scrambler [I
4-1] between connection the same, that different is register [I
3-5] Q
4Termination or door [F
4-10] the B input end, or the door [F
4-10] A input termination register [I
3-3] Q
4End, or door [F
4-10] output terminal be connected to a second output terminal [S]; Register [I
3-3] Q
3Termination scrambler [I
4-2] f end, Q
2End is through analog switch [K
2a-1] after connect or the door [F
4-6] the B input end, Q
2End is through analog switch [K
2a-2] be connected to or door [F
4-4] the A input end, Q
1Termination scrambler [I
4-2] b end.Register [I
3-4] Q
4Be connected to or door [F
4-4] the B input end, Q
3Termination scrambler [I
4-2] e end, Q
2End is through analog switch [K
2g-1] be connected to or door [F
4-5] the B input end, Q
2End is through analog switch [K
2g-2] be connected to or door [F
4-6] the A input end.2 or [a F
4-4, F
4-5] 2 A input ends join.Scrambler [I
4-2] a, d, a g3 end meet 3 or [a F respectively
4-4～F
4-6] 3 output terminals; 3 driver [I
5-2, I
5-3, I
5-4] D, C, B, A end respectively with 3 scrambler [I
4-1, I
4-2, I
4-3] Q
4, Q
3, Q
2, Q
1End joins.3 driver [I
5-2, I
5-3, I
5-4] the parallel connection of 3 OD end after be connected to binary-coded decimal output terminal [Q
4], be connected to binary-coded decimal output terminal [Q after the parallel connection of 3 OC ends
3], be connected to binary-coded decimal output terminal [Q after the parallel connection of 3 OB ends
2], be connected to binary-coded decimal output terminal [Q after the parallel connection of 3 OA ends
1].Driver [I
5-1] OB, OA end driver connected [I respectively
5-2] OB, OA the end.Triple gate output control circuit [I
6] 1,2,3,4 ends meet 4 ternary output driving circuit [I respectively
5-1, I
5-2, I
5-3, I
5-4] 4 DIS end.Triple gate output control circuit [I
6] A, B, C end respectively with 3 positions control A
1, A
2, A
3, join.Triple gate output control circuit [I
6] D termination power Vss.
Embodiment 2(is referring to Fig. 3): 6 ternary register [I of four identical D types among the present invention
3-1～I
3-6] circuit is designed to Fig. 3: it mainly by four D flip-flops and 3 not gates, 8 with door, 4 or, 4 gate triple gates, 2 input and output control gates constitute.Because the input of circuit, output connection make it be in transmission state, so the data D of input end
1～D
4, directly by being sent to the D end of trigger with door or door, the CL pulse is added to trigger C end, under its pulse front edge triggers, makes the data of D end deliver to output terminal Q, and deposits into.Also in other words, if trigger is not triggered by the CL pulse again, the logic current potential of Q end is stablized constant.The data of Q end are exported through triple gate, finish D
1～D
4Data are sent to Q
1To Q
4End.The effect of R is to make the trigger zero clearing, when R is 1, and the trigger zero clearing.
Embodiment 3(is referring to Fig. 4): identical seven sections of among the present invention 3 are to BCD encoder circuit [I
4-1, I
4-2, I
4-3] being designed to Fig. 4: it is the relation according to binary-coded decimal four figures and relevant field, by 10 not gates, 5 two inputs and door, 1 three input and door, 1 two input nand gate, 1 four input nand gate and 1 the two code conversion circuit that the input rejection gate is formed, wherein: Q
1The position is by three Sheffer stroke gates, 21 and door and one or constitute, through and a, e, f section occurrence logic relation, make Q
1Produce corresponding logic current potential.Q
2The position is made of three Sheffer stroke gates, two and door, a rejection gate, through and a, b, e, f section occurrence logic relation, make Q
2Produce corresponding logic current potential.Q
3The position is to be made of four Sheffer stroke gates, three and door, a rejection gate, through and a, b, d, f, g section occurrence logic relation, make Q
3Produce corresponding logic current potential.Q
4Be to constitute,, make Q through concerning with a, b, f, g section occurrence logic by two Sheffer stroke gates
4Produce corresponding logic current potential.In view of the above, after the logic current potential of six fields is passed to coding circuit, at Q
1, Q
2, Q
3, Q
4The corresponding logic current potential of last generation, Q
1To Q
4The logic current potential promptly be the decimal numeral binary-coded decimal of corresponding field.
Embodiment 4(is referring to Fig. 5): 4 identical ternary output driving circuit [I among the present invention
5-1～I
5-4] being designed to Fig. 5: it is the big output driving current tri-state gate circuit of a kind of door-control type, two metal-oxide-semiconductors constitute the CMOS phase inverter, its grid are subjected to Sheffer stroke gate output control, for increasing output driving current, be connected in series a metal-oxide-semiconductor between phase inverter and the Vss, an input end of its grid and Sheffer stroke gate is with being connected to control end DIS.When DIS is 1, the metal-oxide-semiconductor conducting of serial connection, Sheffer stroke gate is open-minded simultaneously, the phase inverter conducting, the data transmission of input end is to output terminal out.When DIS is 0, the not conducting of metal-oxide-semiconductor of serial connection, simultaneously Sheffer stroke gate is closed, is imported with output and be cut off, and output presents high resistant, has finished controlled triple gate and has driven output.
Embodiment 5(is referring to Fig. 6): the triple gate output control circuit [I among the present invention
6] can adopt a BCD-to-decimal decoder, this BCD-to-decimal decoder can be designed to Fig. 6: it is made up of 7 two input rejection gates, 10 two input nand gates, 8 not gates, 10 out gates, and it converts binary-coded decimal to decimal number output.When input end A, B, C, D import binary-coded decimal, as 0000 ..., 1001, the sign indicating number, after the logical circuit conversion, there is corresponding positive logic current potential to occur at output terminal 0 to 9, each output terminal is corresponding decimal number, as output terminal 5 are positive logic current potentials, then be decimal number 5, the binary-coded decimal that also is exactly correspondence is 0101.
Embodiment 6(is referring to Fig. 8): the liquid crystal display formula electronic watch core circuit plate lead-in wire of interface circuit for numeric code converting timer control of the present invention [ASIC] and the two public electrodes of desk calendar type (A type) links and is the T of interface circuit [ASIC]
1(H
1), T
2, T
3, T
4, M
1, M
2, M
3, M
4, N
2, N
3, N
4, COM
2These 12 external connection end are joined the COM of interface circuit [ASIC] with 2,3,4,5,6,7,8,9,10,11,12,13 these 12 ends of electronic watch core circuit plate [core A] lead-in wire respectively in order
11 end of termination electronic watch core circuit plate lead-in wire.
Embodiment 7(is referring to Fig. 9): make a noise liquid crystal display formula electronic watch core circuit plate [core B] lead-in wire of going through the two public electrodes of type (Type B) of interface circuit for numeric code converting timer control of the present invention [ASIC] and platform links and is the H of interface circuit [ASIC]
1, T
1(H
1), T
2, T
3, T
4, M
2, M
3, M
4, N
1, N
2, N
3, N
4, COM
1, COM
2These 14 external connection end are joined with 4,5,6,7,8,10,11,12,9,13,14,15,1,16 these 14 ends of electronic watch core circuit plate lead-in wire respectively in order.
Embodiment 8(is referring to Figure 10): interface circuit for numeric code converting timer control of the present invention [ASIC] and the liquid crystal display formula electronic watch core circuit plate lead-in wire of going through the two public electrodes of type (C type) of hang making a noise link and are the H of interface circuit [ASIC]
1, H
2, T
1, T
2, T
3, T
4, M
1, M
2, M
3, M
4, N
1, N
2, N
3, N
4, COM
1, COM
2These 16 external connection end in order respectively with the (b of electronic watch core circuit plate [core C] lead-in wire
1c
1), (a
1e
1d
1g
1), (a
2), (b
2c
2), (g
2d
2), (f
2e
2), (a
3), (f
3e
3), (g
3d
3), (b
3c
3), (a
4), (f
4e
4), (g
4d
4), (b
4c
4), (COM
1), (COM
12) these 16 ends join.
Embodiment 9(is referring to Figure 11): after the present invention links with two public electrode liquid crystal display formula electronic watch core circuits, get " month, time position " field signal amplify, separate deposit, gating, the ternary output unit circuit working that drives of coding be: get the Type B electronic watch core circuit, with " month, time " combined field b of electronic watch core (Type B) circuit
1d
1(the 5th point), f
2e
2(the 6th point), a
2g
2(the 7th point), b
2c
2(the 8th point) public electrode (the 1st point), public electrode (the 16th point) are connected to the T of interface circuit [ASIC] respectively in order
1, T
2, T
3, T
4, COM
1, COM
2End.T
1To T
4Signal all through I
1-3To I
1-6Amplify I
1-3To I
1-6Be output as V
0Deliver to I respectively
2-3To I
2-8A end.COM
1Signal is through I
1-15Amplify, again through F
2-1After anti-phase, pass through F
1-1(level conversion increases load capacity) is added to I
2-6To I
2-8B end.COM
2Signal is through I
1-16After the amplification, pass through F
1-2Be added to I
2-3To I
2-5B end.Because this b
1Section is not participated in conversion, so do not sent to and the public electrode XOR.Therefore, T
1Combined field b
1d
1After amplifying, only deliver to I
2-6A end, carry out XOR, then I with public electrode
1-6S end be field d
2Signal, and deliver to I
3-2D
4End is at COM
1Under the forward position trigger action of amplifying signal, D
4The d of end
2Signal is delivered to output terminal Q
4Select the Type B electronic watch core circuit for use, ST=1, then K
1d-2By gating, I
3-2Q
4Signal passes through K
1d-2Deliver to F
4-1A end, its S end is delivered to I
4-1The d end of scrambler.In like manner, T
2F
2e
2, the V after amplifying
0Deliver to I simultaneously
2-3, I
2-7A end, respectively with I
2-3, I
2-7B end phase XOR, I
2-3S output f
2Signal is sent to F
3-1D
3End is at COM
2Amplify output V
0, through F
2-2Under the forward position trigger action of anti-phase back signal, D
4The signal of end is delivered to output terminal Q
4, and directly deliver to I
4-1F end.I
2-7The e of S end output
2Signal is sent to I
3-2D
3, at COM
1Under the forward position trigger action of amplifying signal, D
3Signal deliver to output terminal Q
3, and directly deliver to I
4-1E end.T
3Combined field a
2g
2, after amplification, separation are deposited, I
3-1Q
2The signal of end passes through K
1a-2Deliver to F
4-1A end, deliver to I again from its S end
4-1A end.I
3-2Q
2The signal of end passes through K
1g-2, deliver to F
4-3A end, deliver to I again from its S end
4-1G end.T
4Combined field b
2c
2Through amplifying (owing to need not the C field during coding, so the C field does not participate in conversion), I after separating
3-1Q
1The signal of end is directly delivered to I
4-1B end.Like this, at I
4-1Input end a, b, d, e, f, g field signal, encoded conversion, I are arranged
4-1Output terminal is binary-coded decimal, and delivers to I
5Input end A, B, C, D, if A
3, A
2, A
1Be 010, I
6Output pulse distribution position 2 is 1, I
5-2DIS end be 1, I then
5-2The output binary-coded decimal realizes that promptly the conversion of signals of " month, time " field is a binary-coded decimal, as I
5-2DIS end be O, then be output as high impedance.When using C type electronic watch core circuit, K
1a-1, K
1d-1, K
1g-1By gating,, deliver to I respectively different field signals
4-1Carry out code conversion on the corresponding field end, at I
6Under the control, I
5-2The output binary-coded decimal.
" ten of day, branches, individual of day, branch " transfer principle is the same.M
1, N
1When connecing A type electronic watch core circuit or Type B electronic watch core circuit, I
3-3Q
4End or I
3-5Q
4End output is a second signal, passes through F
4-10To second signal output part [S] output second signal.
Embodiment 10(is referring to Figure 13): the triple gate output control circuit [I in the control circuit of the present invention
6] can adopt one 8 tunnels analogy transmitter (separation vessel), this transmitter (separation vessel) is designed to Figure 13: by 8 analog switches, level shift and one have forbid controlling 8 select 1 transmitter to constitute.With way circuit of the present invention according to below connect: when given sequence code (binary-coded decimal), output terminal has 8 to select 1 switching value output, so output switching terminal is met the control end DIS of controlled triple gate respectively.Because controlled have only four, be connected to every DIS end respectively so select for use four switches of transmitter to export an end 1,2,3,4 chronologically, promptly replace BCD-to-decimal decoder and connect former output terminal 1,2,3,4, and sequence code A, the B of transmitter, C are connected to A, B, the C place of the input end of former code translator respectively.Switch one end (out/ln) of transmitter connects power positive end [VDD], and the VEE of transmitter, inh end all connects the VSS end.
Claims (10)
1, a kind of interface circuit for numeric code converting timer control, it is characterized in that this interface circuit includes: amplify, separate deposit, gating, ternary output, control and second signal output apparatus of driving of coding, with 27 external connection end that connect usefulness with external circuit, this interface circuit can carry out that signal amplifies, field is separated, four figures converts the DCL current potential simultaneously to the clock signal of two public electrode liquid crystal display formula electronic watch core circuits, and by 27 external connection end directly and electronic watch core circuit and other all kinds of circuit link and constitute various in good time TT﹠C system, wherein:
Described amplifying circuit comprises by 16 input resistance [R
1～R
16] and 16 operational amplifier [I
1-1～I
1-16] 16 in-phase amplifiers constituting, the various signals that this amplifying circuit will be taken from each drive output output of electronic watch core circuit are amplified to and are enough to promote next stage and separate the required logic current potential of cmos circuit conversion in the register circuit,
Described separation register circuit comprises by 22 XOR gate [I
2-1～I
2-22] separation circuit that constitutes and by the ternary register [I of 6 four D types
3-1～I
3-6] register circuit that constitutes forms, the interchange field shows signal of sending here after amplifying circuit is amplified is deposited to handle through separation and is converted corresponding DCL current potential output to,
Described gating circuit is that the AC signal that various field that a kind of electronic watch core circuit that guarantees various pairs of omnibus circuits is sent here shows can both be converted into dc logic signal smoothly, includes 16 analog switch [K
1a-1, K
1a-2, K
2a-1, K
2a-2, K
3a-1, K
3a-2, K
1d-1, K
1d-2, K
3d-1, K
3d-2, K
1g-1, K
1g-2, K
2g-1, K
2g-2, K
3g-1, K
3g-2] and 9 or [a F
4-1～F
4-9] automatic strobe circuit,
Described coding is ternary, and to drive output circuit be a kind ofly to include 3 seven sections to BCD scrambler [F
4-1～F
4-3] coding circuit that the input word segment encode can be converted to binary-coded decimal that constitutes and by 4 ternary output driving circuit [I
5-1～I
5-4] constitute can be with binary-coded decimal through the driving output circuit of triple gate output in order to other circuit of drive controlling.
Described control circuit is one and comprises by 2 homophase device [F
1-1, F
1-2], 4 phase inverter [F
2-1, F
2-2, F
5-1, F
5-2] and one can be by a BCD-to-decimal decoder or the triple gate output control circuit [I that can constitute by one 8 tunnels analogy transmitter (separation vessel)
6] controllable sub formed from deposit, gating and coding are ternary drives these three circuit of output carry out work chronologically with state control circuit,
Signal output apparatus included one or [a F in described second
4-10] constitute, described 27 external connection end include: 16 watch core circuit meet end and 11, and other connects end, and wherein: 16 watch core circuit connect end and are respectively: 2 " months, Shi Shiwei " hold [H
1, H
2], 4 " month, time position " hold [T
1～T
4], 4 " day, divide ten " end [M
1～M
4], 4 " day, divide position " end [N
1～N
4] and 2 extreme [COM of common electrical
1, COM
2], 11 other connect end and be respectively: 4 binary-coded decimal output terminal [Q
1～Q
4], 3 positions control end [A
1, A
2, A
3], 1 gating end [ST], 1 output terminal second [S] and 2 power ends [VDD, VSS].
2, according to claim 1 interface circuit for numeric code converting timer control, is characterized in that this interface circuit is designed to: 16 input resistance [R1～R
16] 16 ends meet end [H with 16 watch core circuit respectively1、H
2、T
1～T
4、M
1～M
4、N
1～N
4、COM
1、COM
2] join, these 16 input resistance [R1～R
16] 16 other ends respectively with 16 operational amplifier [I1-1～I
1-16] the input (+) of each operational amplifier join, these 16 operational amplifier [I1-1～I
1-16] another remaining input (-) is connected to power supply after all being connected together and connects end [VSS], 2 operational amplifier [I1-1、I
1-2] 2 outputs respectively with 2 XOR gate [I2-1、I
2-2] the A input join, XOR gate [I2-1] B input and 11 XOR gate [I2-3～I
2-5、I
2-9～I
2-12、I
2-16～I
2-19] the B input join after again with homophase device [F1-2] output join, XOR gate [I2-2] B input and 9 XOR gate [I2-6～I
2-8、I
2-13～I
2-15、I
2-20～I
2-22] B end input join after again with homophase device [F1-1] output join; 3 operational amplifier [I1-3～I
1-5] 3 outputs respectively with 3 XOR gate [I2-6～I
2-8] 3 A inputs join; Operational amplifier [I1-6] output termination XOR gate [I2-5] the A input; 2 operational amplifier [I1-4、I
1-5] 2 outputs respectively with 2 XOR gate [I2-3、I
2-4] the A input join; In like manner, 4 operational amplifier [I1-7～I
1-10] 4 outputs respectively with 4 XOR gate [I2-9～I
2-12] the A input join, 3 operational amplifier [I1-7～I
1-9] 3 outputs respectively with 3 XOR gate [I2-13～I
2-15] the A input join; 4 operational amplifier [I1-11～I
1-14] 4 outputs respectively with 4 XOR gate [I2-16～I
2-19] the A input join; 3 operational amplifier [I1-11～I
1-13] 3 outputs respectively with 3 XOR gate [I2-20～I
2-22] the A input join; 2 operational amplifier [I1-15、I
1-16] 2 outputs and phase inverter [F2-1] input, homophase device [F1-1] input join, phase inverter [F2-1] output termination homophase device [F1-2] input; 2 XOR gate [I2-1、I
2-2] 2 outputs respectively with register [I3-1] D4End, register [I3-2]D
1End joins; 3 XOR gate [I2-3～I
2-5] 3 outputs respectively with register [I3-1] D3、D
2、D
1End joins; 3 XOR gate [I2-6～I
2-8] 3 outputs respectively with register [I3-2] D4、D
3、D
2End joins; 4 XOR gate [I2-9 ～I
2-12 ] 4 outputs respectively with register [I 3-3] D 4 ～D
14 Individual end joins; 3 XOR gate [I2-13 ～I
2-15] 3 outputs respectively with register [I 3-4] D 4 、D
3 、D
2End joins; 4 XOR gate 2-12] 4 outputs join with 14 ends of D 4～D of register [I 3-3] respectively; 3 outputs of 3 XOR gates [I 2-13～I 2-15] join with D 4, D 3, D 2 ends of register [I 3-4] respectively; 4 XOR gate [I2-16～I
2-19] 4 outputs respectively with register] I3-5] D4～D
14Individual end joins; 3 XOR gate [I2-20～I
2-22] 3 outputs respectively with register [I3-6] D4、D
3、D
2End joins; 6 register [I3-1～I
3-6] 6 R hold and connect after meet power end VSS; 3 register [I3-1、I
3-3、I
3-5] 3 CL hold and connect after meet phase inverter [F2-2] output; 3 register [I3-2、I
3-4、I
3-6] 3 CL hold and connect after meet phase inverter [F2-1] input; Register [I3-1] Q4Termination NAND gate [F3] the B input, Q3Hold the encoder [I that joins4-1] f end, Q2End is through analog switch [K1a-1] after be connected to or the door [F4-3] the B input, Q2End is through analog switch [K1a-2] be connected to or door [F4-1] the A input, Q1Termination encoder [I4-1] b end; Register [I3-2] Q4End is through analog switch [K1d-1] be connected to or door [F4-1] the B input, Q4End is through analog switch [K1d-2] be connected to or door [F4-2] the A input, Q3Termination encoder [I4-1] e end, Q2End is through analog switch [K1g-1] be connected to or door [F4-2] the B input, Q2End is through analog switch [K1g-2] be connected to or door [F4-3] the A input, Q1Termination NAND gate [F3] the A input after be connected to driver [I5-1] B end; Encoder [F4-1] a, d, a g3 end respectively with 3 or [a F4-1、F
4-2、F
4-3] 3 outputs join; Gating end [ST] is through phase inverter [F5-1] rear and 8 analog switch [K1a-1、K
1d-1、K
1g-1、K
2a-1、K
2g-1、K
3a-1、K
3d-1、K
3g-1] 8 control ends and connect after meet phase inverter [F5-1] output, its input is to gating end [ST]; 8 analog switch [K1a-2、K
1d-2、K
1g-2、K
2a-2、K
2g-2、K
3a-2、K
3d-2、K
3g-2] 8 control ends and connect after meet phase inverter [F5-2] output, phase inverter [F5-1] output and phase inverter [F5-2] input join; 2 register [I3-5、I
3-6] Q4～Q
1End, encoder [I4-3], 3 or [a F4-7～F
4-9], 6 analog switch [K3a-1、K
3a-2、K
3d-1、K
3d-2、K
3g-1、K
3g-2] mutual connection with above-mentioned 2 register [I3-1、I
3-2] and corresponding 3 or [a F4-1～F
4-3], 6 analog switch [K1a-1、K
1a-2、K
1d-1、K
1d-2、K
1g-1、K
1g-2] and encoder [I4-1] between connection the same, difference is register [I3-5] Q4Termination or door [F4-10] the B input, or the door [F4-10] A termination register [I3-3] Q4End, or door [F4-10] output be connected to a second output [S]; Register [I3-3] Q3Termination encoder [F4-2] f end, Q2End is through analog switch [K2a-1] after connect or the door [F4-6] the B input, Q2End is through analog switch [K2a-2] be connected to or door [F4-4] the A input, Q1Termination encoder [F4-2] b end; Register [I3-4] Q4Be connected to or door [F4-4] the B input, Q3Termination encoder [I4-2] e end, Q2End is through analog switch [K2g-1] be connected to or door [F4-5] the B input; Q2End is through analog switch [K2g-2] be connected to or door [F4-6] the A input; 2 or [a F4-4、F
4-5] 2 A inputs join; Encoder [I4-2] a, d, a g3 end meet respectively 3 or [a F4-4～F
4-6] 3 outputs; 3 driver [I5-2、I
5-3、I
5-4] D, C, B, A end respectively with 3 encoder [I4-1、I
4-2、I
4-3,] Q4、Q
3、Q
2、Q
1End joins; 3 driver [I5-2、I
5-3、I
5-4] the parallel connection of 3 OD end after be connected to binary-coded decimal output [Q4], be connected to binary-coded decimal output [Q after the parallel connection of 3 OC ends3], be connected to binary-coded decimal output [Q after the parallel connection of 3 OB ends2], be connected to binary-coded decimal output [Q after the parallel connection of 3 OA ends1], driver [I5-1] OB, OA end driver connected [I respectively5-2] OB, OA the end; Triple gate output control circuit [I6] 1,2,3,4 ends meet respectively 4 ternary output drive circuit [I5-1、I
5-2、I
5-3、I
5-4] 4 DIS end; Triple gate output control circuit [I6] A, B, C end respectively with 3 positions control end A1、A
2、A
3Join; Triple gate output control circuit [I6] D termination power Vss end.
3,, it is characterized in that 6 ternary register [I of four identical D types wherein according to the interface circuit for numeric code converting timer control of claim 1 and claim 2
3-1～I
3-6] circuit be by 4 D flip-flops and 3 not gates, 8 constitute with door, 4 gate triple gates, 2 input and output control gates.
4,, it is characterized in that identical seven sections of wherein 3 are to BCD encoder circuit [I according to the interface circuit for numeric code converting timer control of claim 1 and claim 2
4-1～I
4-3] by 10 not gates, 5 two inputs and door, 1 three input and door, 1 two input nand gate, 1 four input nand gate and 1 the two code conversion circuit that the input rejection gate is formed.
5,, it is characterized in that 4 identical ternary output driving circuit [I wherein according to the interface circuit for numeric code converting timer control of claim 1 and claim 2
5-1～I
5-4] be the big output driving current tri-state gate circuit of a kind of door-control type.
6,, it is characterized in that triple gate output control circuit [I wherein according to the interface circuit for numeric code converting timer control of claim 1 and claim 2
6] can adopt a BCD-to-decimal decoder, this code translator includes 7 two input rejection gates, 10 two input nand gates, 8 not gates, 10 out gates compositions.
7,, it is characterized in that triple gate output control circuit [I wherein according to the interface circuit for numeric code converting timer control of claim 1 and claim 2
6] can adopt one 8 tunnels analogy transmitter (separation vessel), this transmitter includes 8 analog switches, 1 electromigration and 1 to be had and forbids controlling 8 and select 1 code translator.
8,, it is characterized in that this interface circuit [ASIC] and the two public electrode liquid crystal display formula of desk calendar type (A type) electronic watch core circuit plate lead-in wire links and be the T of this interface circuit [ASIC] according to the interface circuit for numeric code converting timer control of claim 1 and claim 2
1(H
1), T
2, T
3, T
4, M
1, M
2, M
3, M
4, N
2, N
3, N
4, COM
1, COM
2These 13 external connection end have 2,3,4,5,6,7,8,9,10,11,12,1,13 these 13 ends to join with electronic watch core circuit plate [core A] lead-in wire respectively in order.
9,, it is characterized in that this interface circuit [ASIC] and platform make a noise to go through the two public electrode liquid crystal display of type (Type B) formula electronic watch core circuit plate lead-in wire and link and be the H of this interface circuit [ASIC] according to the interface circuit for numeric code converting timer control of claim 1 and claim 2
2, T
1(H
1), T
2, T
3, T
4, M
2, M
3, M
4, N
1, N
2, N
3, N
4, COM
1, COM
2These 14 external connection end are joined with 4,5,6,7,8,10,11,12,13,14,15,1,16 these 14 ends of electronic watch core circuit plate [core B] lead-in wire respectively in order.
10,, it is characterized in that this interface circuit [ASIC] goes through the two public electrode liquid crystal display formula of type (C type) electronic watch core circuit plate lead-in wire and link and be the H of this interface circuit [ASIC] with hang making a noise according to the interface circuit for numeric code converting timer control of claim 1 and claim 2
1, H
2, T
1, T
2, T
3, T
4, M
1, M
2, M
3, M
4, N
1, N
2, N
3, N
4, COM
1, COM
2These 16 external connection end in order respectively with the (b of electronic watch core circuit plate [core B] lead-in wire
1c
1), (a
1e
1d
1g
1), (a
2), (b
2c
2), (g
2d
2), (f
2e
2), (a
3), (f
3e
3), (g
3d
3), (b
3c
3), (a
4), (f
4e
4), (g
4d
4), (b
4c
4), (COM
1), (COM
2) these 16 ends join.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 91111346 CN1073020A (en) | 1991-12-04 | 1991-12-04 | Interface circuit for numeric code converting timer control |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 91111346 CN1073020A (en) | 1991-12-04 | 1991-12-04 | Interface circuit for numeric code converting timer control |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1073020A true CN1073020A (en) | 1993-06-09 |
Family
ID=4910584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 91111346 Pending CN1073020A (en) | 1991-12-04 | 1991-12-04 | Interface circuit for numeric code converting timer control |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1073020A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1777032B (en) * | 2005-12-06 | 2010-12-08 | 东南大学 | Four-channel mismatch-free clock control circuit |
| CN101300500B (en) * | 2005-11-02 | 2011-07-27 | Nxp股份有限公司 | Ic testing methods and apparatus |
| CN112233613A (en) * | 2020-10-29 | 2021-01-15 | 中国航发南方工业有限公司 | Display panel assembly, display and operation device of gas turbine generator set |
-
1991
- 1991-12-04 CN CN 91111346 patent/CN1073020A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101300500B (en) * | 2005-11-02 | 2011-07-27 | Nxp股份有限公司 | Ic testing methods and apparatus |
| CN1777032B (en) * | 2005-12-06 | 2010-12-08 | 东南大学 | Four-channel mismatch-free clock control circuit |
| CN112233613A (en) * | 2020-10-29 | 2021-01-15 | 中国航发南方工业有限公司 | Display panel assembly, display and operation device of gas turbine generator set |
| CN112233613B (en) * | 2020-10-29 | 2021-08-06 | 中国航发南方工业有限公司 | Display panel assembly, display and operation device of gas turbine generator set |
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