CN107301284B - Digital-analog hybrid system and power management circuit - Google Patents
Digital-analog hybrid system and power management circuit Download PDFInfo
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- CN107301284B CN107301284B CN201710449334.0A CN201710449334A CN107301284B CN 107301284 B CN107301284 B CN 107301284B CN 201710449334 A CN201710449334 A CN 201710449334A CN 107301284 B CN107301284 B CN 107301284B
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- 238000004806 packaging method and process Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 12
- 238000004590 computer program Methods 0.000 description 7
- 238000012986 modification Methods 0.000 description 5
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/06—Structured ASICs
Abstract
The embodiment of the application provides a digital-analog hybrid system and a power management circuit, and the digital-analog hybrid system comprises: a digital unit for processing the digital signal; an analog unit for processing an analog signal; a power supply pin for providing a power-on reset signal for the digital unit; and supplying power to the analog unit; and the power management unit is connected to the power supply pin and used for generating a power-on reset signal of the digital unit and a power signal of the analog unit. By adopting the scheme, one pin can be used for simultaneously powering on and resetting the digital unit and supplying power to the analog unit, so that the pin number and the size of the power management chip are reduced, and the chip packaging is facilitated.
Description
Technical Field
The present application relates to the field of integrated circuit design, and in particular, to a digital-analog hybrid system and a power management circuit.
Background
In a digital-to-analog hybrid system, such as a bluetooth system, a power management chip, a digital chip and an analog chip are typically included. When the system starts to work, the power management chip is needed to power on and reset the digital chip, and meanwhile, the analog chip also needs the power management chip to supply power.
In the prior art, a connection relationship between a power management chip and a digital chip and an analog chip is shown in fig. 1, the power management chip needs to provide 2 output pins, one power-on reset POR pin for performing power-on reset on the digital chip, and the other AVDD pin for supplying power to the analog chip.
The inventor thinks that, adopting the scheme in the prior art, adopting two pins to supply power for digital chip and analog chip, the pin that needs is more for circuit design is complicated, and the chip volume increases, is unfavorable for the encapsulation.
Disclosure of Invention
The embodiment of the application provides a digital-analog hybrid system and a power management circuit, which are used for solving the problems that in the prior art, a power management chip has more pins and is not beneficial to packaging.
According to a first aspect of embodiments of the present application, there is provided a digital-analog hybrid system, comprising: a digital unit for processing the digital signal; an analog unit for processing an analog signal; a power supply pin for providing a power-on reset signal for the digital unit; and supplying power to the analog unit; and the power management unit is connected to the power supply pin and used for generating a power-on reset signal of the digital unit and a power signal of the analog unit.
According to a second aspect of the embodiments of the present application, there is provided a power management circuit applied to a digital-analog hybrid system, including: a voltage regulator for generating a power supply signal; the time delay module is used for delaying the power supply signal generated by the voltage stabilizer; and the power supply pin is connected to the delay module and used for outputting a power-on reset signal to the digital unit of the digital-analog hybrid system and outputting a power supply signal to the analog unit of the digital-analog hybrid system.
By adopting the digital-analog hybrid system and the power management circuit provided by the embodiment of the application, one pin can be used for simultaneously powering on and resetting the digital unit and supplying power to the analog unit, so that the number and the size of the pins of the power management chip are reduced, and the chip packaging is facilitated.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 illustrates a circuit connection diagram of a prior art digital-to-analog hybrid system;
FIG. 2 is a circuit diagram of a digital-analog hybrid system according to a first embodiment of the present application;
fig. 3 is a circuit connection diagram of another digital-analog hybrid system according to an embodiment of the present application.
Detailed Description
In the process of implementing the present application, the inventor finds that, when the digital-analog hybrid system shown in fig. 1 is adopted, two pins are required to supply power to the digital chip and the analog chip, and more pins and connection (bonding) lines are required, so that the circuit design is complicated, the chip size is increased, and the packaging is not facilitated.
In order to solve the technical problem, the application provides a digital-analog hybrid system and a power management circuit, which can use one pin to simultaneously power on and reset a digital unit and supply power to an analog unit, thereby reducing the pin number and the volume of a power management chip and facilitating the chip packaging.
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Example one
Fig. 2 is a circuit connection diagram of a digital-analog hybrid system according to a first embodiment of the present application.
As shown in fig. 2, the digital-analog hybrid system according to the first embodiment of the present application includes: the device comprises a digital unit, an analog unit, a power supply pin POR and a power management unit.
Specifically, the digital unit is used for processing digital signals; the analog unit is used for processing an analog signal; a power supply pin for providing a power-on reset signal for the digital unit; and supplying power to the analog unit; and the power management unit is connected to the power supply pin and used for generating a power-on reset signal of the digital unit and a power signal of the analog unit.
The POR pin is always kept high when the system works normally, so that the POR pin can be used for supplying power to the analog chip.
In an implementation, the power management unit may be packaged in a chip and connected to the digital unit and the analog unit outside the chip through the power supply pin.
In particular, the digital unit and the analog unit may be each packaged in a chip. Specifically, the digital-analog hybrid system may be a bluetooth system; the digital unit may be a CPU; the analog unit may be an oscillator.
In a specific implementation, the power management unit may include: a voltage regulator for generating a power supply signal; and the delay module is used for delaying the power supply signal generated by the voltage stabilizer and is connected between the voltage stabilizer and the power supply pin.
The delay module may be a timing processing circuit commonly used in the prior art, and is configured to delay a power signal generated by the LDO by a predetermined time period, for example, several tens of milliseconds, so as to power on the digital chip within the predetermined time period after the system is started, and trigger the digital chip to perform a reset operation.
In specific implementation, the digital-analog hybrid system may further include: and the filtering unit is connected between the power supply pin and the analog unit and is used for preventing other circuits from interfering the analog chip.
In specific implementation, the digital-analog hybrid system according to the embodiment of the present application may further adopt a circuit connection manner as shown in fig. 3. As shown in fig. 3, there may be a plurality of analog units, and the analog units are respectively connected to the power supply pin. By adopting the mode, more pins and bonding wires can be saved, the number of the pins and the bonding wires are further reduced, the size of a chip is reduced, and the product cost is reduced.
In a specific implementation, the power supply voltages of the analog units can be the same, so that the analog chips can be directly connected to the power supply pins or can be used after being filtered.
In specific implementation, if the power supply voltages of the plurality of analog units are different, the power supply voltage output by the power supply pin can be subjected to voltage conversion and then supplied to the analog units.
By adopting the digital-analog hybrid system in the embodiment of the application, the power-on reset (POR) pin in the power management chip is adopted to supply power to the analog unit, so that chip pins and bonding lines are reduced, and the cost is saved.
Based on the same inventive concept, an embodiment of the present application further provides a power management circuit applied to a digital-analog hybrid system as shown in fig. 2, including: a voltage regulator for generating a power supply signal; the time delay module is used for delaying the power supply signal generated by the voltage stabilizer; and the power supply pin POR is connected to the delay module and used for outputting a power-on reset signal to the digital unit of the digital-analog hybrid system and outputting a power supply signal to the analog unit of the digital-analog hybrid system.
In specific implementation, the voltage stabilizer and the delay module are packaged in a chip and are connected to a digital unit and an analog unit outside the chip through the power supply pin.
The implementation of the power management circuit can refer to the implementation of the power management unit in the digital-analog hybrid system, and repeated details are not repeated.
By adopting the power management circuit in the embodiment of the application, the power-on reset (POR) pin is adopted to supply power to the analog unit, so that the number and the volume of the pins of the power management chip are controlled, and the chip packaging is facilitated.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (7)
1. A digital to analog mixing system, comprising:
a digital unit for processing the digital signal;
an analog unit for processing an analog signal;
the power supply pin POR is used for providing a power-on reset signal for the digital unit and supplying power for the analog unit;
the power management unit is connected to the power supply pin POR and used for generating a power-on reset signal of the digital unit and a power signal of the analog unit; the power management unit is packaged in the chip and is connected to a digital unit and an analog unit outside the chip through the power supply pin POR.
2. The system of claim 1, wherein the power management unit comprises:
a voltage regulator for generating a power supply signal;
and the time delay module is used for delaying the power supply signal generated by the voltage stabilizer and is connected between the voltage stabilizer and the power supply pin.
3. The system of claim 1, further comprising:
and the filtering unit is connected between the power supply pin POR and the analog unit.
4. The system according to claim 1, wherein the analog units are plural, and the plural analog units are respectively connected to the power supply pin POR.
5. The system of claim 4, wherein the supply voltages of the plurality of analog units are the same.
6. The system of claim 1, wherein the digital-to-analog hybrid system comprises a bluetooth system; the digital unit comprises a CPU; the analog unit includes an oscillator.
7. The utility model provides a power management circuit, is applied to digital analog hybrid system which characterized in that includes:
a voltage regulator for generating a power supply signal;
the time delay module is used for delaying the power supply signal generated by the voltage stabilizer;
the power supply pin POR is connected to the delay module and used for outputting a power-on reset signal to a digital unit of the digital-analog hybrid system and outputting a power supply signal to an analog unit of the digital-analog hybrid system; the voltage stabilizer and the time delay module are packaged in the chip and are connected to a digital unit and an analog unit outside the chip through the power supply pin POR.
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| CN201710449334.0A CN107301284B (en) | 2017-06-14 | 2017-06-14 | Digital-analog hybrid system and power management circuit |
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| CN201710449334.0A CN107301284B (en) | 2017-06-14 | 2017-06-14 | Digital-analog hybrid system and power management circuit |
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| CN107301284B true CN107301284B (en) | 2020-09-22 |
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| CN108235180B (en) * | 2017-12-12 | 2020-12-25 | 南京中感微电子有限公司 | Bluetooth circuit |
| CN111180440B (en) * | 2020-01-20 | 2023-04-18 | 杭州电子科技大学 | Single-phase direct current motor driving chip and chip drawing method |
| CN112398328B (en) * | 2020-11-24 | 2022-04-12 | 西安空间无线电技术研究所 | Power supply starting time sequence self-control circuit suitable for complex digital-analog hybrid system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103885799A (en) * | 2014-03-05 | 2014-06-25 | 烽火通信科技股份有限公司 | Microprocessor delay start system and method based on power management |
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| US5859649A (en) * | 1995-05-15 | 1999-01-12 | Motorola, Inc. | Data processing system having display controller with bursting direct memory access |
| US7197578B1 (en) * | 2002-06-28 | 2007-03-27 | Cypress Semiconductor Corp. | Power management system for bridge circuit |
| CN101882864B (en) * | 2010-06-25 | 2012-08-22 | 矽力杰半导体技术(杭州)有限公司 | Electrifying startup circuit and electrifying startup method thereof |
| CN104281067A (en) * | 2014-09-26 | 2015-01-14 | 金学成 | Pin multiplexing control method and device for motor control and drive chip |
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| CN103885799A (en) * | 2014-03-05 | 2014-06-25 | 烽火通信科技股份有限公司 | Microprocessor delay start system and method based on power management |
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