CN107300813B - Array substrate and liquid crystal display panel - Google Patents
Array substrate and liquid crystal display panel Download PDFInfo
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- CN107300813B CN107300813B CN201710631920.7A CN201710631920A CN107300813B CN 107300813 B CN107300813 B CN 107300813B CN 201710631920 A CN201710631920 A CN 201710631920A CN 107300813 B CN107300813 B CN 107300813B
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- 239000000758 substrate Substances 0.000 title claims abstract description 73
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 23
- 239000010409 thin film Substances 0.000 claims abstract description 95
- 239000002184 metal Substances 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000010410 layer Substances 0.000 claims description 111
- 239000011521 glass Substances 0.000 claims description 26
- 239000000969 carrier Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 claims description 5
- 239000011241 protective layer Substances 0.000 claims description 4
- 230000000638 stimulation Effects 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 3
- 230000005611 electricity Effects 0.000 description 16
- 230000003068 static effect Effects 0.000 description 16
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The array substrate and the liquid crystal display panel provided by the invention can reduce the control on ESD and LCQ on the premise of ensuring the functional characteristics of the liquid crystal display panel. The array substrate comprises LCQ test wiring, driving wiring, ADD wiring, a first thin film transistor, a second thin film transistor and a third thin film transistor, wherein the first thin film transistor, the second thin film transistor and the third thin film transistor respectively comprise a gate electrode, a gate insulating layer, a semiconductor layer, a first electrode and a second electrode, the three first electrodes are formed by a first metal layer, the three second electrodes are formed by a second metal layer arranged at intervals with the first metal layer, the first metal layer is electrically connected with the LCQ test wiring, the second metal layer is electrically connected with the driving wiring, the gate electrode of the first thin film transistor is electrically connected with the first metal layer, and the gate electrode of the second thin film transistor is electrically connected with the second metal layer.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to an array substrate and a liquid crystal display panel.
Background
The preparation of the liquid crystal display panel comprises an Array substrate (Array) process, a color film substrate (CF) process and a Cell aligning process of the Array substrate and the color film substrate, and generally, a panel function test (CellTest) is performed during the Cell process to detect the defects of the display panel in the Array, the CF and the Cell, so as to separate the defective products. Currently, a common method for Cell Test is to detect the image quality by deflecting liquid crystal molecules through dataline and gateline inverse terminal sides and LCQ (liquid crystal Display quick) partial injection signals, and the LCQ principle is as follows: in the test, a TFT (Thin Film Transistor) is turned on by an ADD signal, and then an R/G/B signal is transmitted to rotate liquid crystal molecules. In addition, in the manufacture of a liquid crystal display panel, in order to avoid damage to a product due to Static electricity, an electrostatic discharge (ESD) protection circuit is generally provided in the liquid crystal display panel. ESD principle: when Data appears high voltage, the TFT is turned on, and a high voltage signal is transmitted to a Short Ring region through the TFT, so that large current is transmitted out, and the electrostatic protection effect is achieved.
In recent years, liquid crystal display panels and organic EL display devices each having a TFT for each pixel have been widely used. The TFT is manufactured by forming an array substrate using a semiconductor layer formed on a substrate such as a glass substrate. In the related art, the array substrate adopts 4PEP (Four Photo engineering Process), and the TFT in the ESD and LCQ regions needs to be detected by channels, so that the detection time is too long, and the productivity is affected.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides an array substrate and a liquid crystal display panel, which can reduce the control of ESD and LCQ on the premise of ensuring the functional characteristics of the liquid crystal display panel.
The technical scheme of the invention is as follows:
an array substrate comprises substrate glass, and an LCQ test wiring, a driving wiring, an ADD wiring, a first thin film transistor, a second thin film transistor and a third thin film transistor which are arranged on one side of the substrate glass, wherein each of the first thin film transistor, the second thin film transistor and the third thin film transistor comprises a gate electrode, a gate insulating layer, a semiconductor layer, a first electrode and a second electrode, the gate insulating layer is positioned between the gate electrode and the semiconductor layer, the first electrode and the second electrode are positioned on one side of the semiconductor layer, which is far away from the gate electrode, the three first electrodes are formed by a first metal layer, the three second electrodes are formed by a second metal layer which is arranged at intervals with the first metal layer, and the orthographic projections of the first metal layer and the second metal layer on the substrate glass are in a straight strip shape, the first metal layer is electrically connected to the LCQ test wiring, the second metal layer is electrically connected to the driving wiring, the gate electrode of the first thin film transistor is electrically connected to the first metal layer, and the gate electrode of the second thin film transistor is electrically connected to the second metal layer.
Preferably, a channel region is formed on a side of the semiconductor layer away from the gate electrode, and a first region electrically connected to the first electrode and a second region electrically connected to the second electrode are respectively disposed on two sides of the channel region.
Preferably, each of the first thin film transistor, the second thin film transistor, and the third thin film transistor further includes a first contact layer disposed on the first region and a second contact layer disposed on the second region, and the first electrode and the second electrode are electrically connected to the semiconductor layer through the first contact layer and the second contact layer, respectively.
Preferably, the array substrate further includes an insulating protection layer, and the first thin film transistor, the second thin film transistor, and the third thin film transistor are located between the substrate glass and the insulating protection layer.
Preferably, the three gate insulating layers are connected in sequence to form an integral structure.
Preferably, the gate electrode is located on the substrate glass.
Preferably, the first electrode and the second electrode are located on the substrate glass.
Preferably, the semiconductor layer is provided with a protective film for preventing the semiconductor layer from generating photogenerated carriers due to light stimulation of a backlight.
The invention also provides a liquid crystal display panel which comprises the array substrate.
The array substrate and the liquid crystal display panel provided by the embodiment of the invention have the following technical effects: by arranging the three first electrodes to be formed by a first metal layer, the three second electrodes to be formed by a second metal layer arranged at intervals from the first metal layer, the first metal layer being electrically connected with the LCQ test wiring, the second metal layer being electrically connected with the driving wiring, the gate electrode of the first thin film transistor being electrically connected with the first metal layer, and the gate electrode of the second thin film transistor being electrically connected with the second metal layer, it is possible to reduce the control of ESD and LCQ on the premise of ensuring the functional characteristics of the liquid crystal display panel; meanwhile, the orthographic projections of the first metal layer and the second metal layer on the substrate glass are in a straight strip shape, so that the uniformity of the channel region of the ESD and the channel region of the LCQ can be ensured.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is an equivalent circuit diagram of an array substrate of the present invention;
fig. 2 is an enlarged view of a portion C of the array substrate shown in fig. 1;
FIG. 3 is a schematic partial structural diagram of an array substrate according to a first embodiment of the present invention;
fig. 4 is a cross-sectional view of the array substrate of fig. 3 taken along a-a direction;
FIG. 5 is a cross-sectional view of the array substrate of FIG. 3 taken along the direction B-B;
fig. 6 is a partial cross-sectional view of a second embodiment of an array substrate according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Note that the LCQ test wiring, the drive wiring, the ADD wiring, and the pixel unit are not illustrated in fig. 3 to 6.
Fig. 1 is an equivalent circuit diagram of an array substrate of the present invention, and fig. 2 is an enlarged view of a portion C of the array substrate shown in fig. 1. Referring to fig. 1 and 2, the array substrate 100 includes a plurality of LCQ test wirings 11, a plurality of driving wirings 12 formed of gate lines gate and data lines data, ADD wirings 13, a plurality of first thin film transistors 14, a plurality of second thin film transistors 15, a plurality of third thin film transistors 16, and pixel units 10 connected to the gate lines gate and the data lines data. One of the first thin film transistor 14, one of the second thin film transistor 15, and one of the third thin film transistor 16 constitute one of the LCQ and ESD units, and the LCQ test wiring 11, the driving wiring 12, and the LCQ and ESD units are disposed in one-to-one correspondence. In one of the LCQ and ESD cells, the drain and gate of the first thin film transistor 14, the drain of the second thin film transistor 15, and the source of the third thin film transistor 16 are all electrically connected to the LCQ test wiring 11 corresponding to the LCQ and ESD cell, the source of the first thin film transistor 14, the source and gate of the second thin film transistor 15, and the drain of the third thin film transistor 16 are all electrically connected to the drive wiring 12 corresponding to the LCQ and ESD cell, the gate of the third thin film transistor 16 is electrically connected to the wiring ADD 13, and a parallel circuit is formed between the gates of the third thin film transistors 16 of each of the LCQ and ESD cells. Wherein, a plurality of the LCQ test wirings 11 are connected to a signal input terminal, and the R/G/B signal inputted from the LCQ test wirings 11 is transmitted to the driving wirings 12 through the third thin film transistor 16 and transmitted to the pixel unit 10 by the driving wirings 12, so that the liquid crystal molecules are rotated, thereby realizing the R/G/B picture test.
When the ADD wiring 13 is at a high voltage, the R/G/B signal inputted from the LCQ test wiring 11 is transmitted to the drive wiring 12 through the third thin film transistor 16, and in this case, if static electricity exists on the drive wiring 12, even the first thin film transistor 14 is discharged through the second thin film transistor 15, and the discharge time is extremely short, and does not affect the transmission of the R/G/B signal. Specifically, when a large static electricity exists on the driving wiring 12, the second thin film transistor 15 is caused to conduct to form a static electricity path 1-1, when the static electricity on the driving wiring 12 is transferred to the LCQ test wiring 11 through the static electricity path 1-1, at this time, the LCQ test wiring 11 serves as a static electricity discharge terminal and discharges the charges through a peripheral circuit, and when a sufficiently large charge is accumulated on the LCQ test wiring 11, the first thin film transistor 14 is also caused to conduct to form a static electricity path 2-1, so that the static electricity on the driving wiring 12 can be quickly discharged through the static electricity path 1-1 and the static electricity path 2-1.
When the ADD wiring 13 is at a low voltage, the third thin film transistor 16 is always kept in an off state, and in this case, if a large static electricity exists in the driving wiring 12, the static electricity charge on the driving wiring 12 can flow to the LCQ test wiring 11 through the static electricity channel 1-1 or the static electricity channel 1-1 and the static electricity channel 2-1 in two channels, and the discharge of the charge is performed through a peripheral line.
Since the third thin film transistor 16 is turned on and off by the voltage on the ADD wiring 13, the ADD wiring 13 is referred to as a total switch for LCQ detection.
Example one
FIG. 3 is a schematic partial structural diagram of an array substrate according to a first embodiment of the present invention; fig. 4 is a cross-sectional view of the array substrate of fig. 3 taken along a-a direction; fig. 5 is a cross-sectional view of the array substrate of fig. 3 taken along a direction B-B. Referring to fig. 3 to 5, the array substrate 100 further includes a substrate glass 17, and the LCQ test wiring 11, the driving wiring 12, the ADD wiring 13, the first thin film transistor 14, the second thin film transistor 15, and the third thin film transistor 16 are disposed on one side of the substrate glass 17. The first thin film transistor 14, the second thin film transistor 15, and the third thin film transistor 16 each include a gate electrode 141, a gate insulating layer 142, a semiconductor layer 143, a first electrode 144, and a second electrode 145, which are disposed on one side of the substrate glass 17, the gate insulating layer 142 is disposed between the gate electrode 141 and the semiconductor layer 143, a channel region 146 is formed on one side of the semiconductor layer 143 away from the gate electrode 141, a first region 147 and a second region 148 are respectively disposed on two sides of the channel region, the first electrode 144 is electrically connected to the first region 147, the second electrode 145 is electrically connected to the second region 148, the three first electrodes 144 are formed by a first metal layer a, and the three second electrodes 145 are formed by a second metal layer b disposed at an interval from the first metal layer a.
The gate electrode 141 is a metal layer, the first metal layer a is electrically connected to the LCQ test line 11, the second metal layer b is electrically connected to the driving line 12, the gate electrode 141 of the first thin film transistor 14 is electrically connected to the first metal layer a, and the gate electrode 141 of the second thin film transistor 15 is electrically connected to the second metal layer b. That is, the first metal layer a simultaneously serves as the drain of the first thin film transistor 14, the drain of the second thin film transistor 15, and the source of the third thin film transistor 16, and the second metal layer b simultaneously serves as the source of the first thin film transistor 14, the source and the gate of the second thin film transistor 15, and the drain of the third thin film transistor 16. In this embodiment, the gate electrode 141 is located on the substrate glass 17, that is, the array substrate 100 is a bottom gate structure. Since the gate electrode 141 and the gate insulating layer 142 can simultaneously serve as optical protective layers for the semiconductor layer 143, the semiconductor layer 143 can be prevented from generating photo-generated carriers due to light stimulation from a backlight, and the photo-generated carriers can damage the electrical characteristics of the semiconductor layer 143.
Further, orthographic projections of the first metal layer a and the second metal layer b on the substrate glass 17 are in a straight strip shape, so that center lines of the three channel regions 146 are overlapped, when the first thin film transistor 14, the second thin film transistor 15 and the third thin film transistor 16 are turned on, a current direction in each channel region 146 is perpendicular to the center lines, and therefore uniformity of an ESD channel region and a LCQ channel region can be guaranteed.
Further, the array substrate 100 further includes an insulating protection layer 149, and the first thin film transistor 14, the second thin film transistor 15, and the third thin film transistor 16 are located between the substrate glass 1 and the insulating protection layer 149.
Further, the three gate insulating layers 142 are sequentially connected in an end-to-end manner to form an integral structure.
Further, each of the first thin film transistor 14, the second thin film transistor 15, and the third thin film transistor 16 further includes a first contact layer 149 disposed on the first region 147 and a second contact layer 150 disposed on the second region 148, and the first electrode 144 and the second electrode 145 are electrically connected to the semiconductor layer 143 through the first contact layer 149 and the second contact layer 150, respectively.
Example two
Fig. 6 is a partial cross-sectional view of a second embodiment of an array substrate according to the present invention. Referring to fig. 6, the array substrate 200 includes a plurality of LCQ test wirings, a plurality of driving wirings formed of gate lines gate and data lines data, ADD wirings, a plurality of first thin film transistors, a plurality of second thin film transistors, a plurality of third thin film transistors, pixel units connected to the gate lines gate and the data lines data, a substrate glass 27, and an insulating protection layer 28, the first thin film transistor, the second thin film transistor, and the third thin film transistor each include a gate electrode 241, a gate insulating layer 242, a semiconductor layer 243, a first electrode 244, a second electrode 245, a first contact layer 249, and the second contact layer 250 provided on one side of a substrate glass 27, the gate insulating layer 242 is positioned between the gate electrode 241 and the semiconductor layer 243, the first electrode 244 and the second electrode 245 are located on a side of the semiconductor layer 243 away from the gate electrode 241. Wherein the LCQ test wiring, the driving wiring, the ADD wiring, the first thin film transistor, the second thin film transistor, the third thin film transistor, and the pixel unit constitute the same equivalent circuit as in the first embodiment. The difference between the second embodiment and the first embodiment is that: the first electrode 244 and the second electrode 245 are located on the substrate glass 27. That is, the array substrate 200 is a top gate structure. Due to the fact that the first electrode 244 and the second electrode 245 are located on the substrate glass 27, the shape and the configuration of the gate electrode 241, the gate insulating layer 242, the semiconductor layer 243 and the insulating protection layer 28 are changed correspondingly. In addition, since the first electrode 244 and the second electrode 245 are located on the substrate glass 27, both the gate electrode 241 and the gate insulating layer 242 cannot be used as an optical protective layer for the semiconductor layer 243, a protective film (not shown) for preventing the semiconductor layer 243 from generating photo-generated carriers due to light stimulation from a backlight source needs to be provided on the semiconductor layer 243.
The invention also provides a liquid crystal display panel which comprises the array substrate of the first embodiment and the array substrate of the second embodiment.
The array substrate and the liquid crystal display panel provided by the embodiment at least have the following technical effects: by arranging the three first electrodes to be formed by a first metal layer, the three second electrodes to be formed by a second metal layer arranged at intervals from the first metal layer, the first metal layer being electrically connected with the LCQ test wiring, the second metal layer being electrically connected with the driving wiring, the gate electrode of the first thin film transistor being electrically connected with the first metal layer, and the gate electrode of the second thin film transistor being electrically connected with the second metal layer, it is possible to reduce the control of ESD and LCQ on the premise of ensuring the functional characteristics of the liquid crystal display panel; meanwhile, the orthographic projections of the first metal layer and the second metal layer on the substrate glass are in a straight strip shape, so that the uniformity of the channel region of the ESD and the channel region of the LCQ can be ensured.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. An array substrate, comprising a substrate glass, and an LCQ test wiring, a driving wiring, an ADD wiring, a first thin film transistor, a second thin film transistor and a third thin film transistor which are arranged on one side of the substrate glass, wherein the first thin film transistor, the second thin film transistor and the third thin film transistor respectively comprise a gate electrode, a gate insulating layer, a semiconductor layer, a first electrode and a second electrode, the gate insulating layer is positioned between the gate electrode and the semiconductor layer, the first electrode and the second electrode are positioned on one side of the semiconductor layer, which is far away from the gate electrode, wherein the three first electrodes are formed by a first metal layer, the three second electrodes are formed by a second metal layer which is arranged at a distance from the first metal layer, and the orthographic projections of the first metal layer and the second metal layer on the substrate glass are in a straight strip shape, the first metal layer is electrically connected to the LCQ test wiring, the second metal layer is electrically connected to the driving wiring, the gate electrode of the first thin film transistor is electrically connected to the first metal layer, and the gate electrode of the second thin film transistor is electrically connected to the second metal layer.
2. The array substrate of claim 1, wherein a channel region is formed on a side of the semiconductor layer away from the gate electrode, and a first region electrically connected to the first electrode and a second region electrically connected to the second electrode are respectively disposed on two sides of the channel region.
3. The array substrate of claim 2, wherein the first thin film transistor, the second thin film transistor, and the third thin film transistor each further comprise a first contact layer disposed on the first region and a second contact layer disposed on the second region, and the first electrode and the second electrode are electrically connected to the semiconductor layer through the first contact layer and the second contact layer, respectively.
4. The array substrate of claim 1, further comprising an insulating protective layer, wherein the first thin film transistor, the second thin film transistor and the third thin film transistor are located between the substrate glass and the insulating protective layer.
5. The array substrate of claim 1, wherein three gate insulating layers are sequentially connected in an end-to-end manner to form an integral structure.
6. The array substrate of claim 1, wherein the gate electrode is located on the substrate glass.
7. The array substrate of claim 1, wherein the first electrode and the second electrode are located on the substrate glass.
8. The array substrate of claim 7, wherein the semiconductor layer is provided with a protective film for preventing the semiconductor layer from generating photo-generated carriers due to light stimulation from a backlight source.
9. A liquid crystal display panel comprising the array substrate according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710631920.7A CN107300813B (en) | 2017-07-28 | 2017-07-28 | Array substrate and liquid crystal display panel |
Applications Claiming Priority (1)
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| CN101369589A (en) * | 2008-10-15 | 2009-02-18 | 友达光电股份有限公司 | Array substrate of thin-film transistor |
| KR20100108939A (en) * | 2009-03-31 | 2010-10-08 | 하이디스 테크놀로지 주식회사 | Lcd having the test pad |
| CN102280447A (en) * | 2011-08-04 | 2011-12-14 | 无锡中星微电子有限公司 | Electrostatic protection circuit |
| CN104021747A (en) * | 2014-05-23 | 2014-09-03 | 京东方科技集团股份有限公司 | Panel function test circuit, display panel, function testing method and electrostatic protection method |
| CN205665504U (en) * | 2016-04-26 | 2016-10-26 | 京东方科技集团股份有限公司 | Array substrate's circuit, array substrate , display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101369589A (en) * | 2008-10-15 | 2009-02-18 | 友达光电股份有限公司 | Array substrate of thin-film transistor |
| KR20100108939A (en) * | 2009-03-31 | 2010-10-08 | 하이디스 테크놀로지 주식회사 | Lcd having the test pad |
| CN102280447A (en) * | 2011-08-04 | 2011-12-14 | 无锡中星微电子有限公司 | Electrostatic protection circuit |
| CN104021747A (en) * | 2014-05-23 | 2014-09-03 | 京东方科技集团股份有限公司 | Panel function test circuit, display panel, function testing method and electrostatic protection method |
| CN205665504U (en) * | 2016-04-26 | 2016-10-26 | 京东方科技集团股份有限公司 | Array substrate's circuit, array substrate , display device |
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