CN107291421A - System and method occurs for a kind of programmable graphics sequence - Google Patents
System and method occurs for a kind of programmable graphics sequence Download PDFInfo
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- CN107291421A CN107291421A CN201710477618.0A CN201710477618A CN107291421A CN 107291421 A CN107291421 A CN 107291421A CN 201710477618 A CN201710477618 A CN 201710477618A CN 107291421 A CN107291421 A CN 107291421A
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- sequence
- word
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- prbs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/582—Pseudo-random number generators
Abstract
The present invention proposes a kind of programmable graphics sequence and occurs system, including：Word pattern generator, PRBS pattern generators, coding circuit, serial to parallel conversion circuit, delays time to control and output driving circuit；Word pattern generator and PRBS pattern generators produce a variety of programablc word patterns and pseudo-random pattern by the setting of user, by the word figure of write storage circuit or the PRBS figures of setting, encoded circuit is encoded, then serial to parallel conversion circuit is passed through, the parallel signal of low speed is converted to the serial signal of high speed, then pass through delays time to control and output driving circuit, signal is added into delay, direct current biasing, most afterwards through optic electric interface circuit output.The test rate of the present invention can realize 100Mb/s~12.5Gb/s continuously adjustabes, bias 0.2V~3.3V continuously adjustabes, the programmable graphics sequence generation circuit design of amplitude 0.1V~2.0V continuously adjustabes.
Description
Technical field
The present invention relates to technical field of measurement and test, system occurs for more particularly to a kind of programmable graphics sequence, further relates to one kind
Programmable graphics sequence generating method.
Background technology
The current tester that can realize 100Mb/s~12.5Gb/s continuously adjustabe technologies both at home and abroad is simultaneously few, mainly
There is day intrinsic safety to found MP1800, the N4906B of Agilent company of the U.S., the BSA125C of Imtech of the U.S. of company, wherein comparing
Typical product is the vertical signal quality analyzer MP1800 of day intrinsic safety, test rate covering 100Mb/s~12.5Gb/s, output
Amplitude 0.1V~2.0V, supports plurality of level standard.On the premise of speed is up to 12.5Gb/s, high-speed programmable figure sequence
MUX required in generation technique circuit arrangement can not possibly have been realized using discrete device, and commercialization MUX substantially speed is relative
It is relatively low, it is impossible to meet the job requirement of such high-speed.
Because existing solution its speed is low and biasing, amplitude adjusted scope are not wide enough, serial biography can not be met
The test of transferring technology development needs.
The content of the invention
To solve above-mentioned deficiency of the prior art, the present invention proposes that system and side occur for a kind of programmable graphics sequence
Method, solves low existing solution its speed and biasing, the problem of amplitude adjusted scope is not wide enough.
The technical proposal of the invention is realized in this way：
System occurs for a kind of programmable graphics sequence, including：Word pattern generator, PRBS pattern generators, coding circuit,
Serial to parallel conversion circuit, delays time to control and output driving circuit；
Word pattern generator and PRBS pattern generators produce a variety of programablc word patterns and pseudorandom by the setting of user
Figure, by the word figure of write storage circuit or the PRBS figures of setting, encoded circuit is encoded, then by string
And translation circuit, the parallel signal of low speed is converted to the serial signal of high speed, then by delays time to control and output driving electricity
Road, adds delay, direct current biasing, most afterwards through optic electric interface circuit output by signal.
Alternatively, the PRBS pattern generators use parallel processing manner, produce pseudo-random sequence, are closed by low speed sequence
As high speed sequence, n roads pseudo-random pattern is produced first under 1/n clocks, the speed per road figure only has the 1/ of clock frequency
N, then figure all the way is synthesized by Graphics compositor.
Alternatively, the PRBS pattern generators include：M-sequence generator, combinational logic circuit, synthesizer；
M-sequence generator passes through combinational logic circuit, forms n parallel m-sequence, then by n synthesizer synthesis
PRBS Sequence all the way；
If n speed is of equal value for R m-sequence displacement, and its phase differs the 1/n figure cycles each other；To this n roads m-sequence
Sampled in turn with nR speed, then obtain the m-sequence that speed is nR, the sequence and the displacement of original n speed R m-sequence
It is of equal value.
Alternatively, the word pattern generator includes：Address generator is selected through cpu address, the ground in selection DDR3
The corresponding user in location sets word, is compared after shifting processing circuit with receiving word figure in synchronizing indicator, and give
Go out synchronization character sequence and stop signal.
Alternatively, the acquisition of word figure is to be stored in advance in the word set in high speed DDR3 SDRAM to realize by reading
's.
Alternatively, reconfigured to receiving word figure in the way of parallel processing, locally generated word figure is used
The method for circulating supplement displacement, realizes the reading by bit.
The invention also provides a kind of programmable graphics sequence generating method, word pattern generator and PRBS pattern generators
A variety of programablc word patterns and pseudo-random pattern are produced by the setting of user, by the word figure of write storage circuit or setting
PRBS figures, encoded circuit is encoded, then by serial to parallel conversion circuit, and the parallel signal of low speed is converted at a high speed
Serial signal, then by delays time to control and output driving circuit, by signal add delay, direct current biasing, most afterwards through photoelectricity
Interface circuit is exported.
Alternatively, the PRBS pattern generators use parallel processing manner, produce pseudo-random sequence, are closed by low speed sequence
As high speed sequence, n roads pseudo-random pattern is produced first under 1/n clocks, the speed per road figure only has the 1/ of clock frequency
N, then figure all the way is synthesized by Graphics compositor；
Alternatively, the PRBS pattern generators include：M-sequence generator, combinational logic circuit, synthesizer；
M-sequence generator passes through combinational logic circuit, forms n parallel m-sequence, then by n synthesizer synthesis
PRBS Sequence all the way；
If n speed is of equal value for R m-sequence displacement, and its phase differs the 1/n figure cycles each other；To this n roads m-sequence
Sampled in turn with nR speed, then obtain the m-sequence that speed is nR, the sequence and the displacement of original n speed R m-sequence
It is of equal value.
Alternatively, the word pattern generator includes：Address generator is selected through cpu address, the ground in selection DDR3
The corresponding user in location sets word, is compared after shifting processing circuit with receiving word figure in synchronizing indicator, and give
Go out synchronization character sequence and stop signal.
The beneficial effects of the invention are as follows：
(1) test rate can realize 100Mb/s~12.5Gb/s continuously adjustabes, biasing -0.2V~3.3V continuously adjustabes,
The programmable graphics sequence generation circuit design of amplitude 0.1V~2.0V continuously adjustabes；
(2) plurality of level standard such as NECL, SCFL, NCML, PCML, LVPECL, LVDS serial transmission is met well
The demand of test.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
For a kind of programmable graphics sequence of the invention the theory diagram of system occurs for Fig. 1；
Fig. 2 is the theory diagram of the PRBS pattern generators of the present invention；
Fig. 3 is the theory diagram of the word pattern generator of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Include as shown in figure 1, system occurs for the programmable graphics sequence of the present invention：Word pattern generator, PRBS figures hair
Raw device, error code/alarm insertion circuit, clock management circuits, coding circuit, serial to parallel conversion circuit, delays time to control and output driving
Circuit.
System occurs for programmable graphics sequence by the word figure of write storage circuit or the PRBS figures of setting, by compiling
Code circuit is encoded, and then by parallel serial conversion circuit, the parallel signal of low speed is converted to the serial signal of high speed, then
By delay and running, signal is added into delay, direct current biasing, enhancing driving force, most afterwards through light, electrical interface circuit output.Its
In, clock management circuits are using high speed, wideband digital PHASE-LOCKED LOOP PLL TECHNIQUE and synchronization frequency division frequency doubling technology come needed for generation system
The clock signal of each speed.
Word pattern generator and PRBS pattern generators produce a variety of programablc word patterns and pseudorandom by the setting of user
Figure, and carry out graphic format conversion and error code insertion.Because speed is high, and continuously adjustabe, pseudo-random pattern and programmable word
The generation of figure needs to be realized with special method.The programablc word pattern sequence of the present invention occurs system and uses parallel processing
Mode, first in 1/n (n=2k, n roads pseudo-random pattern is produced under the clock of k >=3), and the speed per road figure only has clock frequency
1/n, then pass through Graphics compositor synthesis figure all the way.
Delays time to control and output driving circuit mainly complete that the equilibrium treatment of output signal, amplitude be program control, skew is program control and
Output impedance conversion etc., to realize high-speed digital signal speed is adjustable, level can be set requirement.
Width when data rate is up to 12.5Gb/s per bit only has 80ps, and high speed GaAs devices are in 12.5GHz
Triggering clock under output delay up to 100ps, the delay of the device such as general High Speed ECL, LVPECL, LVDS is bigger.Circuit
In device and printed wiring can also produce transmission delay, if transmission delay exceedes the clock cycle, trigger will produce false touch
Hair.Therefore, it is extremely difficult directly to produce 12.5Gb/s pseudo-random sequences with the method for shift register.Set for reduction circuit
The difficulty and raising reliability of meter, the generation of pseudo-random sequence and word figure need to realize using special method.
The higher pseudo-random sequence of speed is produced, compensation of delay method can be used in theory, this method is with appropriate delay
Line replaces d type flip flop and XOR, so as to produce the sequence of high speed.But this method realizes difficulty, and is difficult to be applied to
Different clock frequencies.
The PRBS pattern generators of the present invention produce pseudo-random sequence using Concurrent Design, are by low speed sequent synthesis
High speed sequence, it is relatively low to the delay requirement of device.As shown in Fig. 2 m (m=2a- 1, a >=1) sequencer process combination
Logic circuit, forms n parallel m-sequence, then synthesizes PRBS Sequence all the way by n synthesizer.
With reference to Fig. 2, if n speed is of equal value for R m-sequence displacement, and its phase differs the 1/n figure cycles each other.To this n
Road m-sequence is sampled in turn with nR speed, then can obtain the m-sequence that speed is nR, the sequence and original n speed R m sequences
The displacement of row is of equal value.And n speed is R, the displacement m-sequence of equal value of phase difference 1/n sequence periods can be by a m sequence
Row carry out a series of XOR to obtain.
Using the above method of the present invention, the operating rate of m-sequence generator only has original 1/n, is high-speed and continuous figure
The generation of shape provides condition.
Using the method for computer simulation, design can produce the combinational logic circuit and low speed of n roads low rate PRBS outputs
The tap position of shift register, finally synthesizes high speed signal all the way by n roads low speed PRBS signals.Wherein low speed shift LD
The tap position of device is determined according to corresponding origin multinomial.
For programmable word sequence, with the raising of data transmission system complexity and transmission speed, it is desirable to for testing
The speed more and more higher that the length of the programablc word pattern sequence of transmission equipment is increasingly longer, produce, is set with fully meeting assessment
The requirement of standby performance.If the length of programablc word pattern reaches 128Mbit, figure speed reaches 12.5Gb/s, and is used for storage figure
The processing speed of the memory of shape is difficult to reach so high speed, and with the raising of speed and capacity, the cost of memory
Also rapid to improve, conventional circuit mode is difficult to the requirement for meeting design.
Therefore, the word pattern generator of the present invention is adopted the following technical scheme that：As shown in figure 3, address generator is through CPU
Location is selected, and the corresponding user in the address sets word in selection DDR3, with receiving word figure synchronous after shifting processing circuit
It is compared in detector, and provides synchronization character sequence and stop signal.
The acquisition of the programablc word pattern of the present invention is to be stored in advance in the word set in high speed DDR3SDRAM by reading
Come what is realized.It is the high speed DDR3SDRAM of 512 as can compile that the present invention, which chooses operating rate up to 1600MHz, data width,
The memory cell of journey word figure, the generation of word figure is first with 512 readings, then transforms to 32 and handled, and is that can reach receipts
Hair word sequence compares detection by bit, also to be reconfigured to receiving word figure in the way of parallel processing, to this real estate
New word figure realizes the reading by bit, this is greatly reduced deposits to high speed DDR3SDRAM using the method for circulation supplement displacement
Store up the requirement of capacity.
16 channel parallel datas of FPGA outputs pass through 16：1MUX chips, you can speed is parallel for 781.25MHz 16 tunnels
Data are converted into the 1 tunnel serial data that speed is 12.5GHz.
The data of MUX chips output are again through high-speed driver, with reference to DAC, the output electricity of amplifier control high-speed driver
Source voltage, output stage biased voltage-regulation biasing, coarse adjustment, thin tuning port regulation the amplitude of oscillation, you can realize biasing -0.2V~
3.3V continuously adjustabes, amplitude 0.1V~2.0V continuously adjustabes.
The test rate of the present invention can realize 100Mb/s~12.5Gb/s continuously adjustabes, and biasing -0.2V~3.3V is continuous
Adjustable, the programmable graphics sequence generation circuit design of amplitude 0.1V~2.0V continuously adjustabes meets plurality of level mark well
The demand that the accurate serial transmission such as NECL, SCFL, NCML, PCML, LVPECL, LVDS is tested.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God is with principle, and any modification, equivalent substitution and improvements made etc. should be included in the scope of the protection.
Claims (10)
1. system occurs for a kind of programmable graphics sequence, it is characterised in that including：Word pattern generator, PRBS pattern generators,
Coding circuit, serial to parallel conversion circuit, delays time to control and output driving circuit；
Word pattern generator and PRBS pattern generators produce a variety of programablc word patterns and pseudo-random pattern by the setting of user,
By the word figure of write storage circuit or the PRBS figures of setting, encoded circuit is encoded, then by going here and there and becoming
Circuit is changed, the parallel signal of low speed is converted to the serial signal of high speed, will then by delays time to control and output driving circuit
Signal adds delay, direct current biasing, most afterwards through optic electric interface circuit output.
2. system occurs for a kind of programmable graphics sequence as claimed in claim 1, it is characterised in that the PRBS figures occur
Device uses parallel processing manner, produces pseudo-random sequence, is high speed sequence by low speed sequent synthesis, is produced first under 1/n clocks
Raw n roads pseudo-random pattern, only has the 1/n of clock frequency per the speed of road figure, then synthesize figure all the way by Graphics compositor.
3. system occurs for a kind of programmable graphics sequence as claimed in claim 2, it is characterised in that the PRBS figures occur
Device includes：M-sequence generator, combinational logic circuit, synthesizer；
M-sequence generator passes through combinational logic circuit, forms n parallel m-sequence, then by n synthesizer synthesis all the way
PRBS Sequence；
If n speed is of equal value for R m-sequence displacement, and its phase differs the 1/n figure cycles each other；To this n roads m-sequence with nR
Speed sample in turn, then obtain the m-sequence that speed is nR, the displacement equivalence of the sequence and original n speed R m-sequence.
4. system occurs for a kind of programmable graphics sequence as claimed in claim 1, it is characterised in that the word pattern generator
Include：Address generator is selected through cpu address, and the corresponding user in the address sets word in selection DDR3, by shifting processing
It is compared after circuit with receiving word figure in synchronizing indicator, and provides synchronization character sequence and stop signal.
5. system occurs for a kind of programmable graphics sequence as claimed in claim 4, it is characterised in that
The acquisition of word figure is to be stored in advance in the word set in high speed DDR3 SDRAM to realize by reading.
6. system occurs for a kind of programmable graphics sequence as claimed in claim 4, it is characterised in that
Reconfigured to receiving word figure in the way of parallel processing, to locally generated word figure using circulation supplement displacement
Method, realize by bit reading.
7. a kind of programmable graphics sequence generating method, it is characterised in that
Word pattern generator and PRBS pattern generators produce a variety of programablc word patterns and pseudo-random pattern by the setting of user,
By the word figure of write storage circuit or the PRBS figures of setting, encoded circuit is encoded, then by going here and there and becoming
Circuit is changed, the parallel signal of low speed is converted to the serial signal of high speed, will then by delays time to control and output driving circuit
Signal adds delay, direct current biasing, most afterwards through optic electric interface circuit output.
8. a kind of programmable graphics sequence generating method as claimed in claim 7, it is characterised in that the PRBS figures occur
Device uses parallel processing manner, produces pseudo-random sequence, is high speed sequence by low speed sequent synthesis, is produced first under 1/n clocks
Raw n roads pseudo-random pattern, only has the 1/n of clock frequency per the speed of road figure, then synthesize figure all the way by Graphics compositor.
9. a kind of programmable graphics sequence generating method as claimed in claim 8, it is characterised in that the PRBS figures occur
Device includes：M-sequence generator, combinational logic circuit, synthesizer；
M-sequence generator passes through combinational logic circuit, forms n parallel m-sequence, then by n synthesizer synthesis all the way
PRBS Sequence；
If n speed is of equal value for R m-sequence displacement, and its phase differs the 1/n figure cycles each other；To this n roads m-sequence with nR
Speed sample in turn, then obtain the m-sequence that speed is nR, the displacement equivalence of the sequence and original n speed R m-sequence.
10. a kind of programmable graphics sequence generating method as claimed in claim 7, it is characterised in that the word figure occurs
Device includes：Address generator is selected through cpu address, and the corresponding user in the address sets word in selection DDR3, at displacement
It is compared after reason circuit with receiving word figure in synchronizing indicator, and provides synchronization character sequence and stop signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710477618.0A CN107291421A (en) | 2017-06-09 | 2017-06-09 | System and method occurs for a kind of programmable graphics sequence |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710477618.0A CN107291421A (en) | 2017-06-09 | 2017-06-09 | System and method occurs for a kind of programmable graphics sequence |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112162946A (en) * | 2020-09-17 | 2021-01-01 | 中电科仪器仪表有限公司 | 100Gbps pseudo-random pattern generating device |
| CN112836982A (en) * | 2021-02-22 | 2021-05-25 | 长春汇通光电技术有限公司 | Instruction list generation method and device and computer readable storage medium |
| TWI806340B (en) * | 2021-01-14 | 2023-06-21 | 大陸商深圳比特微電子科技有限公司 | Test circuit for pipeline stage including sequential device to be tested, test method and computing system including test circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112162946A (en) * | 2020-09-17 | 2021-01-01 | 中电科仪器仪表有限公司 | 100Gbps pseudo-random pattern generating device |
| TWI806340B (en) * | 2021-01-14 | 2023-06-21 | 大陸商深圳比特微電子科技有限公司 | Test circuit for pipeline stage including sequential device to be tested, test method and computing system including test circuit |
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