CN107290908B - Electrostatic protection circuit and liquid crystal display panel - Google Patents
Electrostatic protection circuit and liquid crystal display panel Download PDFInfo
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- CN107290908B CN107290908B CN201710488488.0A CN201710488488A CN107290908B CN 107290908 B CN107290908 B CN 107290908B CN 201710488488 A CN201710488488 A CN 201710488488A CN 107290908 B CN107290908 B CN 107290908B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/22—Antistatic materials or arrangements
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Abstract
The invention provides an electrostatic protection circuit and a liquid crystal display panel. The electrostatic protection circuit is provided with an ESD device (1) which is electrically connected with the Mth signal line (L) (M) on the Mth signal line (L (M)), and a linkage device (2) which is electrically connected with the two signal lines (L (M) and L (M +1)) is correspondingly arranged between every two adjacent signal lines (L (M) and L (M + 1)); the linkage device (2) is used for conducting static electricity on the corresponding signal line (L (M)) to the signal line adjacent to the linkage device, linkage of the ESD devices (1) between two adjacent signal lines is achieved, the multiple ESD devices on the multiple signal lines can play a protection role simultaneously, the antistatic capacity of the ESD devices in the liquid crystal display panel can be enhanced, and greater flexibility can be provided for circuit layout of the liquid crystal display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to an electrostatic protection circuit and a liquid crystal display panel.
Background
During the manufacturing and transportation of Thin Film Transistor Liquid Crystal Display (TFT-LCD), an Electro-Static Discharge (ESD) phenomenon is easily generated. When electrostatic discharge occurs, a large current is generated in a short time, and once the electrostatic discharge current flows through a semiconductor integrated circuit, electrostatic damage is generally caused, so that an insulating medium is broken down, and the threshold voltage of a thin film transistor is shifted or a gate and a source are short-circuited. Unless there is a proper discharge path, when static charge is accumulated to a certain extent and discharged, a part of pixel structures in the TFT-LCD may be damaged, resulting in poor display, and even causing damage to the whole TFT-LCD.
Referring to fig. 1 and 2, a conventional ESD protection circuit for a liquid crystal display panel generally includes an ESD device 100 corresponding to a signal line l (M) (where M is a positive integer). As shown in fig. 1, the first type ESD device 100 is referred to as a CMOS type ESD device, and is composed of an N-type TFT T10 and a P-type TFT T20, the gate and the drain of the N-type TFT T10 are shorted, both are connected to a constant voltage low potential VGL, and the source is electrically connected to a corresponding signal line l (m); the gate and drain of the P-type TFT T20 are shorted, both connected to a constant voltage high voltage VGH, and the source is electrically connected to the corresponding signal line L (M). When positive electrostatic charges are accumulated on the signal line l (m) to such an extent that the potential of the source of the P-type TFT T20 is higher than the constant voltage high potential VGH, the P-type TFT T20 is turned on to discharge static electricity; when negative electrostatic charges are accumulated on the signal line l (m) to such an extent that the potential of the source of the N-type TFT T10 is lower than the constant voltage low potential VGL, the N-type TFT T10 is turned on to discharge the electrostatic charges.
As shown in fig. 2, the second type ESD device 100 is referred to as an NMOS type ESD device, and is formed by connecting a first N-type TFT T30 and a second N-type TFT T40 in series, the gate and the drain of the first N-type TFT T30 are shorted, both are connected to a constant voltage low potential VGL, and the source is electrically connected to a corresponding signal line l (m); the grid electrode and the drain electrode of the second N-type TFT T40 are in short circuit and are electrically connected with the corresponding signal line L (M), and the source electrode is connected with the constant-voltage high-potential VGH. When positive electrostatic charges are accumulated on the signal line l (m) to such an extent that the potential of the gate electrode of the second N-type TFT T40 is higher than the constant voltage high potential VGH, the second N-type TFT T40 is turned on to discharge static electricity; when negative electrostatic charges are accumulated on the signal line l (m) to such an extent that the potential of the source of the first N-type TFT T30 is lower than the constant voltage low potential VGL, the first N-type TFT T30 is turned on to discharge the electrostatic charges.
As can be seen from the above description, the ESD device 100 on one signal line l (m) only plays a role of electrostatic protection for this signal line l (m), so to improve the ESD resistance of the ESD device 100, the size of the ESD device 100 is often increased, which is an examination for the Layout (Layout) design of the liquid crystal display panel.
Disclosure of Invention
The invention aims to provide an electrostatic protection circuit, which can enhance the antistatic capability of an ESD device in a liquid crystal display panel and can provide greater flexibility for the circuit layout of the liquid crystal display panel.
Another objective of the present invention is to provide a liquid crystal display panel, in which the ESD device has a strong anti-static capability and the circuit layout has a high flexibility.
In order to achieve the above object, the present invention provides an electrostatic protection circuit, which includes a plurality of signal lines, a plurality of ESD devices, and a plurality of linkage devices, wherein the signal lines are sequentially arranged;
setting M as a positive integer, correspondingly setting an ESD device electrically connected with the Mth signal line on the Mth signal line, and correspondingly setting a linkage device electrically connected with the two signal lines between every two adjacent signal lines;
the ESD device is used for electrostatic discharge; the linkage device is used for conducting static electricity on the corresponding signal line to the signal line adjacent to the signal line, and linkage of the ESD device between the two adjacent signal lines is achieved.
Optionally, the linkage device includes at least two transmission gates connected in series;
the transmission gate comprises a first P-type thin film transistor and a first N-type thin film transistor which is arranged opposite to the first P-type thin film transistor; the grid electrode of the first P-type thin film transistor is suspended, the source electrode of the first P-type thin film transistor is electrically connected with the source electrode of the first N-type thin film transistor and serves as the input end of the transmission gate, and the drain electrode of the first P-type thin film transistor is electrically connected with the drain electrode of the first N-type thin film transistor and serves as the output end of the transmission gate; the grid electrode of the first N-type thin film transistor is suspended;
the output end of one transmission gate is electrically connected with the input end of the transmission gate adjacent to the transmission gate; the input end of the transmission gate close to the Mth signal line in the two adjacent signal lines is electrically connected with the Mth signal line, and the output end of the transmission gate close to the (M +1) th signal line in the two adjacent signal lines is electrically connected with the (M +1) th signal line.
Optionally, the linkage device includes at least two second N-type thin film transistors connected in series;
the grid electrode of the second N-type thin film transistor is suspended;
the drain electrode of the second N-type thin film transistor is electrically connected with the source electrode of the second N-type thin film transistor adjacent to the drain electrode; the source electrode of the second N-type thin film transistor close to the Mth signal line in the two adjacent signal lines is electrically connected with the Mth signal line, and the drain electrode of the second N-type thin film transistor close to the M +1 th signal line in the two adjacent signal lines is electrically connected with the M +1 th signal line.
Optionally, the ESD device includes a third N-type thin film transistor and a second P-type thin film transistor; the grid electrode and the drain electrode of the third N-type thin film transistor are in short circuit and are both connected with a constant voltage low potential, and the source electrode is electrically connected with a corresponding signal wire; the grid electrode and the drain electrode of the second P-type thin film transistor are in short circuit and are both connected with a constant voltage high potential, and the source electrode is electrically connected with the corresponding signal wire.
Optionally, the ESD device includes a fourth N-type thin film transistor and a fifth N-type thin film transistor connected in series with the fourth N-type thin film transistor; the grid electrode and the drain electrode of the fourth N-type thin film transistor are in short circuit and are both connected with a constant voltage low potential, and the source electrode is electrically connected with the corresponding signal wire; and the grid electrode and the drain electrode of the fifth N-type thin film transistor are in short circuit and are electrically connected with the corresponding signal lines, and the source electrode is connected with a constant-voltage high potential.
Optionally, the linkage device includes two transmission gates connected in series;
the input end of the transmission gate close to the Mth signal line in the two adjacent signal lines is electrically connected with the Mth signal line, and the output end of the transmission gate close to the (M +1) th signal line in the two adjacent signal lines is electrically connected with the input end of the transmission gate; the output end of the transmission gate close to the (M +1) th signal line in the two adjacent signal lines is electrically connected with the (M +1) th signal line.
Optionally, the linkage device includes two second N-type thin film transistors connected in series;
the source electrode of the second N-type thin film transistor close to the Mth signal line in the two adjacent signal lines is electrically connected with the Mth signal line, and the drain electrode of the second N-type thin film transistor close to the M +1 th signal line in the two adjacent signal lines is electrically connected with the source electrode of the second N-type thin film transistor; and the drain electrode of the second N-type thin film transistor close to the (M +1) th signal line in the two adjacent signal lines is electrically connected with the (M +1) th signal line.
The signal lines are data lines or scanning lines.
The invention also provides a liquid crystal display panel which comprises the electrostatic protection circuit.
The invention has the beneficial effects that: the invention provides an electrostatic protection circuit.A corresponding ESD device connected with an Mth signal line is arranged on the Mth signal line, and a linkage device connected with the two signal lines is arranged between every two adjacent signal lines; the linkage device is used for conducting static electricity on the corresponding signal line to the signal line adjacent to the signal line, linkage of the ESD devices between the two adjacent signal lines is achieved, the multiple ESD devices on the multiple signal lines can play a protection role at the same time, the antistatic capacity of the ESD devices in the liquid crystal display panel can be enhanced, and greater flexibility can be provided for circuit layout of the liquid crystal display panel. The liquid crystal display panel provided by the invention comprises the electrostatic protection circuit, wherein the ESD device in the electrostatic protection circuit has stronger antistatic capability and larger flexibility of circuit layout.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
fig. 1 is a circuit diagram of a first type of conventional electrostatic protection circuit;
fig. 2 is a circuit diagram of a second type of conventional electrostatic protection circuit;
FIG. 3 is a circuit diagram of a first embodiment of an ESD protection circuit according to the present invention;
FIG. 4 is a schematic top view of a linkage device in the first embodiment of the ESD protection circuit according to the present invention;
FIG. 5 is a schematic diagram of a top view of a linkage device in the first embodiment of the ESD protection circuit according to the present invention when a signal line is working normally;
FIG. 6 is a schematic diagram illustrating a top view of the linkage device in the first embodiment of the ESD protection circuit according to the present invention when static electricity exists in the signal line;
FIG. 7 is a circuit diagram of a second embodiment of an electrostatic protection circuit of the present invention;
FIG. 8 is a schematic top view of a linkage device in a second embodiment of the ESD protection circuit according to the present invention;
FIG. 9 is a schematic diagram of a top view of a linkage device in a second embodiment of an ESD protection circuit according to the present invention when a signal line is working normally;
fig. 10 is a schematic top view of the linkage device in the second embodiment of the electrostatic protection circuit according to the present invention when electrostatic charge exists in the signal line.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
The present invention first provides an electrostatic protection circuit. Referring to fig. 3 to 6, assuming that M is a positive integer, the first embodiment of the electrostatic protection circuit of the present invention includes a plurality of signal lines L (M) (e.g., L (1), L (2), L (3), L (4), etc.), a plurality of ESD devices 1, and a plurality of linking devices 2, which are sequentially disposed.
An ESD device 1 electrically connected to the mth signal line l (M) is correspondingly disposed on the mth signal line l (M), for example: the first signal line L (1) is correspondingly provided with an ESD device 1 electrically connected with the first signal line L (1), the second signal line L (2) is correspondingly provided with an ESD device 1 electrically connected with the second signal line L (2), the third signal line L (3) is correspondingly provided with an ESD device 1 electrically connected with the third signal line L (3), the fourth signal line L (4) is correspondingly provided with an ESD device 1 electrically connected with the fourth signal line L (4), and so on.
A linkage device 2 electrically connected to the two signal lines L (M), L (M +1) is correspondingly disposed between every two adjacent signal lines L (M), L (M +1), for example: a linkage device 2 electrically connected with the 1 st signal line L (1) and the 2 nd signal line L (2) is correspondingly arranged between the 1 st signal line L (1) and the 2 nd signal line L (2), a linkage device 2 electrically connected with the 2 nd signal line L (2) and the 3 rd signal line L (3) is correspondingly arranged between the 2 nd signal line L (2) and the 3 rd signal line L (3), a linkage device 2 electrically connected with the 3 rd signal line L (2) and the 3 rd signal line L (3) is correspondingly arranged between the 3 rd signal line L (3) and the 4 th signal line L (4), and so on.
Specifically, in this first embodiment, the linkage 2 includes at least two transmission gates TG connected in series. The transmission gate TG comprises a first P-type thin film transistor T1 and a first N-type thin film transistor T2 arranged opposite to the first P-type thin film transistor T1; the gate G1 of the first P-type tft T1 is floating (i.e., no signal is inputted), the source S1 is electrically connected to the source S2 of the first N-type tft T2 as the input terminal of the transmission gate TG, and the drain D1 is electrically connected to the drain D2 of the first N-type tft T2 as the output terminal of the transmission gate TG; the gate G2 of the first N-type tft T2 is floating. The output end of one transmission gate TG is electrically connected with the input end of the transmission gate TG adjacent to the transmission gate TG; the input end of the transmission gate TG close to the mth signal line L (M) of the two adjacent signal lines L (M), L (M +1) is electrically connected to the mth signal line L (M), and the output end of the transmission gate TG close to the M +1 signal line L (M +1) of the two adjacent signal lines L (M), L (M +1) is electrically connected to the M +1 signal line L (M + 1).
Further, in conjunction with fig. 3 and 4, it is preferable that the linkage device 2 includes two transmission gates TG connected in series. The input end of the transmission gate TG close to the mth signal line L (M) of the two adjacent signal lines L (M), L (M +1) is electrically connected to the mth signal line L (M), and the output end of the transmission gate TG close to the M +1 signal line L (M +1) of the two adjacent signal lines L (M), L (M +1) is electrically connected to the input end of the transmission gate TG; the output end of the transmission gate TG close to the M +1 th signal line L (M +1) of the two adjacent signal lines L (M), L (M +1) is electrically connected to the M +1 th signal line L (M + 1).
Specifically, in the first embodiment, the ESD device 1 includes a third N-type thin film transistor T4 and a second P-type thin film transistor T5. The grid electrode G4 and the drain electrode D4 of the third N-type thin film transistor T4 are in short circuit and are both connected with a constant voltage low potential VGL, and the source electrode S4 is electrically connected with a corresponding signal line L (M); the gate G5 and the drain D5 of the second P-type tft T5 are shorted and both connected to a constant voltage VGH, and the source S5 is electrically connected to the corresponding signal line l (m). When the positive electrostatic charges on the signal line l (m) are accumulated to a certain extent such that the potential of the source electrode S5 of the second P-type thin film transistor T5 is higher than the constant voltage high potential VGH, the second P-type thin film transistor T5 is turned on to discharge the electrostatic charges; when negative electrostatic charges are accumulated on the signal line l (m) to a certain extent such that the potential of the source S4 of the third N-type thin film transistor T4 is lower than the constant voltage low potential VGL, the third N-type thin film transistor T4 is turned on to discharge the electrostatic charges.
The signal lines l (m) are not limited to data lines or scanning lines in the liquid crystal display panel.
In this embodiment, the ESD device 1 and the linkage device 2 both adopt CMOS processes.
With reference to fig. 3 and fig. 5, when each signal line l (m) normally operates, since the gate G1 of the first P-type tft T1 and the gate G2 of the first N-type tft T2 in the transmission gate TG of the link device 2 are floating, the transmission gate TG is in an off state, the current flowing through the transmission gate TG can be substantially ignored, and since the link device 2 includes at least two transmission gates TG connected in series, the crosstalk between adjacent signal lines can be avoided, and the normal operation of each signal line l (m) is not affected.
With reference to fig. 3 and fig. 6, when a signal line l (m) generates static electricity, the ESD device 1 on the signal line l (m) performs static electricity discharge, and meanwhile, because the gate G1 of the first P-type tft T1 and the gate G2 of the first N-type tft T2 of the transmission gate TG of the linking device 2 electrically connected to the signal line l (m) are floating, the floating gate attracts the static electricity to increase the current flowing through the transmission gate TG, and the transmission gate TG is in an open state, the static electricity on the signal line l (m) is conducted to the signal line adjacent to the floating gate, so that the ESD device 1 on the adjacent signal line also performs static electricity discharge, thereby achieving linking of the ESD devices 1 between the adjacent two signal lines; further, the static electricity on the adjacent signal lines can be conducted to more signal lines through the corresponding linkage device 2, and finally the multiple ESD devices 1 on the multiple signal lines l (m) can play a role of electrostatic protection at the same time, so that the antistatic capability of the ESD devices 1 in the liquid crystal display panel can be enhanced on the premise that the size of the ESD devices 1 is not increased, and greater flexibility can be provided for the circuit layout of the liquid crystal display panel.
For example, it is assumed that when the 2 nd signal line L (2) generates static electricity, the ESD device 1 on the 2 nd signal line L (2) performs static electricity discharge; meanwhile, the linkage device 2 electrically connected between the 2 nd signal line L (2) and the 3 rd signal line L (3) conducts the static electricity on the 2 nd signal line L (2) to the 3 rd signal line L (3), and the ESD device 1 on the 3 rd signal line L (3) performs electrostatic discharge; the linkage device 2 electrically connected between the 2 nd signal line L (2) and the 1 st signal line L (1) conducts static electricity on the 2 nd signal line L (2) to the 1 st signal line L (1), and the ESD device 1 on the 1 st signal line L (1) carries out static electricity discharge; further, the static electricity on the 3 rd signal line L (3) is conducted to the 4 th signal line L (4) through the linkage device 2 electrically connected between the 3 rd signal line L (3) and the 4 th signal line L (4), and so on until the static electricity discharge is completed.
Referring to fig. 7 to fig. 10, a second embodiment of an electrostatic protection circuit according to the present invention is different from the first embodiment in that:
firstly, the linkage device 2 comprises at least two second N-type thin film transistors T3 connected in series. The gate G3 of the second N-type tft T3 is floating. The drain D3 of a second N-type tft T3 is electrically connected to the source S3 of the adjacent second N-type tft T3; the source S3 of the second N-type tft T3 close to the mth signal line L (M) of the two adjacent signal lines L (M), L (M +1) is electrically connected to the mth signal line L (M), and the drain D3 of the second N-type tft T3 close to the M +1 signal line L (M +1) of the two adjacent signal lines L (M), L (M +1) is electrically connected to the M +1 signal line L (M + 1).
Further, with reference to fig. 7 and 8, it is preferable that the linkage device 2 includes two second N-type tfts T3 connected in series. The source S3 of the second N-type tft T3 close to the mth signal line L (M) of the two adjacent signal lines L (M), L (M +1) is electrically connected to the mth signal line L (M), and the drain D3 is electrically connected to the source S3 of the second N-type tft T3 close to the M +1 signal line L (M +1) of the two adjacent signal lines L (M), L (M + 1); the drain D3 of the second N-type tft T3 close to the M +1 th signal line L (M +1) of the two adjacent signal lines L (M), L (M +1) is electrically connected to the M +1 th signal line L (M + 1).
Secondly, the ESD device 1 includes a fourth N-type thin film transistor T6, and a fifth N-type thin film transistor T7 connected in series with the fourth N-type thin film transistor T6; the gate G6 and the drain D6 of the fourth N-type tft T6 are shorted, and both are connected to a constant voltage low voltage VGL, and the source S6 is electrically connected to the corresponding signal line l (m); the gate G7 and the drain D7 of the fifth N-type tft T7 are shorted and electrically connected to the corresponding signal line l (m), and the source S7 is connected to the constant-voltage high-voltage VGH. When positive electrostatic charges are accumulated on the signal line l (m) to such an extent that the potential of the gate G7 of the fifth N-type thin film transistor T7 is higher than the constant voltage high potential VGH, the fifth N-type thin film transistor T7 is turned on to discharge the electrostatic charges; when negative electrostatic charges are accumulated on the signal line l (m) to a certain extent such that the potential of the source electrode S6 of the fourth N-type thin film transistor T6 is lower than the constant voltage low potential VGL, the fourth N-type thin film transistor T6 is turned on to discharge the electrostatic charges.
In this embodiment, the ESD device 1 and the linking device 2 both adopt an NMOS process.
With reference to fig. 7 and 9, when each signal line l (m) normally operates, since the gate G3 of each second N-type thin film transistor T3 in the linking device 2 is floating, and each second N-type thin film transistor T3 is in an off state, the current flowing through the second N-type thin film transistor T3 can be substantially ignored, and since the linking device 2 includes at least two second N-type thin film transistors T3 connected in series, the crosstalk between adjacent signal lines can be avoided, and the normal operation of each signal line l (m) is not affected.
With reference to fig. 7 and 10, when a signal line l (m) generates static electricity, the ESD device 1 on the signal line l (m) performs static electricity discharge, and meanwhile, because the gates G3 of the second N-type tfts T3 of the linking device 2 electrically connected to the signal line l (m) are suspended, the suspended gates attract the static electricity to increase the current flowing through the second N-type tfts T3, so that the static electricity on the signal line l (m) is conducted to the signal line adjacent to the signal line, so that the ESD device 1 on the adjacent signal line also performs static electricity discharge, thereby achieving the linking of the ESD devices 1 between the two adjacent signal lines; further, the static electricity on the adjacent signal lines can be conducted to more signal lines through the corresponding linkage device 2, and finally the multiple ESD devices 1 on the multiple signal lines l (m) can play a role of electrostatic protection at the same time, so that the antistatic capability of the ESD devices 1 in the liquid crystal display panel can be enhanced on the premise that the size of the ESD devices 1 is not increased, and greater flexibility can be provided for the circuit layout of the liquid crystal display panel.
For example, it is assumed that when the 2 nd signal line L (2) generates static electricity, the ESD device 1 on the 2 nd signal line L (2) performs static electricity discharge; meanwhile, the linkage device 2 electrically connected between the 2 nd signal line L (2) and the 3 rd signal line L (3) conducts the static electricity on the 2 nd signal line L (2) to the 3 rd signal line L (3), and the ESD device 1 on the 3 rd signal line L (3) performs electrostatic discharge; the linkage device 2 electrically connected between the 2 nd signal line L (2) and the 1 st signal line L (1) conducts static electricity on the 2 nd signal line L (2) to the 1 st signal line L (1), and the ESD device 1 on the 1 st signal line L (1) carries out static electricity discharge; further, the static electricity on the 3 rd signal line L (3) is conducted to the 4 th signal line L (4) through the linkage device 2 electrically connected between the 3 rd signal line L (3) and the 4 th signal line L (4), and so on until the static electricity discharge is completed.
Of course, if the influence of the manufacturing process is not considered, the ESD device 1 formed by the fourth N-type thin film transistor T6 and the fifth N-type thin film transistor T7 in the second embodiment may be collocated with the linking device 2 including at least two transmission gates TG connected in series in the first embodiment to form an electrostatic protection circuit; or the interlocking device 2 including at least two second N-type thin film transistors T3 connected in series in the second embodiment is matched with the ESD device 1 including the third N-type thin film transistor T4 and the second P-type thin film transistor T5 in the first embodiment to form an electrostatic protection circuit, so that the purpose of enhancing the antistatic capability of the ESD device in the liquid crystal display panel and providing greater flexibility for the circuit layout of the liquid crystal display panel can be achieved.
Based on the same inventive concept, the invention also provides a liquid crystal display panel, which comprises any one of the electrostatic protection circuits, so that the ESD device in the liquid crystal display panel has stronger antistatic capability and the flexibility of circuit layout is higher. The electrostatic protection circuit will not be described repeatedly herein.
In summary, in the electrostatic protection circuit of the present invention, an ESD device electrically connected to an mth signal line is correspondingly disposed on the mth signal line, and a linking device electrically connected to the two signal lines is correspondingly disposed between every two adjacent signal lines; the linkage device is used for conducting static electricity on the corresponding signal line to the signal line adjacent to the signal line, linkage of the ESD devices between the two adjacent signal lines is achieved, the multiple ESD devices on the multiple signal lines can play a protection role at the same time, the antistatic capacity of the ESD devices in the liquid crystal display panel can be enhanced, and greater flexibility can be provided for circuit layout of the liquid crystal display panel. The liquid crystal display panel comprises the electrostatic protection circuit, and an ESD device in the electrostatic protection circuit has stronger antistatic capacity and higher flexibility of circuit layout.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications should fall within the scope of the claims of the present invention.
Claims (4)
1. An electrostatic protection circuit is characterized by comprising a plurality of signal lines (L (M)), a plurality of ESD devices (1) and a plurality of linkage devices (2), wherein the signal lines (L (M)) are sequentially distributed;
setting M as a positive integer, correspondingly arranging an ESD device (1) electrically connected with the Mth signal line (L) (M) on the Mth signal line (L (M)), and arranging a linkage device (2) electrically connected with the two signal lines (L (M) and L (M +1)) between every two adjacent signal lines (L (M) and L (M + 1));
the ESD device (1) is used for electrostatic discharge; the linkage device (2) is used for conducting static electricity on the Mth signal line (L (M)) to the signal line adjacent to the Mth signal line (L (M)), so that linkage of the ESD device (1) between the two adjacent signal lines is realized;
the linkage device (2) comprises at least two Transmission Gates (TG) which are connected in series, and crosstalk between adjacent signal lines can be avoided;
the Transmission Gate (TG) comprises a first P-type thin film transistor (T1) and a first N-type thin film transistor (T2) which is arranged opposite to the first P-type thin film transistor (T1); a gate (G1) of the first P-type thin film transistor (T1) is floating, a source (S1) of the first P-type thin film transistor (T1) is electrically connected to a source (S2) of the first N-type thin film transistor (T2) to serve as an input terminal of the Transmission Gate (TG), and a drain (D1) of the first P-type thin film transistor (T1) is electrically connected to a drain (D2) of the first N-type thin film transistor (T2) to serve as an output terminal of the Transmission Gate (TG); the grid electrode (G2) of the first N-type thin film transistor (T2) is suspended;
the output end of one Transmission Gate (TG) is electrically connected with the input end of the Transmission Gate (TG) adjacent to the Transmission Gate (TG); the input end of the Transmission Gate (TG) close to the Mth signal line (L (M)) in the two adjacent signal lines (L (M), L (M +1)) is electrically connected with the Mth signal line (L (M)), and the output end of the Transmission Gate (TG) close to the Mth +1 signal line (L (M +1)) in the two adjacent signal lines (L (M), L (M +1)) is electrically connected with the M +1 signal line (L (M + 1));
the ESD device (1) comprises an N-type thin film transistor (T4) and a P-type thin film transistor (T5); a grid electrode (G4) of an N-type thin film transistor (T4) of the ESD device (1) is in short circuit connection with a drain electrode (D4) of an N-type thin film transistor (T4) of the ESD device (1), the grid electrode and the drain electrode are both connected to a constant voltage low potential (VGL), and a source electrode (S4) of the N-type thin film transistor (T4) of the ESD device (1) is electrically connected with a corresponding signal line (L (M)); the grid electrode (G5) of the P-type thin film transistor (T5) of the ESD device (1) is in short circuit connection with the drain electrode (D5) of the P-type thin film transistor (T5) of the ESD device (1), the grid electrode and the drain electrode are both connected to a constant voltage high potential (VGH), and the source electrode (S5) of the P-type thin film transistor (T5) of the ESD device (1) is electrically connected with a corresponding signal line (L (M));
or the ESD device (1) comprises a first N-type thin film transistor (T6) and a second N-type thin film transistor (T7) connected in series with the first N-type thin film transistor (T6); the grid electrode (G6) of the first N-type thin film transistor (T6) is in short circuit with the drain electrode (D6) of the first N-type thin film transistor (T6), the grid electrode and the drain electrode are both connected with a constant voltage low potential (VGL), and the source electrode (S6) of the first N-type thin film transistor (T6) is electrically connected with a corresponding signal line (L (M)); the grid electrode (G7) of the second N-type thin film transistor (T7) is in short circuit with the drain electrode (D7) of the second N-type thin film transistor (T7) and is electrically connected with the corresponding signal line (L (M)), and the source electrode (S7) of the second N-type thin film transistor (T7) is connected with a constant voltage high potential (VGH).
2. An electrostatic protection circuit according to claim 1, characterized in that the linkage means (2) comprise two Transmission Gates (TG) connected in series;
the input end of the Transmission Gate (TG) close to the Mth signal line (L (M)) in the two adjacent signal lines (L (M), L (M +1)) is electrically connected with the Mth signal line (L (M)), and the output end of the Transmission Gate (TG) close to the Mth signal line (L (M +1)) in the two adjacent signal lines (L (M), L (M +1)) is electrically connected with the input end of the Transmission Gate (TG); the output end of the Transmission Gate (TG) close to the M +1 th signal line (L (M +1)) in the two adjacent signal lines (L (M), L (M +1)) is electrically connected with the M +1 th signal line (L (M + 1)).
3. The electrostatic protection circuit according to claim 1, wherein the signal line (l (m)) is a data line or a scan line.
4. A liquid crystal display panel comprising the electrostatic protection circuit according to any one of claims 1 to 3.
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| CN107895941A (en) * | 2017-11-27 | 2018-04-10 | 武汉华星光电技术有限公司 | Esd protection circuit and display panel |
| CN108732839B (en) * | 2018-05-30 | 2021-09-24 | 南京京东方显示技术有限公司 | Electrostatic protection circuit, electrostatic protection module and liquid crystal display device |
| CN108803167A (en) * | 2018-05-30 | 2018-11-13 | 南京中电熊猫平板显示科技有限公司 | Electrostatic discharge protection circuit, electrostatic protection module and liquid crystal display device |
| CN112530937B (en) * | 2020-12-02 | 2022-09-27 | Tcl华星光电技术有限公司 | Electrostatic protection circuit and display panel |
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| TWI308248B (en) * | 2005-11-09 | 2009-04-01 | Au Optronics Corp | Display device and configuration of common electrode thereof |
| TWI350422B (en) * | 2007-04-25 | 2011-10-11 | Au Optronics Corp | Active device array substrate |
| JP5662114B2 (en) * | 2010-11-17 | 2015-01-28 | 株式会社ジャパンディスプレイ | Display device |
| CN202259302U (en) * | 2011-10-27 | 2012-05-30 | 京东方科技集团股份有限公司 | Electrostatic protection circuit, array substrate and display device |
| CN202550507U (en) * | 2012-03-15 | 2012-11-21 | 京东方科技集团股份有限公司 | Electrostatic protection circuit, array substrate and display device |
| CN103268876B (en) * | 2012-09-27 | 2016-03-30 | 厦门天马微电子有限公司 | Static release protection circuit, display floater and display unit |
| CN103199513B (en) * | 2013-02-22 | 2016-04-06 | 合肥京东方光电科技有限公司 | Electrostatic discharge protective circuit, display unit and electrostatic protection method |
| US9368500B2 (en) * | 2013-11-05 | 2016-06-14 | United Microelectronics Corp. | Complementary metal-oxide-semiconductor device |
| CN103944154A (en) * | 2013-12-11 | 2014-07-23 | 厦门天马微电子有限公司 | Electrostatic protection circuit and liquid crystal displayer |
| KR102219516B1 (en) * | 2014-04-10 | 2021-02-25 | 삼성디스플레이 주식회사 | Display substrate |
| KR102252147B1 (en) * | 2014-09-23 | 2021-05-14 | 엘지디스플레이 주식회사 | Electostatic discharge circuit |
| CN105093739A (en) * | 2015-07-30 | 2015-11-25 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and antistatic array substrate thereof |
| CN105304645B (en) * | 2015-10-16 | 2018-02-27 | 京东方科技集团股份有限公司 | A kind of array base palte, its electrostatic release method and related device |
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| CN206040646U (en) * | 2016-04-26 | 2017-03-22 | 京东方科技集团股份有限公司 | Electrostatic protection and test combined unit , array substrate and display device |
| CN105813365B (en) * | 2016-05-23 | 2018-01-02 | 京东方科技集团股份有限公司 | A kind of electrostatic discharge protective circuit, display panel and display device |
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