CN107290594B - Test structure and its test method - Google Patents
Test structure and its test method Download PDFInfo
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- CN107290594B CN107290594B CN201610208066.9A CN201610208066A CN107290594B CN 107290594 B CN107290594 B CN 107290594B CN 201610208066 A CN201610208066 A CN 201610208066A CN 107290594 B CN107290594 B CN 107290594B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2605—Measuring capacitance
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Abstract
A kind of test structure and its test method, the test structure include: substrate, including first area, second area and third region;First test structure of first area, including several gate structures, the intrabasement doped region in gate structure two sides, the second connection structure between first connection structure and the first connection structure at first area both ends, the first connection structure and the second connection structure include the contact plunger being connected with doped region and the metal layer that is connected with contact plunger;Second test structure of second area, the 4th connection structure between third connection structure and third connection structure including second area both ends are only that the 4th connection structure includes the contact plunger being connected with doped region with the difference of the first test structure;The third in third region tests structure, and the difference with the second test structure is only that the second test structure has the 4th connection structure.By the test structure, the parasitic capacitance of transistor can be accurately obtained.
Description
Technical field
The present invention relates to semiconductor field more particularly to a kind of test structures and its test method.
Background technique
With integrated and semiconductor devices the micromation of integrated circuit, the performance of transistor is for integrated circuit
Influence it is more significant.In the factor for influencing transistor performance, parasitic capacitance can be to the semiconductor devices formed by transistor
Working efficiency have an impact.Therefore, it is necessary to the parasitic capacitances to the transistor to test, to post described in reducing as far as possible
The size of raw capacitor.
But the prior art is complicated for the test method of transistor parasitic capacitance, and is difficult precisely to obtain the parasitism
Capacitance.
Summary of the invention
Problems solved by the invention is to provide a kind of test structure and its test method, effectively obtains the parasitism electricity of transistor
Capacitance.
To solve the above problems, the present invention provides a kind of test structure, comprising: substrate, including first area, second area
With third region;Well region is located in the substrate;Structure, the first test knot are tested positioned at the first of the first area
Structure includes the dry gate structure for being located at first area well region surface, and it is intrabasement several to be located at the gate structure two sides
A the first connection structure and the first connection knot as source region or the doped region in drain region, positioned at the first area both ends
The second connection structure between structure, first connection structure include the contact plunger being connected with the doped region and with institute
State the metal layer that contact plunger is connected, second connection structure include the contact plunger being connected with the doped region and
The metal layer being connected with the contact plunger, wherein the well region is identical as the doping type of the doped region;Positioned at described
Second test structure of second area, the second test structure include the grid that several are located at second area well region surface
Pole structure, positioned at the gate structure two sides it is intrabasement several as source region or the doped region in drain region, be located at described second
The 4th connection structure between the third connection structure at region both ends and the third connection structure, the third connection structure
Including the contact plunger being connected with the doped region and the metal layer being connected with the contact plunger, the 4th connection
Structure includes the contact plunger being connected with the doped region, wherein the well region is identical as the doping type of the doped region;
Third positioned at the third region tests structure, and the third test structure includes that several are located at third region well region
The gate structure on surface, positioned at the gate structure two sides it is intrabasement several as source region or the doped region in drain region, and
The 5th connection structure positioned at third region both ends, the 5th connection structure includes connecing with what the doped region was connected
Touching plug and the metal layer being connected with the contact plunger, wherein the doping type phase of the well region and the doped region
Together.
Optionally, first connection structure, third connection structure and the 5th connection structure are identical structure.
Optionally, the formation work of the gate structure of the first test structure, the second test structure and third test structure
Skill, material and size are identical, and the first test structure, the second test structure and third test the formation of the contact plunger of structure
Technique, material and size are identical, and the first test structure, the second test structure and third test the formation of the metal layer of structure
Technique, material and size are identical.
Optionally, the quantity phase of the gate structure of the first test structure, the second test structure and third test structure
Deng.
Optionally, the quantity of the gate structure of the first test structure, the second test structure and third test structure is n
A, n is the natural number equal to or more than 2.
Optionally, the quantity of the doped region is n+1;The quantity of second connection structure is n-1;Described 4th
The quantity of connection structure is n-1.
Optionally, the test structure is fin field effect pipe structure, and the substrate includes substrate and protrudes from described
The fin of substrate, the gate structure are located at the fin portion surface, and the doped region is located at the fin of the gate structure two sides
It is interior;Alternatively, the test structure is planar transistor structure, the substrate is substrate, and the gate structure is located at the substrate
Surface, the doped region are located in the substrate of the gate structure two sides.
Optionally, the test structure further includes stressor layers, and the doped region is formed in the stressor layers.
Optionally, the doped region further includes the overlapping region below the gate structure.
Correspondingly, the present invention also provides a kind of test methods, comprising: provide test structure of the present invention;It surveys respectively
Obtain the first test structure, the capacitance of the second test structure and third test structure;Pass through the first test structure
The difference of the capacitance of capacitance and the second test structure, obtains the first testing capacitor value, the first testing capacitor value
For the capacitance between the gate structure and the adjacent metal layer;By it is described second test structure capacitance with it is described
Third tests the difference of the capacitance of structure, obtains the second testing capacitor value, and the second testing capacitor value is the grid knot
Capacitance between structure and the adjacent contact plunger;The capacitance of structure and described first, which is tested, by the third tests electricity
The difference of capacitance and the second testing capacitor value, obtains third testing capacitor value, and the third testing capacitor value is the grid
Capacitance between structure and the adjacent doping area edge.
Optionally, obtain the second testing capacitor value the step of in, it is described second test structure capacitance with it is described
The difference of the capacitance of third test structure is 2 × (n-1) times of the second testing capacitor value.
Optionally, obtain the first testing capacitor value the step of in, it is described first test structure capacitance with it is described
The difference of the capacitance of second test structure is 2 × (n-1) times of the first testing capacitor value.
Optionally, in the step of obtaining the third testing capacitor value, the capacitance of the third test structure and 2 times of institutes
The difference of the second testing capacitor value and 2 times of the first testing capacitor values is stated, is 2n times of the third testing capacitor value.
Optionally, the test method further include: pass through the first testing capacitor value, the second testing capacitor value and third
Testing capacitor value, obtains the 4th testing capacitor value, and the 4th testing capacitor value is the gate structure and the adjacent doping
The overlap capacitance value in area.
Optionally, the step of obtaining the 4th testing capacitor value includes: to provide the test of gate structure to drain region capacitor
Structure;By the test structure of the gate structure to drain region capacitor, the 5th testing capacitor value, the 5th testing capacitor are obtained
The capacitance being worth between the gate structure and drain region;The 5th testing capacitor value subtract the second testing capacitor value,
First testing capacitor value and third testing capacitor value obtain the 4th testing capacitor value.
Compared with prior art, technical solution of the present invention has the advantage that
The present invention passes through the test structure of three kinds of different structures, wherein the first test structure and the second test structure
Difference be only that the second connection structure of the first test structure and the 4th connection structure of the second test structure, described the
Two connection structures include the contact plunger being connected with the doped region and the metal layer that is connected with the contact plunger, institute
Stating the 4th connection structure includes the contact plunger being connected with the doped region, therefore, passes through the electricity of the first test structure
The difference of the capacitance of capacitance and the second test structure, can obtain the first testing capacitor value, first testing capacitor
The capacitance being worth between the gate structure and the adjacent metal layer;The second test structure and third test structure
Difference is only that the second test structure has the 4th connection structure, and the 4th connection structure includes and the doped region phase
Therefore the contact plunger of connection tests the capacitance of structure by the capacitance and the third of the second test structure
Difference, can obtain the second testing capacitor value, and the second testing capacitor value is that the gate structure is inserted with adjacent described contact
Capacitance between plug finally can test the capacitance of structure by third and the second testing capacitor value and first are surveyed
Try capacitance difference, obtain third testing capacitor value, the third testing capacitor value be the gate structure with it is adjacent described
The capacitance between area edge is adulterated, so as to accurately obtain the parasitic capacitance of the transistor.
In optinal plan, by using the test structure of gate structure to drain region capacitor, the 5th testing capacitor can be obtained
Value, capacitance of the 5th testing capacitor value between the gate structure and drain region, then by the 5th testing capacitor
Value subtracts the second testing capacitor value, the first testing capacitor value and third testing capacitor value, obtains the 4th testing capacitor value,
The 4th testing capacitor value is the overlap capacitance value of the gate structure and the adjacent doped region, may further obtain institute
State the parasitic capacitance of transistor.
Detailed description of the invention
Fig. 1 to Fig. 4 is corresponding structural schematic diagram in present invention test one embodiment of structure.
Specific embodiment
As stated in the background art, the prior art is complicated for the test method of transistor parasitic capacitance, and is difficult precisely to obtain
Take the parasitic capacitance value.
With the continuous reduction of device feature size, the short channel effect of device is increasingly severe.In order to preferably adapt to spy
The reduction of size is levied, semiconductor technology gradually starts from planar MOSFET transistor to the three-dimensional with more high effect
Transistor transient, such as fin field effect pipe (FinFET), with the short channel effect of suppression device.Correspondingly, using FinFET as representative
Three-dimensional transistor in, the contact plunger that is connected with source region and drain region uses slot (trench) structure, that is, adopts
With contact groove plug, the contact groove plug can reduce the resistance in source region and drain region, but also considerably increase crystal simultaneously
The parasitic capacitance of pipe.Wherein, the parasitic capacitance mainly include gate structure and positioned at the gate structure two sides source region or
Capacitor, gate structure between the edge of drain region and the capacitor between the contact plunger on source region or drain region surface, gate structure
Capacitor and gate structure between the metal layer on contact plunger and the fractional source regions below the gate structure or
Overlap capacitance between drain region.And during actual measurement, it is difficult to directly measure and individually obtain the above capacitance.
In order to solve the technical problem, the present invention provides a kind of test structure, comprising: substrate, including first area,
Two regions and third region;Well region is located in the substrate;The first test structure positioned at the first area, described first
Test structure includes the dry gate structure for being located at first area well region surface, is located in the substrate of the gate structure two sides
Several as source region or the doped region in drain region, positioned at first connection structure at the first area both ends and described first
The second connection structure between connection structure, first connection structure include the contact plunger that is connected with the doped region with
And the metal layer being connected with the contact plunger, second connection structure include that the contact being connected with the doped region is inserted
Plug and the metal layer being connected with the contact plunger, wherein the well region is identical as the doping type of the doped region;Position
Structure is tested in the second of the second area, the second test structure includes that several are located at the second area well region table
The gate structure in face, positioned at the gate structure two sides it is intrabasement several as source region or the doped region in drain region, be located at institute
The 4th connection structure between the third connection structure and the third connection structure at second area both ends is stated, the third connects
Binding structure includes the contact plunger being connected with the doped region and the metal layer that is connected with the contact plunger, and described
Four connection structures include the contact plunger being connected with the doped region, wherein the doping class of the well region and the doped region
Type is identical;Third positioned at the third region tests structure, and the third test structure includes that several are located at the third
The gate structure on region well region surface, positioned at several intrabasement doping as source region or drain region of the gate structure two sides
Area, and the 5th connection structure positioned at third region both ends, the 5th connection structure include and the doped region phase
The contact plunger of connection and the metal layer being connected with the contact plunger, wherein the well region is mixed with the doped region
Miscellany type is identical.
The present invention passes through the test structure of three kinds of different structures, wherein the first test structure and the second test structure
Difference be only that the second connection structure of the first test structure and the 4th connection structure of the second test structure, described the
Two connection structures include the contact plunger being connected with the doped region and the metal layer that is connected with the contact plunger, institute
Stating the 4th connection structure includes the contact plunger being connected with the doped region, therefore, passes through the electricity of the first test structure
The difference of the capacitance of capacitance and the second test structure, can obtain the first testing capacitor value, first testing capacitor
The capacitance being worth between the gate structure and the adjacent metal layer;The second test structure and third test structure
Difference is only that the second test structure has the 4th connection structure, and the 4th connection structure includes and the doped region phase
Therefore the contact plunger of connection tests the capacitance of structure by the capacitance and the third of the second test structure
Difference, can obtain the second testing capacitor value, and the second testing capacitor value is that the gate structure is inserted with adjacent described contact
Capacitance between plug finally can test the capacitance of structure by third and the second testing capacitor value and first are surveyed
Try capacitance difference, obtain third testing capacitor value, the third testing capacitor value be the gate structure with it is adjacent described
The capacitance between area edge is adulterated, so as to accurately obtain the parasitic capacitance of the transistor.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Fig. 4 is corresponding structural schematic diagram in present invention test one embodiment of structure.
In conjunction with referring to figs. 1 to Fig. 3, the test structure includes: substrate (not indicating), the substrate include first area I,
Second area II and third region III;Well region 200 is located in the substrate.
In the present embodiment, the first area I, second area II and third region III are non-conterminous region.In another reality
It applies in example, the first area I, second area II and third region III can also be adjacent area, and pass through isolation structure
120 are isolated.
In the present embodiment, the test structure is fin field effect pipe structure, and the substrate includes substrate 100 and protrusion
In the fin 110 of the substrate 100, the substrate further includes the isolation structure 120 positioned at 100 surface of substrate, it is described every
It is used for from structure 120 to playing buffer action between adjacent devices.
The material of the isolation structure 120 can be silica, silicon nitride or silicon oxynitride.In the present embodiment, it is described every
Material from structure 120 is silica.
The material of the substrate 100 is silicon, germanium, SiGe, silicon carbide, GaAs or gallium indium, and the substrate 100 can also
It is enough the germanium substrate on the silicon substrate or insulator on insulator;The material of the fin 110 includes silicon, germanium, SiGe, carbon
SiClx, GaAs or gallium indium.In the present embodiment, the substrate 100 is silicon substrate, and the material of the fin 110 is silicon.
In other embodiments, the test structure can also be planar transistor structure, and the substrate is substrate.
In the present embodiment, the doping type of the well region 200 of the first area I, second area II and third region III and
Doping concentration is identical.
As shown in Figure 1, the test structure further include: first positioned at the first area I tests structure (not indicating).
The first test structure includes the gate structure 130 that several are located at 200 surface of first area I well region,
Positioned at 130 two sides of gate structure it is intrabasement several as source region or the doped region 140 in drain region, be located at firstth area
The second connection structure 320 between first connection structure 310 and first connection structure 310 at the domain both ends I.
In the present embodiment, the well region 200 is identical as the doping type of the first area I doped region 140, to make institute
Mutual conduction between the transistor of first area I is stated, the parasitic capacitance of all transistors can be obtained simultaneously during the test
Value.
In the present embodiment, the quantity of the gate structure 130 of the first test structure is n, and n is equal to or more than 2
Natural number.Correspondingly, the quantity of the first area I doped region 140 is n+1, the quantity of second connection structure 320 is
N-1.
In a specific embodiment, it is described first test structure gate structure 130 quantity be 5, described first
The quantity of region I doped region 140 is 6, and the quantity of second connection structure 320 is 4.
It should be noted that the first test structure further includes being located at 110 intersection of the isolation structure 120 and fin
Pseudo- grid structure 135, for improving the formation quality of the doped region 140.
In the present embodiment, the test structure is fin field effect pipe structure, correspondingly, the gate structure 130 is located at
110 surface of fin, the doped region 140 are located in the fin 110 of 130 two sides of gate structure.
In another embodiment, the test structure is planar transistor structure, and the substrate is substrate, correspondingly, institute
It states gate structure and is located at the substrate surface, the doped region is located in the substrate of the gate structure two sides.
It should be noted that the first test structure further includes stressor layers (not shown), the doped region 140 is formed in
In the stressor layers, and the doped region 140 further includes the overlapping region (not shown) positioned at 130 lower section of gate structure
First connection structure 310 includes the contact plunger 150 being connected with the doped region 140 and connects with described
The metal layer 160 that touching plug 150 is connected, second connection structure 320 includes the contact being connected with the doped region 140
Plug 150 and the metal layer 160 being connected with the contact plunger 150.
In the present embodiment, the contact plunger 150 is slot (trench) structure, as contact groove plug.In another implementation
In example, the contact plunger can also be contact hole plug.
As shown in Fig. 2, the test structure further include: the second test structure positioned at the second area II (is not marked
Show).
The second test structure includes the gate structure 130 that several are located at 200 surface of second area II well region,
Positioned at 130 two sides of gate structure it is intrabasement several as source region or the doped region 140 in drain region, be located at secondth area
The 4th connection structure 340 between the third connection structure 330 at the domain both ends II and the third connection structure 330.
In the present embodiment, the well region 200 is identical as the doping type of the second area II doped region 140, to make
Mutual conduction between the transistor of the second area II can obtain the parasitism electricity of all transistors simultaneously during the test
Capacitance.
In the present embodiment, the quantity of the gate structure 130 of the first test structure and the second test structure is equal.Accordingly
, the quantity of the gate structure 130 of the second test structure is n, and n is the natural number equal to or more than 2, secondth area
The quantity of domain II doped region 140 is n+1, and the quantity of the 4th connection structure 340 is n-1.
In a specific embodiment, it is described second test structure gate structure 130 quantity be 5, described second
The quantity of region II doped region 140 is 6, and the quantity of the 4th connection structure 340 is 4.
It should be noted that the second test structure further includes being located at 110 intersection of the isolation structure 120 and fin
Pseudo- grid structure 135, for improving the formation quality of the doped region 140.
It should also be noted that, the formation process of the gate structure 130 of the first test structure and the second test structure,
Material is identical with size, and the first test structure is identical with the formation process of the doped region 140 of the second test structure, and described the
One test structure and the formation process of the contact plunger 150 of the second test structure, material are identical with size, the first test knot
The formation process of structure and the metal layer 160 of the second test structure, material are identical with size.
It should also be noted that, the third connection structure 330 and the first connection structure 310 are identical structure.
In the present embodiment, the test structure is fin field effect pipe structure, correspondingly, the gate structure 130 is located at
110 surface of fin, the doped region 140 are located in the fin 110 of 130 two sides of gate structure.
In another embodiment, the test structure is planar transistor structure, and the substrate is substrate, correspondingly, institute
It states gate structure and is located at the substrate surface, the doped region is located in the substrate of the gate structure two sides.
It should be noted that the second test structure further includes stressor layers (not shown), the doped region 140 is formed in
In the stressor layers, and the doped region 140 further includes the overlapping region (not shown) positioned at 130 lower section of gate structure
In the present embodiment, the third connection structure 330 includes the contact plunger 150 being connected with the doped region 140
And the metal layer 160 being connected with the contact plunger 150, the 4th connection structure 340 include and the doped region 140
The contact plunger 150 being connected.
In the present embodiment, the contact plunger 150 is slot (trench) structure, as contact groove plug.In another implementation
In example, the contact plunger can also be contact hole plug.
As shown in figure 3, the test structure further include: the third test structure positioned at the third region III (is not marked
Show).
The third test structure includes the gate structure that several are located at 200 surface of third region III well region
130, positioned at 130 two sides of gate structure it is intrabasement several as source region or the doped region 140 in drain region, and be located at institute
The 5th connection structure 350 at the third region both ends III is stated, the 5th connection structure 350 includes being connected with the doped region 140
The contact plunger 150 connect and the metal layer 160 being connected with the contact plunger 150.
In the present embodiment, the well region 200 is identical as the doping type of the third region III doped region 140, to make
Mutual conduction between the transistor of the third region III can obtain the parasitism of all transistors simultaneously during the test
Capacitance.
In the present embodiment, the first test structure, the second test structure and third test the gate structure 130 of structure
Quantity is equal.Correspondingly, the quantity of the gate structure 130 of the third test structure is n, n is the nature equal to or more than 2
Number, the quantity of the third region III doped region 140 are n+1.
In a specific embodiment, the quantity of the gate structure 130 of the third test structure is 5, the third
The quantity of region III doped region 140 is 6.
It should be noted that the third test structure further includes being located at 110 intersection of the isolation structure 120 and fin
Pseudo- grid structure 135, for improving the formation quality of the doped region 140.
It should also be noted that, the gate structure of the first test structure, the second test structure and third test structure
130 formation process, material are identical with size, and the first test structure, the second test structure and third test structure are mixed
The formation process in miscellaneous area 140 is identical, the contact plunger of the first test structure, the second test structure and third test structure
150 formation process, material are identical with size, the gold of the first test structure, the second test structure and third test structure
Formation process, the material for belonging to layer 160 are identical with size.
It should also be noted that, first connection structure 310, third connection structure 330 and the 5th connection structure 350 are
Identical structure.
In the present embodiment, the test structure is fin field effect pipe structure, correspondingly, the gate structure 130 is located at
110 surface of fin, the doped region 140 are located in the fin 110 of 130 two sides of gate structure.
In another embodiment, the test structure is planar transistor structure, and the substrate is substrate, correspondingly, institute
It states gate structure and is located at the substrate surface, the doped region is located in the substrate of the gate structure two sides.
It should be noted that the third test structure further includes stressor layers (not shown), the doped region 140 is formed in
In the stressor layers, and the doped region 140 further includes the overlapping region (not shown) positioned at 130 lower section of gate structure
In the present embodiment, the contact plunger 150 is slot (trench) structure, as contact groove plug.In another implementation
In example, the contact plunger can also be contact hole plug.
In conjunction with referring to figs. 1 to Fig. 4, correspondingly, the present invention also provides a kind of test methods, comprising:
Test structure of the present invention is provided;
Capacitance C1, the second test structure (as shown in Figure 2) of first test structure (as shown in Figure 1) are measured respectively
Capacitance C2 and third test structure (as shown in Figure 3) capacitance C3;
By the difference of the capacitance C2 of the capacitance C1 and the second test structure of the first test structure, obtain
First testing capacitor value Cgm (as shown in Figure 4), the first testing capacitor value Cgm be the gate structure 130 with it is adjacent described
Capacitance between metal layer 160;
The difference that the capacitance C3 of structure is tested by the capacitance C2 and the third of the second test structure, obtains
Second testing capacitor value Cgt (as shown in Figure 4), the second testing capacitor value Cgt be the gate structure 130 with it is adjacent described
Capacitance between contact plunger 150;
The capacitance C3 and the second testing capacitor value Cgt and the first testing capacitor of structure are tested by the third
The difference of value Cgm obtains third testing capacitor value Cof (as shown in Figure 4), and the third testing capacitor value Cof is the grid
Capacitance between structure 130 and adjacent 140 edge of the doped region.
In conjunction with reference Fig. 4, concrete analysis obtains the second testing capacitor value Cgt, the first testing capacitor value Cgm and the
The Computing Principle of three testing capacitor value Cof.
Fig. 4 is the structural schematic diagram of the first test one embodiment of structure, wherein is illustrated by taking n=2 as an example.It is brilliant
The parasitic capacitance of body pipe includes third testing capacitor value Cof, the second testing capacitor value Cgt and the first testing capacitor value Cgm.
Firstly, the difference of the capacitance C2 by the capacitance C1 and the second test structure of the first test structure
Value obtains the first testing capacitor value Cgm.
In the present embodiment, the difference of the first test structure and the second test structure is only that the first test structure
The second connection structure 320 (as shown in Figure 1) and the second test structure the 4th connection structure 340 (as shown in Figure 2), described the
Two connection structures 320 include the contact plunger 150 being connected with the doped region 140 and are connected with the contact plunger 150
The metal layer 160 connect, the 4th connection structure 340 include the contact plunger 150 being connected with the doped region 140, therefore,
It is described first test structure capacitance C1 be greater than it is described second test structure capacitance C2, and the difference of C1 and C2 from
Capacitance between the gate structure 130 and the adjacent metal layer 160 of the first test structure, i.e. the first testing capacitor value
Cgm, that is to say, that pass through the difference of the capacitance C2 of the capacitance C1 and the second test structure of the first test structure
Value, can obtain the first testing capacitor value Cgm.
Specifically, the capacitance C1 of the first test structure and the difference of the capacitance C2 of the second test structure are
2 × (n-1) of the first testing capacitor value Cgm times, n is the gate structure of the first test structure or the second test structure
130 quantity, that is, the formula for obtaining the first testing capacitor value Cgm is C1-C2=2 × (n-1) × Cgm.
In a specific embodiment, it is described first test structure gate structure 130 quantity be 5, described second
The quantity for testing the gate structure 130 of structure is 5, and therefore, the formula for obtaining the first testing capacitor value Cgm is C1-C2
=8 × Cgm.
Then, the difference of the capacitance C3 of structure is tested by the capacitance C2 and the third of the second test structure
Value obtains the second testing capacitor value Cgt.
In the present embodiment, the difference of the second test structure and third test structure is only that the second test structure
With the 4th connection structure 340, the 4th connection structure 340 includes the contact plunger being connected with the doped region 140
150, therefore, the capacitance C2 of the second test structure is greater than the capacitance C3 of third test structure, and C2 and C3
Capacitance of the difference between the gate structure 130 and the adjacent contact plunger 140 of the second test structure, i.e., the
Two testing capacitor value Cgt, that is to say, that the electricity of structure is tested by the capacitance C2 and the third of the second test structure
The difference of capacitance C3 can obtain the second testing capacitor value Cgt.
Specifically, the capacitance C2 of the second test structure and the difference of the capacitance C3 of third test structure are
2 × (n-1) of the second testing capacitor value Cgt times, n is the gate structure that the second test structure or third test structure
130 quantity, that is, the formula for obtaining the second testing capacitor value Cgt is C2-C3=2 × (n-1) × Cgt.
In a specific embodiment, the quantity of the gate structure 130 of the second test structure is 5, the third
The quantity for testing the gate structure 130 of structure is 5, therefore the formula for obtaining the second testing capacitor value Cgt is C2-C3=
8×Cgt。
It should be noted that first obtaining the first testing capacitor value Cgm in the present embodiment, then obtains described second and survey
Try capacitance Cgt.In another embodiment, the second testing capacitor value Cgt can be first obtained, then obtains first test
Capacitance Cgm.
Finally, capacitance C3 and the second testing capacitor value Cgt (as shown in Figure 4) by third test structure
And the difference of the first testing capacitor value Cgm (as shown in Figure 4), the third testing capacitor value Cof is obtained (such as Fig. 4 institute
Show).
In conjunction with reference Fig. 3, in the present embodiment, the capacitance C3 of the third test structure includes third testing capacitor value
Cof, the second testing capacitor value Cgt and the first testing capacitor value Cgm, therefore, the capacitance C3 of third test structure and 2 times
The difference of the second testing capacitor value Cgt and 2 times of the first testing capacitor value Cgm are the third testing capacitor value
2n times of Cof, that is, the formula for obtaining the third testing capacitor value Cof is C3-2 × Cgt-2 × Cgm=2 × n × Cof.
It should be noted that the doped region 140 further includes the overlapping region (figure positioned at 130 lower section of gate structure
Do not show), correspondingly, the test method further include: by the first testing capacitor value Cgm, the second testing capacitor value Cgt and
Third testing capacitor value Cof, obtaining the 4th testing capacitor value Cov, the 4th testing capacitor value Cov is the gate structure
130 with the overlap capacitance value of the adjacent doped region 140.
In the present embodiment, (does not indicate) the test structure (not shown) of capacitor by using gate structure 130 to drain region, obtain
Obtain the 4th testing capacitor value Cov.
It should be noted that the gate structure 130 to drain region (does not indicate) test structure and the present embodiment institute of capacitor
The difference for stating test structure is that the well region of the test structure is different from the doping type of doped region 140.The gate structure
Capacitance between 130 and the drain region includes the second testing capacitor value Cgt, the first testing capacitor value Cgm, third testing capacitor
Value Cof and the 4th testing capacitor value Cov.
Specifically, the step of obtaining the 4th testing capacitor value Cov includes: to provide gate structure 130 to drain region (not mark
Show) the test structure (not shown) of capacitor;By the test structure of the gate structure to drain region capacitor, the 5th test electricity is obtained
The capacitance of capacitance Cgd, the 5th testing capacitor value Cgd between the gate structure 130 and drain region;5th test
Capacitance Cgd subtracts the second testing capacitor value Cgt, the first testing capacitor value Cgm and third testing capacitor value Cof, can
To obtain the 4th testing capacitor value Cov, that is, the formula for obtaining the 4th testing capacitor value Cov is Cov=Cgd-Cgt-
Cgm-Cof。
The present invention tests structure by the first test structure, the second test structure and third, wherein the first test knot
The difference of structure and the second test structure be only that the first test structure the second connection structure and the second test structure the
The difference of four connection structures, the second test structure and third test structure is only that the second test structure has the 4th
Therefore connection structure tests the capacitance of structure by measuring the first test structure, the second test structure and third, and
By operation, capacitance, gate structure and the adjacent institute between the gate structure and the adjacent contact plunger can be obtained
The capacitance between metal layer and the capacitance between gate structure and the adjacent doped region are stated, so as to accurately
Obtain the parasitic capacitance of the transistor.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (15)
1. a kind of test structure characterized by comprising
Substrate, including first area, second area and third region;
Well region is located in the substrate;
Structure is tested positioned at the first of the first area, the first test structure includes dry and is located at the first area trap
The gate structure on area surface, positioned at the gate structure two sides it is intrabasement several as source region or the doped region in drain region, position
The second connection structure between first connection structure and first connection structure at the first area both ends, described
One connection structure includes the contact plunger being connected with the doped region and the metal layer that is connected with the contact plunger, institute
State the metal that the second connection structure includes the contact plunger being connected with the doped region and is connected with the contact plunger
Layer, wherein the well region is identical as the doping type of the doped region;
Structure is tested positioned at the second of the second area, the second test structure includes that several are located at the second area
The gate structure on well region surface, positioned at the gate structure two sides it is intrabasement several as source region or the doped region in drain region,
The 4th connection structure between the third connection structure and the third connection structure at the second area both ends, it is described
Third connection structure includes the contact plunger being connected with the doped region and the metal layer that is connected with the contact plunger,
4th connection structure includes the contact plunger being connected with the doped region, wherein the well region and the doped region
Doping type is identical;
Third positioned at the third region tests structure, and the third test structure includes that several are located at the third region
The gate structure on well region surface, positioned at the gate structure two sides it is intrabasement several as source region or the doped region in drain region,
And the 5th connection structure positioned at third region both ends, the 5th connection structure includes being connected with the doped region
Contact plunger and the metal layer that is connected with the contact plunger, wherein the doping class of the well region and the doped region
Type is identical.
2. test structure as described in claim 1, which is characterized in that first connection structure, third connection structure and the
Five connection structures are identical structure.
3. test structure as described in claim 1, which is characterized in that the first test structure, the second test structure and the
The formation process of gate structure of three test structures, material are identical with size, the first test structure, the second test structure and
The formation process of the contact plunger of third test structure, material are identical with size, the first test structure, the second test structure
It is identical with size with the formation process of the metal layer of third test structure, material.
4. test structure as described in claim 1, which is characterized in that the first test structure, the second test structure and the
The quantity of the gate structure of three test structures is equal.
5. test structure as claimed in claim 4, which is characterized in that the first test structure, the second test structure and the
The quantity of the gate structure of three test structures is n, and n is the natural number equal to or more than 2.
6. test structure as claimed in claim 5, which is characterized in that the quantity of the doped region is n+1;Described second connects
The quantity of binding structure is n-1;The quantity of 4th connection structure is n-1.
7. test structure as described in claim 1, which is characterized in that the test structure is fin field effect pipe structure, institute
Stating substrate includes substrate and the fin for protruding from the substrate, and the gate structure is located at the fin portion surface, the doping
Area is located in the fin of the gate structure two sides;
Alternatively, the test structure is planar transistor structure, the substrate is substrate, and the gate structure is located at the substrate
Surface, the doped region are located in the substrate of the gate structure two sides.
8. test structure as described in claim 1, which is characterized in that the test structure further includes stressor layers, the doping
Area is formed in the stressor layers.
9. test structure as described in claim 1, which is characterized in that the doped region further includes being located under the gate structure
The overlapping region of side.
10. a kind of test method characterized by comprising
Test structure as described in any one of claim 1 to 9 is provided;
The first test structure, the capacitance of the second test structure and third test structure are measured respectively;
By the difference of the capacitance of the capacitance and the second test structure of the first test structure, the first test is obtained
Capacitance, capacitance of the first testing capacitor value between the gate structure and the adjacent metal layer;
The difference that the capacitance of structure is tested by the capacitance and the third of the second test structure, obtains the second test
Capacitance, capacitance of the second testing capacitor value between the gate structure and the adjacent contact plunger;
The capacitance of structure and the difference of the first testing capacitor value and the second testing capacitor value are tested by the third,
Third testing capacitor value is obtained, the third testing capacitor value is between the gate structure and the adjacent doping area edge
Capacitance.
11. test method as claimed in claim 10, which is characterized in that in the step of obtaining the second testing capacitor value,
The difference of the capacitance of the capacitance and third test structure of the second test structure is the second testing capacitor value
2 × (n-1) times.
12. test method as claimed in claim 10, which is characterized in that in the step of obtaining the first testing capacitor value,
The difference of the capacitance of the capacitance of the first test structure and the second test structure, is the first testing capacitor value
2 × (n-1) times.
13. test method as claimed in claim 10, which is characterized in that in the step of obtaining the third testing capacitor value,
The capacitance of the third test structure and the difference of 2 times of the second testing capacitor values and 2 times of the first testing capacitor values
Value is 2n times of the third testing capacitor value.
14. test method as claimed in claim 10, which is characterized in that it is characterized in that, the test method further include: logical
It crosses the first testing capacitor value, the second testing capacitor value and third testing capacitor value, obtains the 4th testing capacitor value, described the
Four testing capacitor values are the overlap capacitance value of the gate structure and the adjacent doped region.
15. test method as claimed in claim 14, which is characterized in that it is characterized in that, obtaining the 4th testing capacitor
The step of value includes: to provide the test structure of gate structure to drain region capacitor;
By the test structure of the gate structure to drain region capacitor, the 5th testing capacitor value, the 5th testing capacitor are obtained
The capacitance being worth between the gate structure and drain region;
The 5th testing capacitor value subtracts the second testing capacitor value, the first testing capacitor value and third testing capacitor
Value obtains the 4th testing capacitor value.
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CN111933546B (en) * | 2020-10-14 | 2021-01-01 | 南京晶驱集成电路有限公司 | Capacitance measuring structure and measuring method |
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