CN107229153A - Embedded touch control type array base palte and preparation method and display device - Google Patents
Embedded touch control type array base palte and preparation method and display device Download PDFInfo
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- CN107229153A CN107229153A CN201710553129.9A CN201710553129A CN107229153A CN 107229153 A CN107229153 A CN 107229153A CN 201710553129 A CN201710553129 A CN 201710553129A CN 107229153 A CN107229153 A CN 107229153A
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- induction line
- insulating barrier
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
Abstract
A kind of embedded touch control type array base palte and preparation method and display device, the embedded touch control type array base palte includes common electrode layer and induction line layer, the common electrode layer includes multiple public electrode blocks that are spaced and being arranged in array, the induction line layer includes multiple induction lines of spaced arrangement, one end of every induction line is electrically connected by via hole public electrode block corresponding with one in the common electrode layer in the induction line layer, and the other end of every induction line is electrically connected with touch-control driving integrated chip.The preparation method of the embedded touch control type array base palte makes common electrode layer and induction line layer by using an intermediate tone mask version, single exposure can be reduced, shorten processing time, reduce production cost, and touch-control sensitivity and pixel aperture ratio will not be impacted.
Description
Technical field
The present invention relates to display technology field, and more particularly to a kind of embedded touch control type array base palte and preparation method and aobvious
Showing device.
Background technology
With developing rapidly for Display Technique, each side of touch-screen (touch panel) in people's life
Face.With the continuous progress of touch technology, requirement of the people to touch-control product also more and more higher, while sensitivity is paid close attention to also
Consider frivolous so that display panel manufacturer processing procedure cost is significantly lifted.
At present, touch-screen can be divided into according to composition structure：Cover surface-type touch-screen (On-cell touch panel)
And In-cell touch panel (In-cell touch panel).In-cell touch panel is to be embedded in the touch control electrode of touch-screen
Inside display screen, for example, touch control electrode is embedded on array base palte.Wherein there is a kind of mode, be to utilize the public affairs on array base palte
Common electrode layer (common electrode) serves as touch control electrode, and common electrode layer takes time-sharing multiplex, picture is shown with touching
Alternately, i.e. a frame picture is divided into display period and touch-control period to control sensing, and common electrode layer is used in the display period
Picture is carried out in driving liquid crystal molecule to show, is used to realize that touch-control sensing is detected in the touch-control period.
As shown in figure 1, a kind of existing array base palte is provided with common electrode layer and induction line layer, wherein public electrode
Layer include be arranged in array and mutually insulated multiple public electrode blocks 81, induction line layer include a plurality of sensing of mutually insulated
Circuit 82, a plurality of induction line 82 is corresponded respectively with the multiple public electrode block 81 to be electrically connected.Specifically, it is public
It is provided with insulating barrier, insulating barrier and is provided with the position corresponding with each public electrode block 81 between electrode layer and induction line layer
One end of every induction line 82 passes through the public electrode block 81 corresponding with one of via hole 83 in via hole 83, induction line layer
The other end of every induction line 82 is electrically connected with touch-control driving integrated chip 90 in electrical connection, induction line layer.
Intersect limit multiple as shown in Fig. 2 being additionally provided with and being insulated by scan line 86 and data wire 87 on the array base palte
Pixel electrode 88 and thin film transistor (TFT) 70 are provided with pixel cell, each pixel cell.Fig. 2 show each bar of induction line layer
Induction line 82 is overlapped with data wire about 87.
As shown in figure 3, the array base palte is when making, at least need to undergo eight road etch process.First of etching system
Journey is used for the grid 71 and scan line 86 for making thin film transistor (TFT) 70；Second etch process is used to make thin film transistor (TFT) 70
Semiconductor layer 72；3rd road etch process is used for the source electrode 73 and drain electrode 74 and data wire 87 for making thin film transistor (TFT) 70；
4th road etch process is used for the contact hole 89 for making switch on pixel electrode 88；5th road etch process is used to make pixel electrode
88；6th road etch process is used for the induction line 82 for making induction line layer；7th road etch process is used to make conducting public affairs
The via hole 83 of common electrode block 81；8th road etch process is used for the public electrode block 81 for making common electrode layer.This technique
Method needs multiexposure, multiple exposure and etching, its processing time length and adds cost of manufacture.
Fig. 4 is the structural representation of single pixel unit on existing another array base palte, and Fig. 4 show induction line
Each bar induction line 82 and the data wire 87 of layer are in same layer and close to being arranged side by side.
As shown in figure 5, the array base palte is when making, first of etch process is used for the grid for making thin film transistor (TFT) 70
Pole 71 and scan line 86；Second etch process is used for the semiconductor layer 72 for making thin film transistor (TFT) 70；3rd road etching system
Journey is used for the induction line 82 for making the source electrode 73 of thin film transistor (TFT) 70, drain electrode 74 and data wire 87 and induction line layer；The
Four road etch process are used to make pixel electrode 88, and pixel electrode 88 is directly contacted with the drain electrode 74 of thin film transistor (TFT) 70；5th
Road etch process is used for the via hole 83 for making conducting public electrode block 81；6th road etch process is used to make common electrode layer
Public electrode block 81.This process needs the etch process undergone to reduce, and reduces processing time and cost of manufacture, but
Be due to induction line layer each bar induction line 82 with data wire 87 close to being arranged side by side, cause the load of induction line 82
Weight, touch-control sensitivity is poor, and pixel aperture ratio is also decreased obviously.
The content of the invention
In view of this, filled it is an object of the invention to provide a kind of embedded touch control type array base palte and preparation method and display
Put, processing time and cost of manufacture can be reduced, and touch-control sensitivity and pixel aperture ratio will not be impacted.
The embodiment of the present invention provides a kind of embedded touch control type array base palte, including：
Substrate；
Form multi-strip scanning line over the substrate and a plurality of data lines and multiple thin film transistor (TFT)s, it is described a plurality of to sweep
Retouch line and insulated with a plurality of data lines and intersect the multiple pixel cells limited in array distribution, the multiple thin film transistor (TFT) point
Wei Yu not be in the multiple pixel cell；
First insulating barrier, first insulating barrier is covered on the multiple thin film transistor (TFT)；
Common electrode layer, the common electrode layer formation is on first insulating barrier, and the common electrode layer includes phase
The multiple public electrode blocks for being mutually spaced and being arranged in array；
Second insulating barrier, the second insulating barrier formation is in the common electrode layer, and second insulating barrier is adjacent
The public electrode block separated and be provided with via hole corresponding to each public electrode block；
Induction line layer, the induction line layer is formed on second insulating barrier, and the induction line layer includes phase
The multiple induction lines being mutually intervally arranged, every induction line two neighboring public electrode block in their extension direction
Between be disconnect；
3rd insulating barrier, the 3rd insulating barrier formation is on induction line layer, and the 3rd insulating barrier covering is each
Every induction line of correspondence is provided with bridge joint at the two ends of open position in induction line described in bar, the 3rd insulating barrier
The leakage of each thin film transistor (TFT) of correspondence in hole, the 3rd insulating barrier, second insulating barrier and first insulating barrier
Pole is provided with contact hole；
Pixel electrode layer, the pixel electrode layer formation is on the 3rd insulating barrier, and the pixel electrode layer includes many
Individual conductive bar and multiple pixel electrodes, wherein each conductive bar insert in the corresponding bridge joint hole and will it is corresponding described in
Induction line conductive communication between the two neighboring public electrode block, each pixel electrode is located at corresponding pixel list
Member is interior and inserts the Drain Electrodes Conductive connection in the corresponding contact hole with the corresponding thin film transistor (TFT).
Further, one end of every induction line passes through the via hole and the public affairs in the induction line layer
A corresponding public electrode block electrical connection in common electrode layer, the other end of every induction line drives with touch-control to be collected
Into chip electrical connection.
Further, each public electrode block corresponds to multiple pixel cells.
Further, induction line described in each bar is overlapping with above and below a plurality of data lines in the induction line layer sets
Put.
Further, the common electrode layer and the pixel electrode layer are made of electrically conducting transparent material, the sensing
Line layer is made of metal, and first insulating barrier, second insulating barrier and the 3rd insulating barrier use inorganic insulation
Material is made.
The embodiment of the present invention also provides a kind of display device, including above-mentioned embedded touch control type array base palte.
The embodiment of the present invention also provides a kind of preparation method of embedded touch control type array base palte, including step：
Made on substrate and form multi-strip scanning line and a plurality of data lines and multiple thin film transistor (TFT)s, the multi-strip scanning
Line insulate with a plurality of data lines intersects the multiple pixel cells limited in array distribution, the multiple thin film transistor (TFT) difference
In the multiple pixel cell；
The depositing first insulator layer on the multiple thin film transistor (TFT), public electrode is deposited on first insulating barrier
Layer, deposits the second insulating barrier in the common electrode layer；
Second insulating barrier is etched, corresponding to the open position between two neighboring public electrode block and
Second insulating barrier is removed corresponding to the position of via hole, and the institute below exposing in the removals position of second insulating barrier
State common electrode layer；
The deposition induction line layer on second insulating barrier and the common electrode layer exposed；
Photoresist layer is coated with induction line layer；
The photoresist layer is exposed using an intermediate tone mask version, then the photoresist layer developed, institute
State photoresist layer to form complete removal region after development, region and part removal region is fully retained, wherein the complete removal
The open position that region corresponds between the two neighboring public electrode block, the region that is fully retained is corresponding to every sensing
The extended position of circuit, the part removes other regions that region corresponds to the photoresist layer；
By the use of the photoresist layer as shade, wet corrosion is carried out to the induction line layer below the complete removal region
Carve, remove the induction line layer corresponding with the complete removal region, and below exposing in the complete removal region
The common electrode layer；
The photoresist layer is continued with as shade, the common electrode layer exposed to the complete removal region is carried out
Wet etching, remove the common electrode layer corresponding with the complete removal region, and formation is spaced and is arranged in array
Multiple public electrode blocks；
The photoresist layer is ashed, the photoresist layer that the part removes region is completely removed and exposes lower section
Induction line layer, but the region that is fully retained still remains with the photoresist layer；
The induction line exposed in region layer is removed to the part and carries out wet etching, is removed and the part removal area
The corresponding induction line layer in domain, forms spaced and parallel arrangement multiple induction lines；
The remaining photoresist layer is peeled off, now every induction line is two neighboring in their extension direction
It is to disconnect between the public electrode block；
The 3rd insulating barrier is deposited on induction line layer, the 3rd insulating barrier covers each article of induction line, to institute
The 3rd insulating barrier is stated to be etched in the two ends formation bridge joint hole of the open position of every induction line of correspondence and in correspondence
The drain locations formation contact hole of each thin film transistor (TFT)；
The pixel deposition electrode layer on the 3rd insulating barrier, is etched to form multiple pixels to the pixel electrode layer
Electrode and multiple conductive bars, wherein each conductive bar is inserted in the corresponding bridge joint hole and is connected across two neighboring described
Open position between public electrode block, makes every induction line in open position by the conductive bar conductive communication,
Each pixel electrode be located in corresponding pixel cell and insert in corresponding contact hole with the corresponding film crystal
The Drain Electrodes Conductive connection of pipe.
Further, deposit and formed after the common electrode layer on first insulating barrier, in addition to the public affairs
Common electrode layer carries out high-temperature baking.
Further, when carrying out wet etching to the common electrode layer, specifically using chloroazotic acid to the complete removal
The common electrode layer that region is exposed is etched.
Further, the common electrode layer and the pixel electrode layer are made of electrically conducting transparent material, the sensing
Line layer is made of metal, and first insulating barrier, second insulating barrier and the 3rd insulating barrier use inorganic insulation
Material is made.
Embedded touch control type array base palte provided in an embodiment of the present invention and preparation method, by using an intermediate tone mask
Version come make common electrode layer and induction line layer, it is possible to reduce single exposure, shorten processing time, reduce production cost, and
Touch-control sensitivity and pixel aperture ratio will not be impacted.
Brief description of the drawings
Fig. 1 is a kind of existing floor map of array base palte.
Fig. 2 is the structural representation of single pixel unit on Fig. 1 array base palte.
Fig. 3 is schematic cross-sections of the Fig. 2 along line A-A.
Fig. 4 is the structural representation of single pixel unit on existing another array base palte.
Fig. 5 is schematic cross-sections of the Fig. 4 along line B-B.
Fig. 6 is the planar structure schematic diagram of array base palte in one embodiment of the invention.
Fig. 7 is the enlarged plan structural representation at array base palte dotted line frame C in Fig. 6.
Fig. 8 is schematic cross-sections of the Fig. 7 along line D-D.
Fig. 9 a to Fig. 9 j are manufacturing process schematic cross-section of the array base palte along E-E lines in Fig. 6.
Figure 10 a to Figure 10 l are the manufacturing process floor map at array base palte dotted line frame F in Fig. 6.
Embodiment
Further to illustrate the present invention to reach technical approach and effect that predetermined goal of the invention is taken, below in conjunction with
Drawings and Examples, to embodiment, structure, feature and its effect of the present invention, are described in detail as after.
Fig. 6 is the planar structure schematic diagram of array base palte in one embodiment of the invention.Fig. 7 is array base palte void in Fig. 6
Enlarged plan structural representation at wire frame C.Fig. 8 is schematic cross-sections of the Fig. 7 along line D-D.As shown in Figure 6 to 8, this hair
The embedded touch control type array base palte that bright embodiment is provided include being formed with substrate 11, substrate 11 by multi-strip scanning line 12 with it is a plurality of
The mutually insulated of data wire 13 intersects in the multiple pixel cells for limiting and being formed in array distribution, each pixel cell provided with pixel electricity
Pole 141 and thin film transistor (TFT) 15.Thin film transistor (TFT) 15 includes grid 151, semiconductor layer 152, source electrode 153 and drain electrode 154.Scanning
The grid 151 of line 12 and thin film transistor (TFT) 15 is formed on the substrate 11, and gate insulator 16 forms and be covered in the He of scan line 12
On grid 151, semiconductor layer 152 is formed on gate insulator 16, the He of source electrode 153 of data wire 13 and thin film transistor (TFT) 15
Drain electrode 154 is formed on gate insulator 16, and two end in contact of source electrode 153 and drain electrode 154 respectively with semiconductor layer 152 connect
Connect.
Wherein, the grid 151 of thin film transistor (TFT) 15 electrically connects corresponding scan line 12, the grid 151 of thin film transistor (TFT) 15
A part for scan line 12 can be independently arranged or can also be, the source electrode 153 of thin film transistor (TFT) 15 electrically connects corresponding number
According to line 13, the drain electrode 154 of thin film transistor (TFT) 15 electrically connects corresponding pixel electrode 141.
There is deposition on thin film transistor (TFT) 15 is formed with common electrode layer 18 on first insulating barrier 17, the first insulating barrier 17, public
There being deposition in common electrode layer 18 is formed with induction line layer 21 on second insulating barrier 19, the second insulating barrier 19, induction line layer 21
Upper deposition has is formed with pixel electrode layer 14 on the 3rd insulating barrier 22, the 3rd insulating barrier 22.
Common electrode layer 18 include be arranged in array and mutually insulated multiple public electrode blocks 181, each public electrode
Block 181 corresponds to multiple pixel cells.Induction line layer 21 includes a plurality of induction line 211 of mutually insulated, a plurality of sense
Answer circuit 211 to be overlapped with a plurality of data lines about 13, touch-control sensitivity and pixel aperture ratio will not so be caused
Influence.The a plurality of induction line 211 is corresponded and electrically connected respectively with the multiple public electrode block 181, specifically, public
Be provided with the second insulating barrier 19 between electrode layer 18 and induction line layer 21, in the second insulating barrier 19 with each public electrode block
One end that 181 corresponding positions are provided with every induction line 211 in via hole 191, induction line layer 21 passes through via hole 191
Public electrode block 181 corresponding with one in common electrode layer 18 is electrically connected, and the other end and the touch-control of every induction line 211 drive
Dynamic integrated chip 50 is electrically connected.
Due to being provided with the second insulating barrier 19, therefore every induction line between common electrode layer 18 and induction line layer 21
211 can keep insulating by the second insulating barrier 19 with other public electrode blocks 181.That is, every induction line 211
It is middle outside the other end is electrically connected with touch-control driving integrated chip 50 except one end is electrically connected with corresponding public electrode block 181
Mutually insulated between part and other public electrode blocks 181.
In the present embodiment, the induction line 211 of induction line layer 21 and the induction line 211 of common electrode layer 18 are in array
Embedded touch sensor (In-cell touch sensors) is formed in substrate, the embedded touch sensor is from appearance
Formula framework, each public electrode block 181 of common electrode layer 18 is used as each bar line of induction held certainly in electrode, induction line layer 21
Detectable signal is led to touch-control driving integrated chip 50 by road 211 as cabling, drives 50 pairs of detections of integrated chip to believe by touch-control
Number handled.
In the present embodiment, touch-control sensing function, common electrode layer 18 are served as using the common electrode layer 18 on array base palte
Time-sharing multiplex is taken, picture is shown that with touch-control sensing alternately, i.e. a frame picture is divided into display period and touch-control time
Section, common electrode layer 18 is used to apply common electric voltage (Vcom) and forms electric field between pixel electrode 141 in the display period
Shown with driving liquid crystal molecule to carry out picture, be used to realize that touch-control sensing is detected in the touch-control period, with to touching on display screen
Signal is touched to be sensed.
Common electrode layer 18 and pixel electrode layer 14 can be made of electrically conducting transparent materials such as tin indium oxides (ITO), be felt
Line layer 21 is answered to be made up of the relatively low metal of the resistivity such as Mo, Al, Au, Ag, Cu.First insulating barrier 17, the second insulating barrier
19 and the 3rd insulating barrier 22 can be made using inorganic insulating material such as silica, silicon nitride, silicon oxynitride.
The embodiment of the present invention also provides a kind of preparation method of above-mentioned array base palte, comprises the following steps：
Make on the substrate 11 and form multi-strip scanning line 12 and a plurality of data lines 13 and multiple thin film transistor (TFT)s 15, it is described
Multi-strip scanning line 12 insulate with a plurality of data lines 13 intersects the multiple pixel cells limited in array distribution, the multiple thin
Film transistor 15 is located in the multiple pixel cell respectively；
Wherein, make on the substrate 11 and form multi-strip scanning line 12 and a plurality of data lines 13 and multiple thin film transistor (TFT)s
15, it can use but be not limited to following processing procedure and made, for example：
The first metal layer is first deposited on the substrate 11, and the first metal layer is patterned using one of etch process,
Make the grid 151 for obtaining scan line 12 and thin film transistor (TFT) 15；
Then gate insulator 16, and one layer of the deposition on gate insulator 16 are deposited in scan line 12 and grid 151
Amorphous silicon layer, and amorphous silicon layer is patterned using one of etch process, make and obtain correspondence positioned at the top of grid 151
Semiconductor layer 152；
Then the depositing second metal layer on semiconductor layer 152 and gate insulator 16, and one is utilized to second metal layer
Road etch process is patterned, and makes the source electrode 153 for obtaining data wire 13 and being separated from each other and drain electrode 154, and the He of source electrode 153
154 two ends respectively with semiconductor layer 152 of drain electrode are in contact；
Next, Fig. 9 a to Fig. 9 j and Figure 10 a to Figure 10 l please be join, a 30 (half-tone of intermediate tone mask version are utilized
Mask) come make common electrode layer 18 and induction line layer 21.
As shown in Fig. 9 a and Figure 10 a, the depositing first insulator layer 17 on the multiple thin film transistor (TFT) 15, in the first insulation
Common electrode layer 18 is deposited on layer 17, the second insulating barrier 19 is deposited in common electrode layer 18；Wherein it is preferred to, it is exhausted first
Deposition is formed after common electrode layer 18 in edge layer 17, in addition to carries out high-temperature baking to common electrode layer 18, improves it stable
Property and electric conductivity.
As shown in Fig. 9 b and Figure 10 b, the second insulating barrier 19 is etched using one of etch process, corresponding to adjacent
Open position between two public electrode blocks 181 and the position corresponding to via hole 191 remove the second insulating barrier 19, the
Expose the common electrode layer 18 of lower section in the removal position of two insulating barriers 19.
As shown in Fig. 9 c and Figure 10 c, the deposition induction line layer on the second insulating barrier 19 and the common electrode layer 18 exposed
21。
As shown in Fig. 9 d and Figure 10 d, photoresist layer 40 is coated with induction line layer 21.In the present embodiment, photoresist layer 40 with
Illustrated exemplified by positivity photoresistance.
As shown in Fig. 9 e and Figure 10 e, entered using intermediate tone mask version (half-tone mask) 30 pairs of photoresist layers 40
Row exposure, intermediate tone mask version 30 includes light tight area 30a, semi-opaque region 30b and transparent area 30c, and intermediate tone mask version 30 is adopted
Processing is exposed to photoresist layer 40 with light transmittance different multiple regions, then photoresist layer 40 developed, photoresist layer 40
Formed after development and remove region 41 completely, region 42 be fully retained and part removal region 43, wherein removing region 41 completely
Corresponding to the open position between two neighboring public electrode block 181, region 42 is fully retained corresponding to every induction line 211
Extended position, part remove region 43 correspond to photoresist layer 40 other regions.
As shown in Fig. 9 f and Figure 10 f, by the use of photoresist layer 40 as shade, the induction line to removing the lower section of region 41 completely
Layer 21 carries out wet etching, removes with removing the corresponding induction line in region 41 layer 21 completely, and expose removing region 41 completely
The common electrode layer 18 of lower section.
As shown in Fig. 9 g and Figure 10 g, photoresist layer 40 is continued with as shade, what removal region 41 completely was exposed is public
Electrode layer 18 carries out wet etching, removes common electrode layer 18 corresponding with removing region 41 completely, so just completes to common electrical
The patterning of pole layer 18, forms multiple public electrode blocks 181 that are spaced and being arranged in array.Due in above-mentioned steps,
High-temperature baking was carried out to common electrode layer 18, therefore in this step, it is possible to use chloroazotic acid exposes to removing region 41 completely
Common electrode layer 18 be etched, improve etching efficiency.
As shown in Fig. 9 h and Figure 10 h, photoresist layer 40 is ashed (Ashing), part removes the photoresist layer 40 in region 43
The induction line layer 21 of lower section is completely removed and exposed, but region 42 is fully retained and still remains with photoresist layer 40.
As shown in Fig. 9 i and Figure 10 i, to part remove region 43 expose induction line layer 21 carry out wet etching, remove with
Part removes the corresponding induction line in region 43 layer 21, so just completes the patterning to induction line layer 21, forms mutual
Every and parallel arrangement multiple induction lines 211.
As shown in Fig. 9 j and Figure 10 j, remaining photoresist layer 40 is peeled off, so as to utilize an intermediate tone mask version 30
Complete to make the patterning of common electrode layer 18 and induction line layer 21.But, now every induction line 211 extends at it
It is to disconnect between two neighboring public electrode block 181 on direction (the present embodiment is vertical direction).It is to be appreciated that at other
In embodiment, when touch-control drives integrated chip 50 to be arranged on the left side or right side of array base palte, rather than the present embodiment downside when,
The bearing of trend of every induction line 211 can be horizontally oriented, but the preparation method that the present embodiment is provided is general.
As shown in Fig. 8 and Figure 10 k, the 3rd insulating barrier 22 is deposited on induction line layer 21, the 3rd insulating barrier 22 is covered respectively
Bar induction line 211, and the 3rd insulating barrier 22 is etched in every induction line 211 of correspondence using one of etch process
The two ends of open position form bridge joint hole 221 and form contact hole in the position of drain electrode 154 of each thin film transistor (TFT) 15 of correspondence
222, wherein contact hole 222 also extends through the second insulating barrier 19 and the first insulating barrier 17；
As shown in Fig. 8 and Figure 10 l, the pixel deposition electrode layer 14 on the 3rd insulating barrier 22, and utilize one of etch process
Pixel electrode layer 14 is etched to form multiple pixel electrodes 141 and multiple conductive bars 142, wherein each conductive bar 142 is filled out
The open position for entering in corresponding bridge joint hole 221 and being connected across between two neighboring public electrode block 181, makes every induction line
211 in open position by the conductive communication of conductive bar 142, each pixel electrode 141 be located in corresponding pixel cell and
The drain electrode 154 in corresponding contact hole 222 with corresponding thin film transistor (TFT) 15 is inserted to be conductively connected.So as to every induction line
211 one end is electrically connected by the public electrode block 181 corresponding with one in common electrode layer 18 of via hole 191, every sensing
The other end of circuit 211 is electrically connected with touch-control driving integrated chip 50, and the center section of every induction line 211 passes through conductive bar
142 connect and pass through realization insulation between the second insulating barrier 19 and other public electrode blocks 181.
To sum up, embedded touch control type array base palte provided in an embodiment of the present invention and preparation method, by using one and half colors
Adjust mask plate to make common electrode layer and induction line layer, it is possible to reduce single exposure, shorten processing time, reduction is produced into
This, and touch-control sensitivity and pixel aperture ratio will not be impacted.
The embodiment of the present invention also provides a kind of display device, including above-mentioned embedded touch control type array base palte.Wherein, it is described
Display device can be liquid crystal display device, and also include the parts such as color membrane substrates and liquid crystal layer.
It the above is only presently preferred embodiments of the present invention, any formal limitation not made to the present invention, although this
Invention is disclosed above with preferred embodiment, but is not limited to the present invention, any those skilled in the art,
Do not depart from the range of technical solution of the present invention, when the technology contents using the disclosure above make a little change or are modified to equivalent
The equivalent embodiment of change, as long as being that, without departing from technical solution of the present invention content, the technical spirit according to the present invention is real to more than
Any simple modification, equivalent variations and modification that example made are applied, in the range of still falling within technical solution of the present invention.
Claims (10)
1. a kind of embedded touch control type array base palte, it is characterised in that including：
Substrate (11)；
The multi-strip scanning line (12) and a plurality of data lines (13) and multiple thin film transistor (TFT)s formed on the substrate (11)
(15), the multi-strip scanning line (12) is insulated with a plurality of data lines (13) intersects the multiple pixel lists limited in array distribution
Member, the multiple thin film transistor (TFT) (15) is located in the multiple pixel cell respectively；
First insulating barrier (17), first insulating barrier (17) is covered on the multiple thin film transistor (TFT) (15)；
Common electrode layer (18), the common electrode layer (18) is formed on first insulating barrier (17), the public electrode
Layer (18) includes multiple public electrode blocks (181) that are spaced and being arranged in array；
Second insulating barrier (19), second insulating barrier (19) is formed in the common electrode layer (18), second insulation
Layer (19) is provided with the separated of the adjacent public electrode block (181) and corresponding to each public electrode block (181)
Via hole (191)；
Induction line layer (21), the induction line layer (21) is formed on second insulating barrier (19), the induction line
Layer (21) includes multiple induction lines (211) of spaced arrangement, and every induction line (211) is in their extension direction
It is to disconnect between the two neighboring public electrode block (181)；
3rd insulating barrier (22), the 3rd insulating barrier (22) is formed on induction line layer (21), the 3rd insulation
Layer (22) covers every induction line (211) of correspondence in induction line (211) described in each bar, the 3rd insulating barrier (22)
At the two ends of open position provided with bridge joint hole (221), the 3rd insulating barrier (22), second insulating barrier (19) and described the
The drain electrode (154) of each thin film transistor (TFT) (15) of correspondence is provided with contact hole (222) in one insulating barrier (17)；
Pixel electrode layer (14), the pixel electrode layer (14) is formed on the 3rd insulating barrier (22), the pixel electrode
Layer (14) includes multiple conductive bars (142) and multiple pixel electrodes (141), wherein each conductive bar (142) inserts correspondence
The bridge joint hole (221) in and by the corresponding induction line (211) the two neighboring public electrode block (181) it
Between conductive communication, each pixel electrode (141) is located in corresponding pixel cell and inserts the corresponding contact hole
(222) drain electrode (154) in the corresponding thin film transistor (TFT) (15) is conductively connected.
2. embedded touch control type array base palte as claimed in claim 1, it is characterised in that every in the induction line layer (21)
One end of the induction line (211) passes through the via hole (191) and a corresponding institute in the common electrode layer (18)
State public electrode block (181) electrical connection, the other end and touch-control driving integrated chip (50) electricity of every induction line (211)
Connection.
3. embedded touch control type array base palte as claimed in claim 1, it is characterised in that each public electrode block (181)
Corresponding to multiple pixel cells.
4. embedded touch control type array base palte as claimed in claim 1, it is characterised in that each bar in the induction line layer (21)
The induction line (211) overlaps up and down with a plurality of data lines (13).
5. embedded touch control type array base palte as claimed in claim 1, it is characterised in that the common electrode layer (18) and described
Pixel electrode layer (14) is made of electrically conducting transparent material, and the induction line layer (21) is made of metal, and described first is exhausted
Edge layer (17), second insulating barrier (19) and the 3rd insulating barrier (22) are made of inorganic insulating material.
6. a kind of display device, it is characterised in that including the embedded touch control type array base as described in any one of claim 1 to 5
Plate.
7. a kind of preparation method of embedded touch control type array base palte, it is characterised in that including step：
Made on substrate (11) and form multi-strip scanning line (12) and a plurality of data lines (13) and multiple thin film transistor (TFT)s (15),
The multi-strip scanning line (12) is insulated with a plurality of data lines (13) intersects the multiple pixel cells limited in array distribution, institute
Multiple thin film transistor (TFT)s (15) are stated respectively to be located in the multiple pixel cell；
The depositing first insulator layer (17) on the multiple thin film transistor (TFT) (15), is deposited public on first insulating barrier (17)
Common electrode layer (18), deposits the second insulating barrier (19) in the common electrode layer (18)；
Second insulating barrier (19) is etched, corresponding to the disconnection position between two neighboring public electrode block (181)
Put and remove second insulating barrier (19) corresponding to the position of via hole (191), and in second insulating barrier (19)
Remove the common electrode layer (18) that lower section is exposed in position；
Induction line layer (21) is deposited on second insulating barrier (19) and the common electrode layer (18) exposed；
The coating photoresist layer (40) on induction line layer (21)；
The photoresist layer (40) is exposed using an intermediate tone mask version (30), then the photoresist layer (40) carried out
Development, the photoresist layer (40) forms remove region (41) completely after development, region (42) is fully retained and part removal area
Domain (43), wherein the disconnection position that the complete removal region (41) corresponds between the two neighboring public electrode block (181)
Put, the extended position that region (42) is fully retained corresponding to every induction line (211), the part removes region (43)
Corresponding to other regions of the photoresist layer (40)；
By the use of the photoresist layer (40) as shade, to the induction line layer (21) below the complete removal region (41)
Wet etching is carried out, the induction line layer (21) corresponding with the complete removal region (41) is removed, and go completely described
Except region (41) expose the common electrode layer (18) of lower section；
The photoresist layer (40) is continued with as shade, the common electrode layer exposed to the complete removal region (41)
(18) wet etching is carried out, the common electrode layer (18) corresponding with the complete removal region (41) is removed, is formed each other
Every and multiple public electrode blocks (181) for being arranged in array；
The photoresist layer (40) is ashed, the photoresist layer (40) that the part removes region (43) is completely removed simultaneously
Expose the induction line layer (21) of lower section, but the region (42) that is fully retained still remains with the photoresist layer
(40)；
Induction line region (43) exposed layer (21) is removed to the part and carries out wet etching, removal is gone with the part
Except region (43) the corresponding induction line layer (21), spaced and parallel arrangement multiple induction lines are formed
(211)；
The remaining photoresist layer (40) is peeled off, now every induction line (211) phase in their extension direction
It is to disconnect between adjacent two public electrode blocks (181)；
The 3rd insulating barrier (22) is deposited on induction line layer (21), the 3rd insulating barrier (22) covers each article of line of induction
Road (211), two in the open position for corresponding to every induction line (211) are etched to the 3rd insulating barrier (22)
End forms bridge joint hole (221) and forms contact hole in drain electrode (154) position of each thin film transistor (TFT) (15) of correspondence
(222)；
The pixel deposition electrode layer (14) on the 3rd insulating barrier (22), is etched to be formed to the pixel electrode layer (14)
Multiple pixel electrodes (141) and multiple conductive bars (142), wherein each conductive bar (142) inserts the corresponding bridge joint
In hole (221) and the open position that is connected across between the two neighboring public electrode block (181), make every induction line
(211) in open position by the conductive bar (142) conductive communication, each pixel electrode (141) is located at corresponding picture
In plain unit and the drain electrode (154) inserted in corresponding contact hole (222) with the corresponding thin film transistor (TFT) (15) is led
Electrical connection.
8. the preparation method of embedded touch control type array base palte as claimed in claim 7, it is characterised in that in the described first insulation
Deposit and formed after the common electrode layer (18) on layer (17), in addition to high temperature baking is carried out to the common electrode layer (18)
It is roasting.
9. the preparation method of embedded touch control type array base palte as claimed in claim 8, it is characterised in that to the common electrical
When pole layer (18) carries out wet etching, the common electrode layer specifically exposed using chloroazotic acid to the complete removal region (41)
(18) it is etched.
10. the preparation method of embedded touch control type array base palte as claimed in claim 7, it is characterised in that the public electrode
Layer (18) and the pixel electrode layer (14) are made of electrically conducting transparent material, and the induction line layer (21) uses metal system
Into first insulating barrier (17), second insulating barrier (19) and the 3rd insulating barrier (22) use inorganic insulating material
It is made.
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| CN201710553129.9A CN107229153B (en) | 2017-07-07 | 2017-07-07 | Embedded touch control type array substrate and production method and display device |
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