CN107222212B

CN107222212B - Method for improving signal-to-noise ratio of successive approximation type analog-to-digital converter circuit and implementation circuit

Info

Publication number: CN107222212B
Application number: CN201710268578.9A
Authority: CN
Inventors: 穆庚; 陈思正; 闫娜; 闵昊
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2017-04-23
Filing date: 2017-04-23
Publication date: 2021-01-26
Anticipated expiration: 2037-04-23
Also published as: CN107222212A

Abstract

The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a method for improving the signal-to-noise ratio of a successive approximation type analog-to-digital converter circuit and an implementation circuit. The invention mainly compares M (M) repeatedly by the last LSB bit of the successive approximation type analog-to-digital converter>1) Next, M digital codes of the last bit comparison are obtained

Then combining the M digital codes with the corresponding weight coefficients of the M codes

And intercept term

Quantization code for obtaining final LSB bit after weight summation

Final LSB bit quantized code value

The quantization precision of the digital-to-analog converter is higher than that of a traditional successive approximation type analog-to-digital converter, and the signal-to-noise ratio of the circuit is improved with small circuit cost.

Description

Method for improving signal-to-noise ratio of successive approximation type analog-to-digital converter circuit and implementation circuit

Technical Field

The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a method for improving the signal-to-noise ratio of a successive approximation type analog-to-digital converter circuit and a realization circuit.

Background

Analog-to-digital converters have been very important circuit modules in integrated circuits, which implement the function of converting analog signals into digital signals, and are related to the whole analog world and the logic world. With the development of circuit technology, analog-to-digital converters with low noise become one of the popular research directions for designing analog-to-digital converters.

As shown in fig. 1, the circuit application needs to quantize very tiny signals, which requires that the noise in the analog-to-digital converter circuit is very small, so that the circuit can distinguish very small signals, and if the size of the signals in the circuit is comparable to the size of the noise, the analog-to-digital converter circuit is difficult to quantize the small signals. There are many circuit technologies or structures that can make the circuit noise low, for example, the sigma-delta analog-to-digital converter is a low-noise standard analog-to-digital converter circuit structure, which uses noise shaping and oversampling technology to realize a high-resolution analog-to-digital converter. Because of the low power consumption characteristic of successive approximation type analog-to-digital converters, more and more circuit designers want to realize low-noise circuit design in successive approximation type analog-to-digital converters, however, the low noise performance in successive approximation type analog-to-digital converters is usually at the cost of very large power consumption, the design overwhelms the low power consumption characteristic of successive approximation type analog-to-digital converters, and new requirements are put forward in the field of integrated circuits on how to realize high signal-to-noise ratio in successive approximation type analog-to-digital converters and with little circuit cost.

Disclosure of Invention

The invention aims to provide a simple, convenient and low-cost method for improving the signal-to-noise ratio of a successive approximation type analog-to-digital converter circuit and a realization circuit.

The method for improving the signal-to-noise ratio of the successive approximation type analog-to-digital converter circuit provided by the invention is to repeatedly compare M (M) to the last LSB bit of the successive approximation type analog-to-digital converter>1) Then, M digital codes are obtained, and the M digital codes are respectively D_LSB0,D_LSB1,…,D_LSBM-1Then according to M digital codes and their weighted values and intercept term D_interceptWeighted summation is carried out to finally obtain D_LSB＝a₀D_LSB0+a₁D_LSB1+…+a_M-1D_LSBM-1+D_interceptTo represent the quantization of the last LSB bit, wherein a_iIs a weighting factor, i is 0, 1, 2 …, M-1.

FIGS. 2-5 illustrate the algorithm principles of the present inventionFIG. a is first obtained by a program written in code₀,a₁,…,a_M-1,D_interceptAnd designing an output digital code calibration circuit according to the obtained numerical value.

FIG. 2 shows the result of obtaining a₀,a₁,…,a_M-1,D_interceptAnd (4) numerical algorithm flow.

First, let the input signal y_realsignalN-bit ADC processing with M-times comparison by LSB bits, where y_idealsignalRepresenting the quantized signal, y, input to the ADC_noiseSimulating noise in real circuits, y_realsignalBy y_idealsignalAnd y_noiseComposing a signal representing the actual quantization of the ADC; the N-bit ADC with LSB bits repeatedly compared M times is implemented by row-level programming of codes, and the structure of the circuit is shown in fig. 3, where the code is executed to obtain:

D_MSB,D_MSB-1,…,D_LSB+1,D_LSB0,D_LSB1,…,D_LSBM-1a digital code;

the next part of the algorithm processes the results of the previous section of code processing:

D_MSB,D_MSB-1,…,D_LSB+1,D_LSB0,D_LSB1,…,D_LSBM-1and externally inputted y_idealsignal(signal to be actually quantized) this part of the code will be D_MSB,D_MSB-1,…,D_LSB+1,D_LSB0,D_LSB1,…,D_LSBM-1And y_idealsignalAs input, its internal use D_y*LSB＝(2^N-1D_MSB+2^N-2D_MSB-1+…+2D_LSB+1+a₀D_LSB0+a₁D_LSB1+…+a_M-1D_LSBM-1+D_intercept) LSB (sum of weights of ADC quantized digital code multiplied by LSB) versus y_idealsignalBy performing approximation (performing the ordering least squares algorithm), this part will output the coefficient a of the linear fit through the input of a large amount of data₀,a₁,…,a_M-1,D_intercept. So far, the coefficients of the linear fit have been obtained by fig. 2;

then D is calculated according to the linear fitting coefficient_y＝2^N-1D_MSB+2^N-2D_MSB-1+…+2D_LSB+1+a₀D_LSB0+a₁D_LSB1+…+a_M-1D_LSBM-1+D_interceptThe weight summation of (2) is realized by a circuit, as shown in figure 4, and D is finally output_MSB,D_MSB-1,…,D_LSB+1,D_LSBIs the quantized digital code of ADC, where D_LSBConsists of an integer bit and a digital decimal bit.

Fig. 5 illustrates the change of the reference in one conversion of the ADC of fig. 4 (the reference change is indicated by a bold line in fig. 5), in which the circuit operation of the MSB to (LSB +1) bits is identical to that of the conventional one, but the last bit is slightly different. Specifically described below, when the circuit compares the result of the (LSB +1) bit, the circuit switches the LSB0 bit according to the comparison result, if the comparison result shows that the reference comparison reference is smaller than the input signal, the new reference is to add a physical LSB amount to the original reference, and if the comparison result shows that the reference comparison reference is larger than the input signal, the new reference is to subtract a physical LSB amount from the original reference, and the references of the remaining digital LSB bits are generated in the same manner as described above, and actually, the circuit of fig. 4 performs a step search for M cycles of the last LSB bit.

Fig. 6 is an example of the present invention for a capacitance type successive approximation type analog-to-digital converter. Illustrated is an N-bit ADC circuit configuration in which the sample-and-hold circuit is S_PAnd S_NThe switch is implemented, the comparative reference generation circuit is implemented by a capacitor array, the capacitor array in the dotted ellipse is a traditional capacitor array structure, the same unit capacitors (M-1) are added (M-1 is added at two sides of the difference respectively, M is 8 in figure 6) after the LSB unit capacitor of the traditional capacitor array, the circuit function of figure 3 can be implemented by matching switch logic, wherein the change of the LSB reference level is realized by letting SP_LSBi(i-0, 1, 2 …, M-1) from V_cmSwitch to V_ref(switch before circuit startIs uniformly connected to V_cmOn level) and SN, and_LSBifrom V_cmSwitching to ground effects a decrease in the magnitude of the original reference voltage by one LSB, via SP_LSBiFrom V_cmSwitch to ground and SN_LSBiFrom V_cmSwitch to V_refThe voltage amount of one LSB is added to the value of the original reference voltage amount, thereby realizing the reference level variation pattern shown in fig. 5 (the manner of converting the MSB to the reference voltage amount of (LSB +1) bits is identical to the conventional one). Final circuit only needs to be paired with D_LSB0,D_LSB1,…,D_LSBM-1Realization of a₀D_LSB0+a₁D_LSB1+…+a_M-1D_LSBM-1+D_interceptThe circuit application of the present invention in the capacitance successive approximation analog-to-digital converter, that is, the circuit implementation of fig. 4, can be realized by the operation of (i.e., the output digital code calibration circuit in fig. 6).

Taking the capacitance successive approximation type analog-to-digital converter of fig. 6 as an example, the present invention has the following 2 advantages: firstly, only 2(M-1) unit capacitors and related digital switch control circuits are added on the circuit scale, and LSB bit output digital code calibration circuits are also added, so that the hardware cost is relatively low. Second, the power consumption is increased only for (M-1) cycles, and the capacitor array consumes almost no power during the (M-1) cycles. These increases are characterized by low hardware cost and low power consumption, and the signal-to-noise ratio of the circuit is well improved, especially for a high-precision successive approximation type analog-to-digital converter, while the circuit for improving the signal-to-noise ratio of the successive approximation type analog-to-digital converter is usually at the cost of a complicated hardware calibration circuit and increased large power consumption.

Drawings

FIG. 1 is a schematic diagram of an analog-to-digital converter.

FIG. 2 shows the calculation of a according to the invention₀,a₁,…,a_M-1,D_interceptThe program algorithm flow of (1).

Fig. 3 is a block diagram of an N-bit ADC structure in which LSB bits of the no-output digital code calibration circuit are repeatedly compared M times.

Fig. 4 is a block diagram of an N-bit ADC architecture with LSB bit comparison M times repeated for the output digital code calibration circuit.

Fig. 5 is a diagram illustrating a variation of a reference standard of an N-bit ADC in which LSB bits are repeatedly compared M times.

Fig. 6 is a specific circuit implementation diagram.

Detailed Description

The circuit implementation of fig. 4 will be described below by taking an N-bit capacitance successive approximation analog-to-digital converter shown in fig. 6 as an example.

The comparative reference generating circuit of the circuit shown in fig. 6 is implemented by a capacitor array, the capacitor array in the dotted line ellipse is a conventional capacitor array structure, 7 (7 on both sides of the difference) same unit capacitors are added after the unit capacitor of the LSB bit of the conventional capacitor array, and the circuit function of fig. 3 can be implemented by matching with a switch logic. When the circuit compares the result of (LSB +1) bit, the circuit switches the LSB0 bit according to the comparison result, if the comparison result shows that the reference comparison reference is smaller than the input signal, the new reference is to add a LSB physical quantity (through SP) to the original reference_LSB0From V_cmSwitch to ground and SN_LSB0From V_cmSwitch to V_refImplemented), if the result of the comparison shows that the reference of the reference comparison is greater than the input signal, then the new reference is the physical quantity (by SP) of one LSB subtracted from the original reference_LSB0From V_cmSwitch to V_refAnd SN is_LSB0From V_cmSwitched to ground implementation), fig. 5 schematically shows the reference change method of fig. 6 (in which the MSB is converted to the reference voltage amount of (LSB +1) bits in a manner consistent with the conventional one); the above operation is performed for the following cycles, even in case of circuit comparison error, such as comparison error of LSB2 bits of fig. 5, the circuit still performs reference change according to the above principle according to the comparison result until completing LSB circuit conversion for 8 times, and then the circuit uses formula D according to the 8 digital codes of LSB bits_LSB＝a₀D_LSB0+a₁D_LSB1+…+a₇D_LSB7+D_interceptQuantized code D for calculating LSB bit_LSBAnd in combination with D obtained in the higher position_MSB，…，D_LSB+1The digital code performs quantization of the input signal, such as the digital output code of FIG. 6, where a₀,a₁,…,a_M-1,D_interceptObtained by simulation of the circuit of fig. 6 by the algorithm program of fig. 2, D_LSBThe calculation of (a) is the output digital code calibration circuit of fig. 6. Typically M is an integer power of 2, in this case a power of 3 of 2, and it is also noted that D is calculated from the results obtained by the orderary least square algorithm_LSBTypically a multi-bit decimal, such as D_LSBIs equal to 1.010011, generally D_LSBThree bits after the decimal point are valid (for M to be 8), so D is taken at the time of circuit design_LSBA value of (D) is equal to 1.010 for circuit design, each group D_LSB0，D_LSB1，…，D_LSB7All have unique D_LSBThe values correspond to the values, and all D are taken during circuit design_LSBThree bits after decimal point as D of circuit design_LSBAnd designing a combinational logic circuit of the output digital code calibration circuit according to the value, and finally finishing the design of the whole circuit. The final circuit achieves quantization of (N +3) bits, resulting in a circuit with a high signal-to-noise ratio.

Claims

1. A method for improving the S/N ratio of successive approximation type A/D converter circuit includes such steps as repeating comparison of the last LSB bit of successive approximation type A/D converter for M times>1, obtaining M digital codes, respectively recording the M digital codes as D_LSB0,D_LSB1,…,D_LSBM-1(ii) a Then, according to M digital codes and their weighted values and intercept item D_interceptWeighted summation is carried out to finally obtain D_LSB＝a₀D_LSB0+a₁D_LSB1+…+a_M-1D_LSBM-1+D_interceptDenotes the quantization of the last LSB bit, a_iIs a weighting factor, i ═ 0, 1, 2 …, M-1;

the specific operation steps are as follows:

(1) first, let the input signal y_realsignalN-bit ADC processing with M-times comparison by LSB bits, where y_idealsignalRepresenting the quantized signal, y, input to the ADC_noiseSimulating noise in real circuits, y_realsignalBy y_idealsignalAnd y_noiseComposing a signal representing the actual quantization of the ADC; the N-bit ADC with LSB bits repeatedly compared for M times is realized by performing row-level writing on codes, wherein the codes are obtained after execution: d_MSB,D_MSB-1,…,D_LSB+1,D_LSB0,D_LSB1,…,D_LSBM-1A digital code;

(2) next, the following results from the previous code processing are processed:

D_MSB,D_MSB-1,…,D_LSB+1,D_LSB0,D_LSB1,…,D_LSBM-1and externally inputted y_idealsignalAccording to equation D_y*LSB＝(2^N-1D_MSB+2^N-2D_MSB-1+…+2D_LSB+1+a₀D_LSB0+a₁D_LSB1+…+a_M-1D_LSBM-1+D_intercept) LSB, pair y_idealsignalPerforming approximation to obtain coefficient a of linear fitting through inputting a large amount of data₀,a₁,…,a_M-1,D_intercept；

(3) According to the linear fitting coefficient, according to equation D_y＝2^N-1D_MSB+2^N-2D_MSB-1+…+2D_LSB+1+a₀D_LSB0+a₁D_LSB1+…+a_M- ₁D_LSBM-1+D_interceptAnd carrying out weight summation to obtain:

D_MSB,D_MSB-1,…,D_LSB+1,D_LSBis the quantized digital code of ADC, where D_LSBConsists of an integer bit and a digital decimal bit.

2. An implementation circuit for the method of claim 1, wherein the circuit operation of the MSB to (LSB +1) bits is identical to conventional, except that the last bit is different; specifically, when the circuit compares the result of the (LSB +1) bit, the circuit switches the LSB0 bit according to the comparison result, if the comparison result shows that the reference comparison reference is smaller than the input signal, the new reference is to add a LSB physical quantity to the original reference, and if the comparison result shows that the reference comparison reference is larger than the input signal, the new reference is to subtract a LSB physical quantity from the original reference, and the following remaining digital LSB reference is also generated in the above manner;

an N-bit ADC circuit structure, in which the sample-and-hold circuit is S_PAnd S_NThe switch is realized, the comparative reference generation circuit is realized by a capacitor array, in particular (M-1) same unit capacitors are added after the LSB unit capacitor of the traditional capacitor array, and the circuit function is realized by matched switch logic, wherein the LSB reference level is changed by letting SP_LSBi(i-0, 1, 2 …, M-1) from V_cmSwitch to V_refAnd SN is_LSBiFrom V_cmSwitching to ground effects a decrease in the magnitude of the original reference voltage by one LSB, via SP_LSBiFrom V_cmSwitch to ground and SN_LSBiFrom V_cmSwitch to V_refThe voltage quantity of one LSB is added to the value of the original reference voltage quantity, so that a reference level change mode is realized; finally, the output digital code calibrates the circuit pair D_LSB0,D_LSB1,…,D_LSBM-1Realization of a₀D_LSB0+a₁D_LSB1+…+a_M-1D_LSBM-1+D_interceptAnd (4) performing the operation of (1).