CN107222170A - A kind of pierce circuit - Google Patents
A kind of pierce circuit Download PDFInfo
- Publication number
- CN107222170A CN107222170A CN201710394999.6A CN201710394999A CN107222170A CN 107222170 A CN107222170 A CN 107222170A CN 201710394999 A CN201710394999 A CN 201710394999A CN 107222170 A CN107222170 A CN 107222170A
- Authority
- CN
- China
- Prior art keywords
- phase inverter
- output
- flop
- rest
- electric capacity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
Abstract
The invention provides a kind of pierce circuit, belong to semiconductor integrated circuit technical field.The circuit includes：First phase inverter, the second phase inverter, the 3rd phase inverter, rest-set flip-flop and electric capacity；The input of first phase inverter connects the output of oscillator, and output connects one end of electric capacity and the input of the second phase inverter and the 3rd phase inverter；The other end ground connection of electric capacity；The output of second phase inverter meets the reset terminal R of rest-set flip-flop；The output of 3rd phase inverter connects the set end of rest-set flip-flop；The output of the output termination oscillator of rest-set flip-flop.Present invention utilizes the difference of the upset point of the second phase inverter and the 3rd phase inverter so that voltage on the electric capacity linear change between the two upset points, so as to constitute a stable frequency.Compared to traditional oscillator, this oscillator frequency is mainly overturn controlling a little by the second phase inverter and the 3rd phase inverter, more stable.
Description
Technical field
The invention belongs to semiconductor integrated circuit technical field, and in particular to a kind of pierce circuit.
Background technology
Oscillator is a kind of energy conversion device, and its main function is that direct current energy is converted into certain frequency
AC energy.
Traditional pierce circuit as shown in figure 1, including：It is first phase inverter INV1, the second phase inverter INV2, the 3rd anti-phase
Device INV3 and electric capacity C1；First phase inverter INV1 input meets the output U of oscillatorOUT；Second phase inverter INV2 input connects
One phase inverter INV1 output；3rd phase inverter INV3 input connects the second phase inverter INV2 output, and output connects oscillator
Export UOUT；Electric capacity C1 a 3rd reverser INV3 of termination output, other end ground connection.
The output clock frequency of oscillator can be influenceed by technique, supply voltage and temperature, be sent out in above-mentioned each factor
During changing that the output clock frequency error for causing oscillator is very big, the output clock frequency error of general oscillator can be with
Technique, supply voltage and temperature change reach 20%-30%, or even have reached 50% unexpectedly sometimes, and this gives circuit design band
Very big puzzlement is carried out, it is impossible to meet the normal work demand of circuit.
The content of the invention
To solve the technical problem that existing oscillator frequency error is big, the invention provides a kind of small vibration of frequency error
Device circuit.
A kind of pierce circuit, including：First phase inverter INV1, the second phase inverter INV2, the 3rd phase inverter INV3, RS are touched
Send out device RS1 and electric capacity C1；First phase inverter INV1 input meets the output U of oscillatorOUT, output connect electric capacity C1 one end with
And second phase inverter INV2 and the 3rd phase inverter INV3 input；Electric capacity C1 other end ground connection；Second phase inverter INV2's is defeated
Go out to connect rest-set flip-flop RS1 reset terminal R；3rd phase inverter INV3 output meets rest-set flip-flop RS1 set end S；Rest-set flip-flop
RS1 output end Q meets the output U of oscillatorOUT。
Further, input upset of the input upset point than the 3rd phase inverter INV3 of the second phase inverter INV2
Point is high.
Present invention utilizes the difference of the second phase inverter INV2 and the 3rd phase inverter INV3 upset point so that on electric capacity C1
Voltage the two upset point between linear change, so as to constitute a stable frequency.Compared to traditional oscillator, this
Individual oscillator frequency is mainly overturn controlling a little by the second phase inverter INV2 and the 3rd phase inverter INV3, more stable.
Brief description of the drawings
Fig. 1 is the electrical block diagram of traditional oscillator；
Fig. 2 is the electrical block diagram of the oscillator of the present invention.
Embodiment
To make the object, technical solutions and advantages of the present invention of greater clarity, with reference to embodiment and join
According to accompanying drawing, the present invention is described in more detail.It should be understood that these descriptions are merely illustrative, and it is not intended to limit this hair
Bright scope.In addition, in the following description, the description to known features and technology is eliminated, to avoid unnecessarily obscuring this
The concept of invention.
The technology for causing error big with the influence of technique, supply voltage and temperature to solve existing oscillator frequency is asked
Topic, the invention provides a kind of small pierce circuit of frequency error.As shown in Fig. 2 the pierce circuit includes：First is anti-phase
Device INV1, the second phase inverter INV2, the 3rd phase inverter INV3, rest-set flip-flop RS1 and electric capacity C1；First phase inverter INV1's is defeated
Enter to connect the output U of oscillatorOUT, output connect electric capacity C1 one end and the second phase inverter INV2 and the 3rd phase inverter INV3 it is defeated
Enter；Electric capacity C1 other end ground connection；Second phase inverter INV2 output meets rest-set flip-flop RS1 reset terminal R；3rd phase inverter
INV3 output meets rest-set flip-flop RS1 set end S；Rest-set flip-flop RS1 output end Q meets the output U of oscillatorOUT。
In above-mentioned pierce circuit, the input upset point of the second phase inverter INV2 is than the 3rd phase inverter INV3's
Input upset point is high.That is the input upset point of the second phase inverter INV2 is higher, the 3rd phase inverter INV3 input upset point ratio
It is relatively low.
Present invention utilizes the difference of the second phase inverter INV2 and the 3rd phase inverter INV3 upset point so that on electric capacity C1
Voltage the two upset point between linear change, so as to constitute a stable frequency.Compared to traditional oscillator, this
Individual oscillator frequency is mainly overturn controlling a little by the second phase inverter INV2 and the 3rd phase inverter INV3, more stable.
It should be appreciated that the above-mentioned embodiment of the present invention is used only for exemplary illustration or explains the present invention's
Principle, without being construed as limiting the invention.Therefore, that is done without departing from the spirit and scope of the present invention is any
Modification, equivalent substitution, improvement etc., should be included in the scope of the protection.In addition, appended claims purport of the present invention
Covering the whole changes fallen into scope and border or this scope and the equivalents on border and repairing
Change example.
Claims (2)
1. a kind of pierce circuit, it is characterised in that including：First phase inverter INV1, the second phase inverter INV2, the 3rd phase inverter
INV3, rest-set flip-flop RS1 and electric capacity C1；First phase inverter INV1 input meets the output U of oscillatorOUT, export and meet electric capacity C1
One end and the second phase inverter INV2 and the 3rd phase inverter INV3 input；Electric capacity C1 other end ground connection；Second phase inverter
INV2 output meets rest-set flip-flop RS1 reset terminal R；3rd phase inverter INV3 output meets rest-set flip-flop RS1 set end S；
Rest-set flip-flop RS1 output end Q meets the output U of oscillatorOUT。
2. pierce circuit according to claim 1, it is characterised in that the input upset point of the second phase inverter INV2
Input upset point than the 3rd phase inverter INV3 is high.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710394999.6A CN107222170A (en) | 2017-05-30 | 2017-05-30 | A kind of pierce circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710394999.6A CN107222170A (en) | 2017-05-30 | 2017-05-30 | A kind of pierce circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107222170A true CN107222170A (en) | 2017-09-29 |
Family
ID=59947931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710394999.6A Pending CN107222170A (en) | 2017-05-30 | 2017-05-30 | A kind of pierce circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107222170A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4080319A4 (en) * | 2020-01-16 | 2023-01-18 | Huawei Technologies Co., Ltd. | Clock signal generator, on-chip clock system, and chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060284666A1 (en) * | 2004-12-21 | 2006-12-21 | Actel Corporation, A California Corporation | Voltage-and temperature-compensated rc oscillator circuit |
| US20070268081A1 (en) * | 2006-05-17 | 2007-11-22 | Sanyo Electric Co., Ltd. | Oscillator circuit |
| CN101997520A (en) * | 2009-08-21 | 2011-03-30 | 三星半导体(中国)研究开发有限公司 | Resistance capacitance (RC) oscillator with low power consumption |
| CN102739197A (en) * | 2012-07-17 | 2012-10-17 | 杭州士兰微电子股份有限公司 | RC (remote control) annular oscillator and voltage regulating method thereof |
| CN202889308U (en) * | 2012-10-31 | 2013-04-17 | 珠海市杰理科技有限公司 | High-precision oscillator |
| CN203537351U (en) * | 2013-11-21 | 2014-04-09 | 北京经纬恒润科技有限公司 | Oscillator circuit |
-
2017
- 2017-05-30 CN CN201710394999.6A patent/CN107222170A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060284666A1 (en) * | 2004-12-21 | 2006-12-21 | Actel Corporation, A California Corporation | Voltage-and temperature-compensated rc oscillator circuit |
| US20070268081A1 (en) * | 2006-05-17 | 2007-11-22 | Sanyo Electric Co., Ltd. | Oscillator circuit |
| CN101997520A (en) * | 2009-08-21 | 2011-03-30 | 三星半导体(中国)研究开发有限公司 | Resistance capacitance (RC) oscillator with low power consumption |
| CN102739197A (en) * | 2012-07-17 | 2012-10-17 | 杭州士兰微电子股份有限公司 | RC (remote control) annular oscillator and voltage regulating method thereof |
| CN202889308U (en) * | 2012-10-31 | 2013-04-17 | 珠海市杰理科技有限公司 | High-precision oscillator |
| CN203537351U (en) * | 2013-11-21 | 2014-04-09 | 北京经纬恒润科技有限公司 | Oscillator circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4080319A4 (en) * | 2020-01-16 | 2023-01-18 | Huawei Technologies Co., Ltd. | Clock signal generator, on-chip clock system, and chip |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170929 |
|
| RJ01 | Rejection of invention patent application after publication |