CN107222101B - A kind of integrated converter circuit for light energy collection - Google Patents
A kind of integrated converter circuit for light energy collection Download PDFInfo
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- CN107222101B CN107222101B CN201710344639.5A CN201710344639A CN107222101B CN 107222101 B CN107222101 B CN 107222101B CN 201710344639 A CN201710344639 A CN 201710344639A CN 107222101 B CN107222101 B CN 107222101B
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- 238000004146 energy storage Methods 0.000 claims 1
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- 238000005516 engineering process Methods 0.000 description 7
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- 230000000630 rising effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/66—Regulating electric power
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
- H02S40/00—Components or accessories in combination with PV modules, not provided for in groups H02S10/00 - H02S30/00
- H02S40/30—Electrical components
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/56—Power conversion systems, e.g. maximum power point trackers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Analogue/Digital Conversion (AREA)
- Dc-Dc Converters (AREA)
Abstract
The present invention discloses a kind of integrated converter circuit for light energy collection, this converter circuit have the function of track maximum power point and be suitable for low energy collect miniaturization wearable device, including power stage, voltage sample, current sample, analog multiplier, sampling holdings, dynamic comparer, be added shake numeric type pulse width modulate (DDPWM), drive and oscillator module.DDPWM module is added on the duty cycle signals of control power tube according to pre-designed jitter sequences shakes, voltage sample and current sampling module sample the output voltage and electric current of photovoltaic cell respectively, and they are inputted into analog multiplier, output of the sampling hold circuit in clock signal control two particular moment analog multipliers of down-sampling, and comparing their size relation using dynamic comparer, the duty cycle control signal of power tube increases or reduces according to the output result of dynamic comparer to realize dynamic tracing maximum power point.
Description
Technical field
The present invention relates to a kind of integrated converter circuits for light energy collection, and in particular to a kind of for light energy collection
Boosting type converter integrated circuit with maximum power point tracking function.
Background technique
With the development of miniaturization technologies, wearable device is become more and more popular.But most wearable device
It is still powered using high capacity cell, limits miniaturising for wearable device, and the frequent charge and discharge of battery can drop
The service life of low equipment.Realize that self-powered is the effective scheme for solving the problems, such as this using the clean energy resource in ambient enviroment.Wherein,
Luminous energy becomes a kind of clean energy resource generally used with its higher energy density.
The nonlinear characteristic of photovoltaic cell keeps it different in the output power of different operating point, and different illumination and temperature
The output characteristic curve of photovoltaic cell can also change under environment.Therefore, maximum power point tracking technology (MPPT) is through common
The transfer efficiency of energy is improved in energy collecting system.
In various MPPT techniques, ripple control technology (RCC) tracking speed is fast, precision is high and it is simple to realize.However,
RCC is not suitable for HF switch energy converter, and this disadvantage limits the applications of RCC.MPPT technique based on shake ripple
(DDRCC) pulse width modulating technology (DDPWM) of RCC technology and addition shake is combined and removes tracking maximum power point, not only
The accuracy of MPPT can be increased, and can be applied to the converter of HF switch.
There should be small volume, and for the converter in portable wearable device in order to improve collection of energy
Transfer efficiency, control circuit power consumption should be sufficiently small in converter.The integrated solution of DDRCC wearable is set for portable
Standby great development prospect: on the one hand the integrated circuit based on DDRCC can simplify system design, reduce system power dissipation；Another party
Face DDRCC is compared with traditional RCC technology, can be used in HF switch converter, to reduce the volume of passive element, is realized
The miniaturization of equipment.
Summary of the invention
It is an object of the invention in view of the above-mentioned problems, providing a kind of integrated solution based on DDRCC and realize should
The photovoltaic energy of scheme collects converter ic.
The technical scheme adopted by the invention is as follows: including power stage module, voltage sample resistance R1 and R2, current sampling resistor
Rsense, voltage sample module, current sampling module, analog multiplier, sampling and keep module, dynamic comparer, shake is added
Digital pulsewidth modulation module (DDPWM), drive module, oscillator.
Another termination function of photovoltaic cell output termination current sampling resistor Rsense and voltage sample resistance R1, Rsense
Rate grade module, the input of another termination voltage sample module of R1 and the other end ground connection of voltage sample resistance R2, R2, electric current are adopted
Two input terminals of egf block connect the both ends current sampling resistor Rsense, the output end of voltage sample and current sampling module respectively
Two input terminals of analog multiplier are connect respectively, and the first input end of the output termination sampling and keep module of analog multiplier is adopted
Sample keeps two output ends of module to be connected respectively with the first input end of dynamic comparer and the second input terminal, dynamic comparer
Output end and the output end of oscillator connect two input terminals of DDPWM module, four output ends difference of DDPWM module respectively
Connect the second input terminal of sampling and keep module, the third input terminal of sampling and keep module, dynamic comparer third input terminal and
Drive module input terminal, drive module output end are connected with power stage.
The power stage module includes: inductance Lboost, input storage capacitor Cin, N-type power tube Mn, p-type power tube
One end of Mp and output storage capacitor Cout, inductance Lboost and input storage capacitor Cin and current sampling resistor Rsense phase
Even, the drain electrode of another termination power tube Mn of Lboost and the source electrode of power tube Mp, the source electrode ground connection of power tube Mn, power tube
The drain electrode of Mp meets output storage capacitor Cout and load, power tube Mn are connected with the grid of Mp with drive module.
The DDPWM module includes MUX, four adders, five adders one, shake chain module of meter control, five
Adder two, five digit counters, DPWM comparator, search module of meter control, four digit counters, digital comparator, frequency divider one,
Frequency divider two.
The output end of oscillator connects the input terminal of five digit counters and the input terminal of frequency divider one respectively, frequency divider one it is defeated
Outlet connects the input of the input terminal of four digit counters, the first input end and frequency divider two of shaking chain module of meter control respectively
End, the output end of frequency divider two connect respectively the first input end of four adders, five adders one first input end and
Search module of meter control first input end, dynamic comparer output termination MUX first input end, MUX other two
The output end of input termination 1 and -1, MUX connect the second input terminal of four adders, and the first output end of four adders connects
It connects the second input terminal of shake chain module of meter control, search the second input terminal of module of meter control and the third of four adders
Input terminal, the second output terminal of four adders connect the second input terminal of five adders one, shake chain module of meter control
The first input end of output five adders two of termination, the second input terminal of five adders two connect the defeated of five adders one
Outlet, the output end of five adders one also connect the third input terminal of five adders one, the output termination of five adders two
The first input end of DPWM comparator, the second input terminal of DPWM comparator connect the output end of five digit counters, and DPWM compares
The input terminal of the output termination drive module of device, the output end of four digit counters and the output end for searching module of meter control connect respectively
Two input terminals of digital comparator, the first output end of digital comparator connect sampling and keep module with second output terminal, it
Third output end connect dynamic comparer.
Beneficial effects of the present invention:
The present invention provides the photovoltaic energy collection converter of a kind of integrated solution based on DDRCC and the realization program
Integrated circuit, suitable for the energy collecting system of portable wearable device.On the one hand the integrated circuit based on DDRCC can
Simplify system design, reduces system power dissipation；Another aspect DDRCC is compared with traditional RCC technology, be can be used in HF switch and is turned
Parallel operation realizes the miniaturization of equipment to reduce the volume of passive element.Therefore, the integrated solution of DDRCC is for portable
The great development prospect of formula wearable device.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of system of the invention.
Fig. 2 is the structural schematic diagram of the pulse width modulation circuit of addition shake of the invention.
Fig. 3 is the maximum power point tracking schematic diagram of the invention based on shake ripple.
Fig. 4 is the circuit diagram of multiplier of the invention.
Fig. 5 is the circuit diagram of sampling and keep module of the invention.
Fig. 6 is the circuit diagram of dynamic comparer of the invention.
Specific embodiment
Referring to Fig. 1, a kind of integrated converter circuit for light energy collection of the invention, including power stage module, voltage
Sampling resistor R1 and R2, current sampling resistor Rsense, voltage sample module, current sampling module, analog multiplier, sampling are protected
Hold module, dynamic comparer, the digital pulsewidth modulation module (DDPWM) that shake is added, drive module, oscillator.
Power stage includes in Fig. 1: inductance Lboost, input storage capacitor Cin, N-type power tube Mn, p-type power tube Mp and
Export storage capacitor Cout.One end of inductance Lboost is connected with input storage capacitor Cin and current sampling resistor Rsense,
The drain electrode of another termination power tube Mn of Lboost and the source electrode of power tube Mp, the source electrode ground connection of power tube Mn, power tube Mp
Drain electrode connect output storage capacitor Cout and load, power tube Mn be connected with the grid of Mp with drive module.
Another termination function of photovoltaic cell output termination current sampling resistor Rsense and voltage sample resistance R1, Rsense
Rate grade module, the input of another termination voltage sample module of R1 and the other end ground connection of voltage sample resistance R2, R2, electric current are adopted
Two input terminals of egf block connect the both ends current sampling resistor Rsense, the output end of voltage sample and current sampling module respectively
Two input terminals of analog multiplier are connect respectively, and the first input end of the output termination sampling and keep module of analog multiplier is adopted
Sample keeps two output ends of module to be connected respectively with the first input end of dynamic comparer and the second input terminal, dynamic comparer
Output end and the output end of oscillator connect two input terminals of DDPWM module, four output ends difference of DDPWM module respectively
Connect the second input terminal of sampling and keep module, the third input terminal of sampling and keep module, dynamic comparer third input terminal and
Drive module input terminal, drive module output end are connected with power stage.
Voltage sample and current sampling module obtain the signal directly proportional to photovoltaic cell output end voltage and electric current respectively
VPVAnd IPV, analog multiplier obtains the voltage signal P (t) directly proportional to the output power from photovoltaic cells, and sampling and keep module is being adopted
Sample signal S0And SRdP (t) value is sampled when arrival and obtains P (0) and P (Rd), and dynamic comparer is in enable signal STdRising edge compares P
(0) and the size of P (Rd) and by comparison result VP,CMPIt is conveyed to digital control module DDPWM, DDPWM control module is according in advance
" shake " is added to the duty cycle signals V of control power tube Mn and Mp by designed jitter sequencesPWMOn.The addition of " shake "
Additional ripple can be generated on converter circuit input voltage and current waveform, referred to as " shake ripple "." shake ripple " packet
The information of the maximum power point containing tracking: if P (Rd) > P (0) needs to increase the duty ratio of power tube to track maximum power point；If P
(Rd) < P (0) needs to reduce the duty ratio of power tube.By mechanism described above, converter circuit can dynamically adjust photovoltaic electric
The output voltage and electric current in pond maximize the output power from photovoltaic cells.
Fig. 2 is the structural schematic diagram of the attribute digital pulsewidth modulation module (DDPWM) of addition shake of the invention,
Including MUX, four adders, five adders one, shake chain module of meter control, five adders two, five digit counters, DPWM
Comparator searches module of meter control, four digit counters, digital comparator, frequency divider one, frequency divider two.DDPWM module is on the one hand
According to pre-designed jitter sequences in duty cycle control signal VPWMOn the other hand upper addition shake generates input sample and protects
Hold the sampled signal S of module0、SRdWith the enable signal S of dynamic comparerTd。
In order to realize shake, we devise 9 control signals, it is by low 4 signal 4bit_sel and high 5 letters
Number 5bit_con composition.DDPWM module need three clocks, be respectively CLK_32M, 1MHz of 32MHz CLK_1M and
62.5KHz CLK_62_5K.In 62.5KHz rising edge clock, 5bit_con with Carry_out signal is added to obtain new
5bit_con value.In 62.5KHz rising edge clock, by multiple selector MUX, according to the output V of dynamic comparerP,CMPChange
The value of 4bit_sel: if VP,CMPAdd 1 for Isosorbide-5-Nitrae bit_sel；If VP,CMPSubtract 1 for 0,4bit_sel.It shakes in chained list module
16 jitter sequences are stored, each jitter sequences are made of 16 " jitter values ", are selected in jitter sequences according to 4bit_sel
One, and one " jitter value " in selected jitter sequences is sequentially output in 1MHz rising edge clock.5bit_con and " shake
Value " is added the input Ref that can obtain DPWM comparator.The purpose of attribute number DPWM control module is to realize a duty
Than for Ref/25Square wave control signal VPWM.Five digit counters use 32MHz clock, when counter is counted as 0, DPWM ratio
Compared with device output signal VPWMIt is set to 1；When counter counts count to Ref value, VPWMFall to 0.Other three output signal S0、SRdWith
STdGeneration mechanism it is as follows: four digit counters use 1MHz clock, when counter is counted as 0, S01 is set to, in other situations
S0Equal to 0；When counter counting reaches 15, STdIt is set to 1, is all 0 in other situations.Rd is determined by 4bit_sel, by looking into
Table method is realized.When counter counting reaches Rd, SRdIt is set to 1, is all 0 in other situations.
" three-stage " shake chained list of the invention is as shown in table 1 below.Traditional Digital dither is in several switch periods
To duty ratio carry out a least significant bit (LSB) adjustment so that average duty ratio two neighbouring quantization duty ratios it
Between, to increase the resolution ratio of duty ratio in the case where not increasing digital controlled signal digit.The shake line of two-part shake
Wave is too small, relatively high to the required precision of comparator, so shaking present invention uses " three-stage " and devising " three-stage "
Shake chained list.The present invention selects 5 signal 5bit_con to control duty ratio, and the eigenresolution of duty ratio is 1/32, i.e.,
1LSB=1/32, while 4bit_sel is used to select one in shake chained list in 16 jitter sequences, 16 switch periods
As a shake period, the duty cycle resolution after addition shake is 1/ (32*16)=1/512.It shakes in chained list, " shake
Value " 2,1 or 0 respectively indicates the number for adding the additional LSB in each switch periods.It shakes in chained list, adjacent rows shake sequence
The summation difference 1 of the jitter value of column, to realize that average duty ratio increases by 1/512 when 4bit_sel signal increases by 1.Here
Special carry mechanism is needed, when 4bit_sel increases to 0111 from 0110, carry signal Carry_out is 1,
5bit_con increases by 1；When 4bit_sel is reduced to 0110 from 0111, Carry_out is that -1,5bit_con subtracts 1.Difference shake
The corresponding sampling instant Rd of sequence is different, is marked in table 1 with solid line, and Rd sampling instant is distributed in the 8 to 11st of shake period
Between switch periods.Look-up table means in Fig. 2 can be found out and Rd value corresponding to solid line position in table 1.
Table 1
Fig. 3 is the maximum power point tracking schematic diagram of the invention based on shake ripple, and Fig. 3 (a) is logical for converter circuit
Cross the process for increasing power tube duty ratio to track maximum power point.Wherein, S0And SRdRespectively represent two samplings noted earlier
Signal, VP,CMPRepresent the output of dynamic comparer as a result, P (t) representative simulation multiplier output signal, VPVVoltage is represented to adopt
The output signal of egf block, IPVRepresent the output signal of current sampling module.Small switching harmonics are illustrated in figure and due to adding
Enter shake ripple big caused by " shake ".In Fig. 3 (a), P (Rd) is always more than P (0), the output result of dynamic comparer
VP,CMPAlways it is 1, needs to increase duty ratio always to track maximum power point.Fig. 3 (b) indicates that converter circuit has worked most
Near high-power point.P (Rd) and P (0) are approximately equal, the output result V of dynamic comparerP,CMPIt is jumped back and forth between 1 and 0,
Show converter circuit work near maximum power point.
Fig. 4 is the circuit diagram for the analog multiplier that the present invention uses.Including PMOS tube M1, M2, M4~M6, M11~M13,
M15, M16, NMOS tube M3, M7~M10, M14, current source bias I1~I4, resistance R3, R4.
+ Vy/2 signal connects the grid of M1 and M2, and the source electrode of M1 meets Vdd, and the drain electrode of M1 connects the source electrode of M2 and the grid of M3 respectively
Pole, the drain electrode of M2 meet gnd, and the drain electrode of M3 meets Vdd by current source I1 and is connected with the grid of M4, and the drain electrode of M3 is grounded by I2
And it is connected with the drain electrode of M4, the source electrode of M7 with the source electrode of M8, the source electrode of M4 meets Vdd, and+Vx/2 signal connects the grid of M5 and M6,
The source electrode of M5 meets Vdd, and the drain electrode of M6 meets gnd, and the drain electrode of M5 is connected with the grid of the source electrode of M6, the grid of M7, M10, the leakage of M7
Pole meets Vdd by resistance R3 and is connected with the drain electrode of M9, an output port Vo+ for draining while being also multiplier of M7,
M8 is connected with the drain electrode of M10 and is connected by R4 and Vdd, an output port for draining while being also multiplier of M10
The grid of Vo-, M8, M9 are connected while connecing the drain electrode of M11 and the source electrode of M12, and the source electrode of M9, M10 are connected while connecting the leakage of M13
The source electrode of pole and M14 ,-Vx/2 signal connect the grid of M11, M12, and the source electrode of M11 connects Vdd, the grounded drain of M12, the source electrode of M13
Vdd is met, the grid of M13 connects drain electrode and one end of I3 of M14, and the source electrode of a termination M14 of another termination Vdd of I3, I4 are another
End ground connection, the grid of M14 connect drain electrode and the source electrode of M16 of M15, and the grid of M15 and M16 connect-Vy/2 signal, and the source electrode of M15 connects
The grounded drain of Vdd, M16.
Fig. 5 is sampling and keep module circuit diagram of the invention, including transmission gate TG1, TG2, TG3, sampling capacitance C1, C2,
C3, dynamic comparer.In sampled signal S0、SRdWith dynamic comparer enable signal STdUnder control, in S0To be opened when high level
TG1 is sampled P (t), is denoted as P (0), is stored on C1.In SRdTo open TG2 when high level, samples P (t), be denoted as P (Rd), deposit
Storage is on C2.In STdRising edge triggering dynamic comparer it is more primary, and comparison result is stored on C3 by TG3, note
For VP,CMP。
Transmission gate is made of a NMOS tube and a PMOS tube.By taking TG1 as an example, the drain electrode of NMOS tube meets P (t), NMOS
The source electrode of pipe meets the reverse input end Vin- of sampling capacitance C1 top crown and dynamic comparer, and the grid of NMOS tube connects sampled signal
S0, S0It is connected by phase inverter with the grid of PMOS tube, the source electrode of PMOS tube connects P (t) signal, and the drain electrode of PMOS tube connects pole on C1
Plate.TG2 is by SRdThe input of control, TG2 terminates P (t), the positive input of output termination sampling capacitance C2 and dynamic comparer
Vin+.TG3 is by STdControl, STdAlso it is connected simultaneously with the clock enable end Clk of dynamic comparer, the input of TG3 connects Dynamic comparison
The positive output end Out+ of device, the output of TG3 connect the top crown of sampling capacitance C3.
Fig. 6 is dynamic comparer circuit diagram used in the present invention, by NMOS tube M17~M21, M27, M30, M31, M33,
M34, M37, PMOS tube M22~M25, M26, M28, M29, M32, M35, M36 composition.The grid of M17 connects clock enable signal
Clk, Clk also connect the grid of M22 and M25, the source electrode ground connection of M17, and the drain electrode of M17 is connected with the source electrode of M18 and M19, the leakage of M18
Pole connects the source electrode of M20, and the grid of M20 meets the drain electrode binding place X of the positive input Vin+, M20 of dynamic comparer, and node X is also
It is connected with the grid of the drain electrode of M22, the drain electrode of M23, M19, M24, M26, M27, the drain electrode of M19 connects the source electrode of M21, the grid of M21
Pole connect drain electrode the binding place Y, node Y of the reverse input end Vin-, M21 of dynamic comparer also with the drain electrode of M24, the drain electrode of M25,
The grid of M18, M23, M36, M37 are connected, and the source electrode of M22~M25 is all connected with Vdd, and M26 and M27, M36 and M37 are separately constituted
The drain electrode of two phase inverters, M26 and M27 are connected together and are connected with M28 with the grid of M31, and the drain electrode of M36 and M37 connect
Be connected together and with M34 with the grid of M35, the source electrode of M26, M28, M29, M32, M35, M36 meet Vdd, M27, M31, M34,
The source electrode of M37 is grounded, and the positive output end Out+ of dynamic comparer connects the drain electrode of M28~M30 and the grid of M32, M33, dynamic
The inverse output terminal Out- of comparator connects the drain electrode of M32, M33, M35 and the grid of M29, M30, the drain electrode of the source electrode and M31 of M30
Connect, the drain electrode of the source electrode and M34 of M33 connects.
Claims (2)
1. a kind of integrated converter circuit for light energy collection, including power stage module, voltage sample resistance R1 and R2, electric current
Sampling resistor Rsense, voltage sample module, current sampling module, analog multiplier, sampling and keep module, dynamic comparer,
Digital pulsewidth modulation module, the drive module, oscillator of shake is added, which is characterized in that photovoltaic cell output termination electricity
Flow another termination power stage module of sampling resistor Rsense and voltage sample resistance R1, Rsense, another termination voltage of R1
The input of sampling module and the other end ground connection of voltage sample resistance R2, R2, two input terminals of current sampling module connect respectively
The output end of the both ends current sampling resistor Rsense, voltage sample and current sampling module connect analog multiplier respectively two are defeated
Enter end, the first input end of the output termination sampling and keep module of analog multiplier, two output ends point of sampling and keep module
It is not connected with the first input end of dynamic comparer and the second input terminal, the output end of dynamic comparer and the output end of oscillator
Two input terminals that the digital pulsewidth modulation module of shake is added are connect respectively, and the digital pulsewidth modulation mould of shake is added
Four output ends of block connect the second input terminal of sampling and keep module, the third input terminal of sampling and keep module, dynamic ratio respectively
Compared with device third input terminal and drive module input terminal, drive module output end is connected with power stage module, and the addition is trembled
Dynamic digital pulsewidth modulation module, including MUX, four adders, five adders one, shake chain module of meter control, five
Position adder 2, DPWM comparator, searches module of meter control, four digit counters, digital comparator, frequency divider at five digit counters
One, frequency divider two, the output end of oscillator connect the input terminal of five digit counters and the input terminal of frequency divider one, frequency divider one respectively
Output end connect respectively four digit counters input terminal, shake chain module of meter control first input end and frequency divider two it is defeated
Enter end, the output end of frequency divider two connect respectively the first input end of four adders, five adders one first input end with
And the first input end of module of meter control is searched, and the first input end of the output termination MUX of dynamic comparer, other the two of MUX
The output end of a input termination 1 and -1, MUX connect the second input terminal of four adders, the first output end of four adders
The of second input terminal of connection shake chain module of meter control, the second input terminal for searching module of meter control and four adders
Three input terminals, the second output terminal of four adders connect the second input terminal of five adders one, shake chain module of meter control
Output five adders two of termination first input end, the second input terminal of five adders two connects five adders one
Output end, the output end of five adders one also connect the third input terminal of five adders one, the output end of five adders two
The first input end of DPWM comparator is connect, the second input terminal of DPWM comparator connects the output end of five digit counters, DPWM ratio
Compared with the input terminal of the output termination drive module of device, the output end of four digit counters and the output end difference for searching module of meter control
Two input terminals of digital comparator are connect, the first output end of digital comparator connects sampling and keep module with second output terminal,
Its third output end connects dynamic comparer.
2. a kind of integrated converter circuit for light energy collection according to claim 1, which is characterized in that power stage mould
Block includes: inductance Lboost, input storage capacitor Cin, N-type power tube Mn, p-type power tube Mp and output storage capacitor Cout,
One end of inductance Lboost is connected with input storage capacitor Cin and current sampling resistor Rsense, another termination function of Lboost
The drain electrode of rate pipe Mn and the source electrode of power tube Mp, the source electrode ground connection of power tube Mn, the drain electrode of power tube Mp connect output energy storage electricity
Hold Cout and load, power tube Mn are connected with the grid of Mp with drive module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710344639.5A CN107222101B (en) | 2017-05-16 | 2017-05-16 | A kind of integrated converter circuit for light energy collection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710344639.5A CN107222101B (en) | 2017-05-16 | 2017-05-16 | A kind of integrated converter circuit for light energy collection |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930026A (en) * | 2009-06-22 | 2010-12-29 | 冠捷投资有限公司 | Electronic device with power loss detection function |
| CN101944841A (en) * | 2010-09-21 | 2011-01-12 | 电子科技大学 | Inversion control digital filter |
| CN102156504A (en) * | 2011-04-14 | 2011-08-17 | 杭州矽力杰半导体技术有限公司 | Solar-cell panel maximum power tracking device, tracking method and solar power supply device using the same |
| CN203326882U (en) * | 2012-12-24 | 2013-12-04 | 苏州硅智源微电子有限公司 | Simulation multiplier in switch voltage-stabilizer feedback loop |
| CN103499992A (en) * | 2013-08-28 | 2014-01-08 | 浙江工业大学 | Photovoltaic array MPPT interface circuit with coupling inductor |
| CN203465347U (en) * | 2013-09-02 | 2014-03-05 | 南京埃科孚电子科技有限公司 | Inductive current zero crossing detection circuit applied to boost power factor correction |
| CN104320124A (en) * | 2014-10-15 | 2015-01-28 | 西安交通大学 | Self-powered interface circuit for thermoelectric energy collection |
| CN104362851A (en) * | 2014-10-15 | 2015-02-18 | 西安交通大学 | DC-DC converter control system |
| CN106371495A (en) * | 2016-10-14 | 2017-02-01 | 西安电子科技大学 | Micro energy capture MPPT control circuit and energy capture circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6003749B2 (en) * | 2013-03-22 | 2016-10-05 | 富士通株式会社 | Modulation apparatus and modulation method |
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Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930026A (en) * | 2009-06-22 | 2010-12-29 | 冠捷投资有限公司 | Electronic device with power loss detection function |
| CN101944841A (en) * | 2010-09-21 | 2011-01-12 | 电子科技大学 | Inversion control digital filter |
| CN102156504A (en) * | 2011-04-14 | 2011-08-17 | 杭州矽力杰半导体技术有限公司 | Solar-cell panel maximum power tracking device, tracking method and solar power supply device using the same |
| CN203326882U (en) * | 2012-12-24 | 2013-12-04 | 苏州硅智源微电子有限公司 | Simulation multiplier in switch voltage-stabilizer feedback loop |
| CN103499992A (en) * | 2013-08-28 | 2014-01-08 | 浙江工业大学 | Photovoltaic array MPPT interface circuit with coupling inductor |
| CN203465347U (en) * | 2013-09-02 | 2014-03-05 | 南京埃科孚电子科技有限公司 | Inductive current zero crossing detection circuit applied to boost power factor correction |
| CN104320124A (en) * | 2014-10-15 | 2015-01-28 | 西安交通大学 | Self-powered interface circuit for thermoelectric energy collection |
| CN104362851A (en) * | 2014-10-15 | 2015-02-18 | 西安交通大学 | DC-DC converter control system |
| CN106371495A (en) * | 2016-10-14 | 2017-02-01 | 西安电子科技大学 | Micro energy capture MPPT control circuit and energy capture circuit |
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