CN107219690B

CN107219690B - Display panel and display device

Info

Publication number: CN107219690B
Application number: CN201710592804.9A
Authority: CN
Inventors: 李康; 严茂程; 秦丹丹; 熊小三; 周齐; 张明天; 金祥; 仇玲珑; 甘小鹏
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2017-07-19
Filing date: 2017-07-19
Publication date: 2020-04-03
Anticipated expiration: 2037-07-19
Also published as: CN107219690A

Abstract

The application discloses display panel and display device, wherein display panel includes: the device comprises a first substrate, a second substrate and a plurality of spacing columns arranged between the first substrate and the second substrate; a plurality of data signal lines extending in a first direction and sequentially arranged in a second direction, and a plurality of gate lines sequentially arranged in the first direction and extending in the second direction; a spacer column bolster corresponding to the spacer column is further arranged between the first substrate and the second substrate and comprises two protruding parts with the same height and a groove positioned between the two protruding parts; the first substrate is also provided with an electrode layer and a first alignment film layer, wherein the electrode layer comprises a first electrode layer, a first insulating layer and a second electrode layer which are sequentially arranged; the two protruding parts respectively comprise a first electrode layer, a first insulating layer, at least one layer of liner layer and a first alignment film layer which are sequentially arranged, and the liner layer and the second electrode layer are arranged on the same layer. So, take place to slide when effectively avoiding space post and space post bolster contact.

Description

Display panel and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

With the continuous development of liquid crystal display technology, liquid crystal displays are increasingly popular with people due to the advantages of light and thin body, space saving, power saving, low radiation, soft picture and the like.

Fig. 1 is a cross-sectional view of a related art display panel, and fig. 2 is another cross-sectional view of the related art display panel. As can be seen from fig. 1, the display panel 300 includes a first substrate 301 and a second substrate 302 disposed opposite to each other, and a spacer 303 disposed between the first substrate 301 and the second substrate 302, a spacer pillow region 304 corresponding to the spacer 303 is disposed on the first substrate 301, and the spacer pillow region 304 includes a common electrode layer 305, an insulating layer 306, and a first alignment film layer 307, which are sequentially disposed, as shown in fig. 2. When the display panel 300 is pressed, the spacer 303 will contact the spacer bolster area 304. Fig. 3 is a diagram illustrating a positional relationship between orthogonal projections of the spacers 303 and the spacers 303 on the plane of the first substrate 301 in the prior art, and it can be seen from fig. 3 that when the display panel 300 is pressed, a part of the spacers 303 is in contact with the protrusions of the spacer pad areas 304, and the other part of the spacers is suspended. When the display panel 300 is pressed, one part of the spacer 303 is in contact with the spacer bolster area 304, and the other part is in a suspended state, so that the spacer 303 is unevenly stressed and is easy to slide; in addition, considering that the first alignment film 307 is directly contacted with the insulating layer 306, the adhesion between the first alignment film 307 and the insulating layer 306 is poor, the first alignment film 307 at the spacer pillow area 304 is easily damaged by the top when the spacer 303 slides, when the first alignment film 307 is damaged by the top and falls off, the phenomenon of poor light leakage caused by abnormal alignment occurs, and the phenomenon of poor broken bright spots also occurs in the display area when the alignment film fragments move to the display area of the display panel 300.

Disclosure of Invention

In view of this, the technical problem to be solved in the present application is to provide a display panel and a display device, in which a spacer is disposed between a first substrate and a second substrate, the spacer includes two protrusions with the same height, and when the spacer contacts with the spacer, the spacer contacts with the two protrusions at the same time, so as to effectively block the spacer from sideslipping.

In order to solve the technical problem, the following technical scheme is adopted:

in a first aspect, the present application provides a display panel, including a first substrate, a second substrate, and a plurality of spacers disposed between the first substrate and the second substrate;

a spacer column bolster corresponding to the spacer column is further arranged between the first substrate and the second substrate and comprises two protruding parts with the same height and a groove positioned between the two protruding parts, wherein the height is a distance in a direction perpendicular to a plane where the first substrate is located;

the first substrate is further provided with an electrode layer and a first alignment film layer, and the electrode layer comprises a first electrode layer, a first insulating layer and a second electrode layer which are sequentially arranged;

the two protruding parts respectively comprise the first electrode layer, the first insulating layer, at least one liner layer and the first alignment film layer which are sequentially arranged, and the liner layer and the second electrode layer are arranged on the same layer; the groove comprises the first insulating layer and the first alignment film layer which are sequentially arranged.

Optionally, wherein:

the backing layer has a thickness D1,

optionally, wherein:

the first electrode layer is a common electrode layer, and the second electrode layer is a pixel electrode layer.

Optionally, wherein:

the width that the space bar is close to space bar bolster one end is greater than the width of recess, the one end that the space bar is close to the space bar bolster is in the orthographic projection on first base plate place plane respectively with two the bellying is in the orthographic projection overlap on first base plate place plane forms first overlap region and second overlap region.

Optionally, wherein:

the area of the first overlap region is equal to the area of the second overlap region.

Optionally, wherein:

the first substrate further comprises a thin film transistor array layer, and the thin film transistor array layer, the electrode layer and the first alignment film layer are sequentially arranged on the surface of one side, facing the second substrate, of the first substrate;

the thin film transistor array layer includes a semiconductor active layer including a source region, a drain region, and a channel region between the source region and the drain region;

the orthographic projection of the groove on the plane of the first substrate is overlapped with the orthographic projection of the channel region on the plane of the first substrate.

Optionally, wherein:

the thin film transistor array layer, the electrode layer and the first alignment film layer are positioned on the surface of one side, facing the second substrate, of the first substrate;

the thin film transistor array layer further comprises a grid metal layer and a source drain metal layer, wherein the grid metal layer is located on one side, close to the first substrate, of the semiconductor active layer, or the grid metal layer is located on one side, far away from the first substrate, of the semiconductor active layer.

Optionally, wherein:

the orthographic projection of the groove on the plane where the first substrate is located is one or a combination of a plurality of square shapes, circular shapes, oval shapes, rhombic shapes or cross shapes.

Optionally, wherein:

the orthogonal projection of one end of the spacer close to the spacer bolster on the plane where the first substrate is located is regular hexagon, circle, ellipse or square.

Optionally, wherein:

the second substrate comprises a pixel region layer and a second alignment film layer, the pixel region layer and the second alignment film layer are sequentially arranged on the surface, facing one side of the first substrate, of the second substrate, and one end, away from the spacer pillow, of the spacer is fixed on the second substrate.

In a second aspect, the present application provides a display device, including a display panel, where the display panel is the display panel provided in the present application.

Compared with the prior art, this application display panel and display device, reached following effect:

in the display panel and the display device provided by the invention, the spacer bolster corresponding to the spacer is arranged between the first substrate and the second substrate, when the spacer contacts with the spacer bolster, the spacer bolster can simultaneously contact with the two convex parts in the spacer bolster, and because the heights of the two convex parts in the spacer bolster are the same, compared with the prior art, the influence of the section difference of the spacer bolster is eliminated, the spacer does not deviate after contacting with the two convex parts, the phenomenon that the spacer contacts with the spacer bolster to slide when the display panel is stressed is effectively avoided, the phenomenon that the first alignment film is damaged and matched due to the sliding of the spacer is also avoided, and compared with the prior art, the phenomena that the display panel has poor light leakage and poor broken bright spots due to the fact that the alignment film in the spacer bolster area is damaged and falls off are fundamentally avoided.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1 is a cross-sectional view of a prior art display panel;

FIG. 2 is another cross-sectional view of a prior art display panel;

FIG. 3 is a diagram showing the positional relationship between the spacers and spacers of the prior art in the orthographic projection of the spacers on the plane of the first substrate;

FIG. 4 is a cross-sectional view of a display panel according to the present application;

fig. 5 is a schematic view illustrating a first substrate of a display panel according to the present disclosure;

fig. 6 is a schematic diagram illustrating a second substrate of the display panel according to the present application;

FIG. 7 is a cross-sectional view of another display panel provided by the present application;

FIG. 8 is a cross-sectional view of another display panel provided by the present application;

fig. 9 is a top view of the display panel provided in the present application;

fig. 10 is a diagram illustrating an orthographic projection position relationship of the spacer, the spacer bolster and the first electrode layer provided in the present application on the plane of the first substrate;

FIG. 11 is a cross-sectional view of another display panel provided by the present application;

FIG. 12 is a cross-sectional view of another display panel provided by the present application;

fig. 13 is a schematic structural diagram of a display device provided in the present application.

Detailed Description

As used in the specification and in the claims, certain terms are used to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This specification and claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. "substantially" means within an acceptable error range, and a person skilled in the art can solve the technical problem within a certain error range to substantially achieve the technical effect. Furthermore, the term "coupled" is intended to encompass any direct or indirect electrical coupling. Thus, if a first device couples to a second device, that connection may be through a direct electrical coupling or through an indirect electrical coupling via other devices and couplings. The description which follows is a preferred embodiment of the present application, but is made for the purpose of illustrating the general principles of the application and not for the purpose of limiting the scope of the application. The protection scope of the present application shall be subject to the definitions of the appended claims.

Fig. 4 is a cross-sectional view of the display panel of the present application, fig. 5 is a schematic diagram of a structure of a first substrate of the display panel of the present application, and fig. 6 is a schematic diagram of a structure of a second substrate of the display panel of the present application. As can be seen from fig. 4, the display panel 100 includes a first substrate 10 and a second substrate 20 disposed opposite to each other, and a liquid crystal 30 is filled between the first substrate 10 and the second substrate 20.

Referring to fig. 5, the first substrate 10 includes a first base 11, and the first base 11 is made of any suitable insulating material and may be transparent, translucent or opaque. A buffer layer 12 is provided on the first substrate 11, and typically the buffer layer 12 covers the entire upper surface of the substrate. A thin film transistor array layer 40 is disposed on the upper surface of the buffer layer 12, and an electrode layer 50 (including a first electrode layer 51, a first insulating layer 52, and a second electrode layer 53) and a first alignment film layer 60 are disposed on the thin film transistor array layer 40. In general, the thin film transistor array layer 40 includes:

a semiconductor active layer 25 on the buffer layer 12, the semiconductor active layer 25 including a source region and a drain region formed by doping N-type impurity ions or P-type impurity ions, a region between the source region and the drain region being a channel region in which impurities are not doped, the semiconductor active layer 25 being formed by changing amorphous silicon into polycrystalline silicon through crystallization of amorphous silicon, and in order to crystallize the amorphous silicon, various methods such as a Rapid Thermal Annealing (RTA) method, a Solid Phase Crystallization (SPC) method, an Excimer Laser Annealing (ELA) method, a Metal Induced Crystallization (MIC) method, a Metal Induced Lateral Crystallization (MILC) method, or a Sequential Lateral Solidification (SLS) method may be used;

a gate insulating layer 26 over the semiconductor active layer 25, the gate insulating layer 26 including an inorganic layer such as silicon oxide, silicon nitride, or metal oxide, and may include a single layer or multiple layers;

the first metal layer 21, which is located in a specific region on the gate insulating layer 26 and serves as a gate electrode of the thin film transistor, may include a single layer or multiple layers of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), or chromium (Cr), or an alloy such as aluminum (Al): neodymium (Nd) alloy, molybdenum (Mo): tungsten (W) alloy;

an interlayer insulating layer 24 over the first metal layer 21, the interlayer insulating layer 24 being formed of an insulating inorganic layer such as silicon oxide or silicon nitride, or an insulating organic layer;

a second metal layer 22 on the interlayer insulating layer 24 as a source electrode 27 and a drain electrode 28 of the thin film transistor, the source electrode 27 and the drain electrode 28 being electrically connected to a source region and a drain region of the semiconductor active layer 25 through contact holes 29, respectively, which are formed by selectively removing the gate insulating layer 26 and the interlayer insulating layer 24; and

the passivation layer 23 is located on the second metal layer, and the passivation layer 23 may be formed of an inorganic layer such as silicon oxide or silicon nitride, or may be formed of an organic layer.

In addition, referring to fig. 6, the second substrate 20 includes a second base 71, a pixel region layer 72 disposed on the second base 71, a second alignment film layer 73, and a spacer 80.

Referring to fig. 7, fig. 7 is another cross-sectional view of the display panel provided in the present application, in which the first substrate 10 and the second substrate 20 are disposed opposite to each other to form a closed space, and the spacers 80 and the liquid crystal 30 are located in the closed space.

Specifically, fig. 8 is a cross-sectional view of a display panel 100 provided in the present application, and in conjunction with fig. 7 and 8, the display panel 100 includes a first substrate 10, a second substrate 20, and a plurality of spacers 80 disposed between the first substrate 10 and the second substrate 20;

a spacer pillow 81 corresponding to the spacer 80 is further disposed between the first substrate 10 and the second substrate 20, the spacer pillow 81 includes two protrusions 90 and 90 'having the same height and a groove 91 between the two protrusions 90 and 90', wherein a height h of the spacer pillow 81 is a distance in a direction perpendicular to a plane of the first substrate 10;

an electrode layer 50 and a first alignment film layer 60 are further disposed on the first substrate 10, wherein the electrode layer 50 includes a first electrode layer 51, a first insulating layer 52 and a second electrode layer 53 disposed in sequence;

the two protruding portions 90 and 90' respectively include a first electrode layer 51, a first insulating layer 52, at least one liner layer 92, and a first alignment film layer 60, which are sequentially disposed, and the liner layer 92 and the second electrode layer 53 are disposed in the same layer; the groove 91 includes the first insulating layer 52 and the first alignment film layer 60 sequentially disposed.

Specifically, please refer to fig. 8, fig. 8 is a schematic structural diagram of a spacer 80 and a spacer bolster 81 corresponding to the spacer 80 in the present application. In fig. 8, the spacer bolster 81 corresponding to the spacer 80 includes two protrusions 90 and 90 ', the two protrusions 90 and 90 ' have the same height in a direction perpendicular to the plane of the first substrate 10, when the spacer 80 contacts the spacer bolster 81 due to the pressure of the display panel 100, the spacer 80 will simultaneously contact the two protrusions 90 and 90 ' of the spacer bolster 81, since the two protrusions 90 and 90 ' of the spacer bolster 81 have the same height, the effect of the step difference of the spacer bolster 81 is eliminated compared with the prior art, the spacer 80 will not shift after contacting the two protrusions 90 and 90 ', the sliding phenomenon of the spacer 80 contacting the spacer bolster 81 when the display panel 100 is stressed is effectively avoided, and the damage of the first alignment film layer 60 caused by the sliding of the spacer 80 is also avoided, compared with the prior art, the phenomena of poor light leakage and poor broken bright spots of the display panel 100 caused by damage and falling of the alignment film due to the action of the spacer pillows 81 on the alignment film are fundamentally avoided. In addition, in the present application, a first electrode layer 51, a first insulating layer 52, a second electrode layer 53 and a first alignment film layer 60 are sequentially disposed on a first substrate 10, a spacer pillow 81 is formed on the basis of the existing structure of the first substrate 10, two protrusions 90 and 90 'respectively include the first electrode layer 51, the first insulating layer 52, at least one liner layer 92 and the first alignment film layer 60 which are sequentially disposed, a groove 91 between the two protrusions 90 and 90' includes the first insulating layer 52 and the first alignment film layer 60 which are sequentially disposed, and the liner layer 92 and the second electrode layer 53 are disposed in the same layer, so that the liner layer 92 is introduced on the basis of the existing structure of the first substrate 10, two protrusions with the same height are formed by the raising action of the liner layer 92, thereby reliably supporting the spacer pillar 80 when the display panel 100 is pressed, avoid producing the poor influence of section, prevent that spacer 80 from taking place to slide, moreover through backing layer 92 with two bellying 90 and 90' bed hedgehopping, can also play certain cushioning effect to spacer 80 when display panel pressurized.

Optionally, the backing layer provided herein has a thickness D1,

specifically, the present application designs the thickness of the backing layer in both bosses 90 and 90' to be

In this case, the two protrusions 90 and 90' can be raised without contacting the spacer 80, so that the display panel 100 provided by the present application has a certain pressing space. In addition, the thickness of the gasket layer in the two protrusions 90 and 90 'is designed to be the same in this application, so that the heights of the two protrusions 90 and 90' are the same, and at the same time, when the display panel 100 is pressed to make the spacer 80 contact the two protrusions 90 and 90 ', the bearing strength of the two protrusions 90 and 90' is more consistent. In the actual production process, the height of the backing layer in the two projections 90 and 90' may be selected, for example

And the like, and this is not particularly limited in the present application.

In addition, the backing layer and the second electrode layer 53 are arranged on the same layer, and in an actual production process, the backing layer can be formed by a material with lower surface roughness, so that the adhesion strength between the first alignment film layer 60 and the backing layer 92 is increased, and the phenomena of poor light leakage and poor broken bright points caused by the fact that the first alignment film layer 60 falls off from the backing layer 92 when the first alignment film layer 60 contacts and bears the force with the spacer columns 80 are avoided. Specifically, the pad layer 92 in the present application may be formed using a material different from that of the second electrode layer 53, or may be formed using the same material as that of the second electrode layer 53. When the pad layer 92 is made of the same material as the second electrode layer 53, the pad layer 92 can be manufactured while the second electrode layer 53 is manufactured in the production process, so that a process for manufacturing the pad layer 92 separately is omitted, the production process is saved, and the production efficiency is improved.

Alternatively, the first electrode layer 51 is a common electrode layer, and the second electrode layer 53 is a pixel electrode layer.

Specifically, please refer to fig. 5, in the present application, the first electrode layer 51 is a common electrode layer, the second electrode layer 53 is a pixel electrode layer, the pixel electrode layer is electrically connected to the drain electrode 28 of the thin film transistor through a via hole, and different image displays of the display panel 100 can be realized through the control effect of the thin film transistor on the pixel electrode.

Optionally, the width of the end of the spacer 80 close to the spacer bolster 81 is greater than the width of the groove 91, and an orthographic projection of the end of the spacer 80 close to the spacer bolster 81 on the plane of the first substrate 10 overlaps with an orthographic projection of the two protrusions 90 and 90' on the plane of the first substrate 10, respectively, to form the first overlapping area 82 and the second overlapping area 83.

Specifically, fig. 9 is a top view of the display panel 100 provided in the present application, and it can be seen from fig. 9 that the display area of the present application includes a plurality of gate lines 95 extending along a first direction and arranged along a second direction, and a plurality of data signal lines 96 arranged along the first direction and arranged along the second direction, and the first direction and the second direction are crossed. With reference to fig. 8, the width D2 of the spacer 80 near one end of the spacer pillow 81 is greater than the width D3 of the groove 91, wherein the width D2 of the spacer 80 near one end of the spacer pillow 81 is the maximum distance of the spacer 80 near one end of the spacer pillow 81 in the extending direction of the gate line 95, and the width D3 of the groove 91 is the maximum distance of the groove 91 in the extending direction of the gate line 95. In addition, fig. 10 is a diagram illustrating an orthographic projection position relationship of the spacer, the spacer bolster and the first electrode layer on the plane of the first substrate, which is provided by the present application, and as can be seen from fig. 10, an orthographic projection of one end of the spacer 80, which is close to the spacer bolster 81, on the plane of the first substrate 10 is overlapped with an orthographic projection of two protrusions 90 and 90 ' of the spacer bolster 81 on the plane of the first substrate 10, respectively, to form a first overlapped region 82 and a second overlapped region 83, so that when the display panel 100 is pressed to make the spacer 80 contact with the spacer bolster 81, the spacer 80 will simultaneously contact with the two protrusions 90 and 90 ' of the spacer bolster 81, and the two protrusions 90 and 90 ' simultaneously support the spacer 80, thereby eliminating a step difference effect and effectively avoiding a phenomenon that the spacer 80 slides when the display panel 100 is pressed.

Alternatively, in fig. 10, the area of the first overlap region 82 is equal to the area of the second overlap region 83.

Specifically, this application forms the area design of overlap region for equal between the spacer 80 and two bellying 90 in the spacer bolster 81 respectively with 90 ', when display panel 100 pressurized makes two bellying 90 and 90' contacts in spacer 80 and the spacer bolster 81, the atress area of spacer 80 on two bellyings 90 and 90 'equals, this just makes two bellyings 90 and 90' more unanimous to the size of the holding power that the spacer 80 was applyed respectively, avoid the uneven phenomenon of atress to appear in the maximum spacer 80, consequently be favorable to blockking spacer 80 more and take place to slide because the atress is uneven.

Optionally, referring to fig. 11, fig. 11 is a cross-sectional view of a display panel 100 provided in the present application, in which the first substrate 10 further includes a thin film transistor array layer 40, the thin film transistor array layer 40, an electrode layer 50, and a first alignment film layer 60 are sequentially disposed on a surface of the first substrate 10 facing the second substrate 20; the thin film transistor array layer 40 includes a semiconductor active layer including a source region, a drain region, and a channel region between the source region and the drain region; the orthographic projection of the groove 91 on the plane of the first substrate 10 overlaps with the orthographic projection of the channel region on the plane of the first substrate 10.

Specifically, as can be seen from fig. 11, a thin film transistor array layer 40, an electrode layer 50 and a first alignment film layer 60 are sequentially disposed on a first substrate 11 of a first substrate 10, a semiconductor active layer 25 in the thin film transistor array layer 40 includes a channel region and a source region and a drain region respectively located at two sides of the channel region, a spacer stud pad 81 is disposed directly above the thin film transistor array layer 40, and an orthographic projection of a groove 91 in the spacer stud pad 81 on a plane where the first substrate 10 is located and an orthographic projection of the channel region in the thin film transistor array layer 40 on a plane where the first substrate 10 is located overlap. In the actual production process, after the thin film transistor array layer 40 is manufactured, the position of the groove 91 in the spacer stud pad 81 can be determined according to the position of the channel region, and then the position of the whole spacer stud pad 81 is determined, so that the orthographic projection of the groove 91 on the plane of the first substrate 10 is overlapped with the orthographic projection of the channel region on the plane of the first substrate 10, and the reference positioning effect can be achieved for the manufacturing of the spacer stud pad 81 region.

Alternatively, referring to fig. 11, the thin film transistor array layer 40, the electrode layer 50 and the first alignment film layer 60 in the present application are located on the surface of the first substrate 10 facing the second substrate 20; the thin film transistor array layer 40 further includes a gate metal layer and a source drain metal layer, the gate metal layer is located on one side of the semiconductor active layer close to the first substrate 10, or the gate metal layer is located on one side of the semiconductor active layer far from the first substrate 10.

Specifically, in the embodiment shown in fig. 11, the thin film transistor array layer 40, the electrode layer 50 and the first alignment film layer 60 are disposed on the surface of the first substrate 10 facing the second substrate 20, so that the thin film transistor array layer 40, the electrode layer 50 and the first alignment film layer 60 can control the liquid crystal between the first substrate 10 and the second substrate 20, and thus can control the display of the second substrate 20. In addition, each thin film transistor in the thin film transistor array layer 40 in the present application may be configured in a top gate structure and may also be designed in a bottom gate structure. The thin film transistor array layer 40 includes the gate metal layer 21 and the source metal layers 27 and 28, and when the gate metal layer 21 is disposed on the side of the semiconductor active layer close to the first substrate 10, it is embodied as a bottom gate structure, and when the gate of the thin film transistor adopts such a structure as shown in fig. 11, high stability of sealing and high flexibility of manufacturing processes can be achieved; when the gate metal layer 21 is disposed on the side of the semiconductor active layer 25 away from the first substrate 10, the top gate structure is shown, referring to fig. 12, and fig. 12 is a cross-sectional view of the display panel 100 provided in the present application, the gate of the thin film transistor is easier to design and has a longer service life when the top gate structure is adopted.

Optionally, an orthographic projection of the groove 91 on the plane of the first substrate 10 is one or more of a square, a circle, an ellipse, a diamond or a cross.

Specifically, referring to fig. 10, in the embodiment shown in fig. 10, an orthographic projection of the groove 91 on the plane of the first substrate 10 is a square, except for this implementation, the orthographic projection of the groove 91 on the plane of the first substrate 10 may be designed as a combination of one or more of a square, a circle, an ellipse, a diamond, or a cross, which is not specifically limited in this application, as long as the two protruding portions 90 and 90' on two sides of the groove 91 can simultaneously support the spacer 80 when the display panel 100 is pressed.

Optionally, the orthogonal projection of one end of the spacer 80 close to the spacer bolster 81 on the plane of the first substrate 10 is a regular hexagon, a circle, an ellipse or a square.

Specifically, referring to fig. 10, in the embodiment shown in fig. 10, an orthogonal projection of one end of the spacer 80 close to the spacer bolster 81 on the plane of the first substrate 10 is a regular hexagon, the spacer 80 spans the groove 91, and the orthogonal projections of two sides of the spacer 80 and the two protrusions form a first overlapping area 82 and a second overlapping area 83, respectively. When the orthogonal projection of the spacer 80 near the end of the spacer bolster 81 is implemented by symmetrical shapes such as regular hexagon, circle, ellipse or square, the same area of the first overlapping region 82 and the second overlapping region 83 is facilitated, so that when the display panel 100 is pressed, the supporting force of the two protrusions 90 and 90' on the spacer 80 is more consistent, and the spacer 80 is more facilitated to slide due to uneven stress when the display panel 100 is pressed.

Optionally, the second substrate 20 includes a pixel region layer 72 and a second alignment film layer 73, the pixel region layer 72 and the second alignment film layer 73 are sequentially disposed on a surface of the second substrate 20 facing the first substrate 10, and an end of the spacer 80 away from the spacer pillow 81 is fixed on the second substrate 20.

Specifically, as can be seen from fig. 6, the second substrate 20 includes a pixel region layer 72 and a second alignment film layer 73, which are sequentially disposed, and a spacer 80 located between the first substrate 10 and the second substrate 20 is fixed on the second substrate 20, that is, one end of the spacer 80 away from the first substrate 10 is fixed on the second substrate 20. It should be noted that the pixel region includes a plurality of sub-pixel units (not shown in the figure), and the sub-pixel units may include a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit, and in other embodiments, the pixel region further includes a white sub-pixel unit, and the kind of the sub-pixel unit is not limited herein. When the display panel needs to display different colors, the sub-pixel units emit light with different brightness respectively, and because the size of the sub-pixel units is very small, the sub-pixel units are visually mixed into the required color, so that the second substrate 20 performs different image display according to the control of the thin film transistor on the first substrate 10.

Based on the same inventive concept, the present application further provides a display device, and fig. 13 is a schematic structural diagram of the display device provided in the present application, where the display device 200 includes a display panel 100, and the display panel 100 is the display panel 100 provided in the present application. The display device 200 provided by the present application may be: any product or component with practical functions such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. In the present application, the embodiment of the display device 200 can refer to the embodiment of the display panel 100, and repeated descriptions are omitted here.

According to the embodiments, the application has the following beneficial effects:

in the display panel and the display device provided by the application, the spacer bolster corresponding to the spacer comprises two convex parts, the heights of the two convex parts along the direction vertical to the plane of the first substrate are the same, when the display panel is pressed to enable the spacing column to be in contact with the spacing column bolster, the spacing column can be in contact with the two convex parts in the spacing column bolster at the same time, because the heights of the two convex parts in the spacer bolster are the same, compared with the prior art, the spacer bolster has the advantages that the influence of the section difference of the spacer bolster is eliminated, the spacer post can not deviate after contacting with the two convex parts, the phenomenon that the spacer post slides when contacting with the spacer bolster when the display panel is stressed is effectively avoided, meanwhile, the phenomenon that the first alignment film is damaged due to sliding of the spacer columns is avoided, and compared with the prior art, the phenomenon that the display panel is poor in light leakage and broken bright spots due to the fact that the alignment film in the spacer column bolster areas is damaged and falls off is fundamentally avoided. In addition, the first electrode layer, the first insulating layer, the second electrode layer and the first alignment film layer are sequentially arranged on the first substrate in the application, the spacer is formed in the spacer bolster on the basis that the first substrate has a structure, the two protruding portions respectively comprise the first electrode layer, the first insulating layer, at least one layer of backing layer and the first alignment film layer which are sequentially arranged, the groove between the two protruding portions comprises the first insulating layer and the first alignment film layer which are sequentially arranged, and the backing layer and the second electrode layer are arranged on the same layer.

The foregoing description shows and describes several preferred embodiments of the present application, but as aforementioned, it is to be understood that the application is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the application, which is to be protected by the claims appended hereto.

Claims

1. A display panel is characterized by comprising a first substrate, a second substrate and a plurality of spacing columns arranged between the first substrate and the second substrate;

a spacer column bolster corresponding to the spacer column is further arranged between the first substrate and the second substrate and comprises two protruding parts with the same height and a groove positioned between the two protruding parts, wherein the height is a distance in a direction perpendicular to a plane where the first substrate is located; the width of one end, close to the spacer bolster, of the spacer is larger than that of the groove, the orthographic projection of one end, close to the spacer bolster, of the spacer on the plane where the first substrate is located is overlapped with the orthographic projection of the two protrusions on the plane where the first substrate is located respectively, and a first overlapped area and a second overlapped area are formed;

2. The display panel according to claim 1, characterized in that: the backing layer has a thickness D1,

3. the display panel according to claim 1, characterized in that: the first electrode layer is a common electrode layer, and the second electrode layer is a pixel electrode layer.

4. The display panel according to claim 1, characterized in that: the area of the first overlap region is equal to the area of the second overlap region.

5. The display panel according to claim 1, characterized in that: the first substrate further comprises a thin film transistor array layer, and the thin film transistor array layer, the electrode layer and the first alignment film layer are sequentially arranged on the surface of one side, facing the second substrate, of the first substrate;

6. The display panel according to claim 5, wherein: the thin film transistor array layer, the electrode layer and the first alignment film layer are positioned on the surface of one side, facing the second substrate, of the first substrate;

7. The display panel according to claim 1, characterized in that: the orthographic projection of the groove on the plane where the first substrate is located is one or a combination of a plurality of square shapes, circular shapes, oval shapes, rhombic shapes or cross shapes.

8. The display panel according to claim 1, characterized in that: the orthogonal projection of one end of the spacer close to the spacer bolster on the plane where the first substrate is located is regular hexagon, circle, ellipse or square.

9. The display panel according to claim 1, wherein the second substrate comprises a pixel region layer and a second alignment film layer, the pixel region layer and the second alignment film layer are sequentially disposed on a surface of the second substrate facing the first substrate, and an end of the spacer pillar away from the spacer pillar bolster is fixed on the second substrate.

10. A display device comprising a display panel, wherein the display panel is the display panel according to any one of claims 1 to 9.