CN107209735B - 可配置管芯、层叠封装装置以及方法 - Google Patents

可配置管芯、层叠封装装置以及方法 Download PDF

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Publication number
CN107209735B
CN107209735B CN201680005707.9A CN201680005707A CN107209735B CN 107209735 B CN107209735 B CN 107209735B CN 201680005707 A CN201680005707 A CN 201680005707A CN 107209735 B CN107209735 B CN 107209735B
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China
Prior art keywords
phy
memory
generic
signal
signals
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Expired - Fee Related
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CN201680005707.9A
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English (en)
Chinese (zh)
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CN107209735A (zh
Inventor
K·M·德赛
P·库普塔
B·J·杨
U·M·劳
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
CN201680005707.9A 2015-01-16 2016-01-07 可配置管芯、层叠封装装置以及方法 Expired - Fee Related CN107209735B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/598,528 2015-01-16
US14/598,528 US9324397B1 (en) 2015-01-16 2015-01-16 Common die for supporting different external memory types with minimal packaging complexity
PCT/US2016/012511 WO2016114975A1 (en) 2015-01-16 2016-01-07 A common die for supporting different external memory types with minimal packaging complexity

Publications (2)

Publication Number Publication Date
CN107209735A CN107209735A (zh) 2017-09-26
CN107209735B true CN107209735B (zh) 2020-07-03

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CN201680005707.9A Expired - Fee Related CN107209735B (zh) 2015-01-16 2016-01-07 可配置管芯、层叠封装装置以及方法

Country Status (5)

Country Link
US (1) US9324397B1 (enExample)
EP (1) EP3245594A1 (enExample)
JP (1) JP6710689B2 (enExample)
CN (1) CN107209735B (enExample)
WO (1) WO2016114975A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6543129B2 (ja) 2015-07-29 2019-07-10 ルネサスエレクトロニクス株式会社 電子装置
WO2020117700A1 (en) 2018-12-03 2020-06-11 Rambus Inc. Dram interface mode with improved channel integrity and efficiency at high signaling rates
US10671551B1 (en) * 2019-02-20 2020-06-02 Intel Corporation Selective data lane interface mapping
US11288222B1 (en) 2020-09-28 2022-03-29 Xilinx, Inc. Multi-die integrated circuit with data processing engine array

Citations (3)

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CN101702947A (zh) * 2007-04-12 2010-05-05 拉姆伯斯公司 具有点对点请求互连的存储器系统
CN102576338A (zh) * 2010-01-28 2012-07-11 惠普发展公司，有限责任合伙企业 用于存储器设备的接口方法和装置
CN102929828A (zh) * 2012-10-18 2013-02-13 广东欧珀移动通信有限公司 同时支持标准和非标准i2c接口的数据传输方法及装置

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US6460120B1 (en) * 1999-08-27 2002-10-01 International Business Machines Corporation Network processor, memory organization and methods
US8356138B1 (en) * 2007-08-20 2013-01-15 Xilinx, Inc. Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP)
US20130194881A1 (en) * 2010-11-09 2013-08-01 Steven C. Woo Area-efficient multi-modal signaling interface
US20120185663A1 (en) 2011-01-14 2012-07-19 Satoshi Yokoya Memory Interface Converter
US8446903B1 (en) 2012-05-22 2013-05-21 Intel Corporation Providing a load/store communication protocol with a low power physical unit
US8972640B2 (en) 2012-06-27 2015-03-03 Intel Corporation Controlling a physical link of a first protocol using an extended capability structure of a second protocol
KR102004849B1 (ko) 2012-08-02 2019-07-29 삼성전자 주식회사 동적 메모리 재할당 관리 방법과 상기 방법을 수행할 수 있는 장치
US8680900B2 (en) * 2012-08-10 2014-03-25 Arm Limited Self-initializing on-chip data processing apparatus and method of self-initializing an on-chip data processing apparatus
WO2014133527A1 (en) 2013-02-28 2014-09-04 Intel Corporation Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different interconnect protocol
KR102029682B1 (ko) * 2013-03-15 2019-10-08 삼성전자주식회사 반도체 장치 및 반도체 패키지
US9123408B2 (en) * 2013-05-24 2015-09-01 Qualcomm Incorporated Low latency synchronization scheme for mesochronous DDR system
US9430434B2 (en) * 2013-09-20 2016-08-30 Qualcomm Incorporated System and method for conserving memory power using dynamic memory I/O resizing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101702947A (zh) * 2007-04-12 2010-05-05 拉姆伯斯公司 具有点对点请求互连的存储器系统
CN102576338A (zh) * 2010-01-28 2012-07-11 惠普发展公司，有限责任合伙企业 用于存储器设备的接口方法和装置
CN102929828A (zh) * 2012-10-18 2013-02-13 广东欧珀移动通信有限公司 同时支持标准和非标准i2c接口的数据传输方法及装置

Also Published As

Publication number Publication date
WO2016114975A1 (en) 2016-07-21
US9324397B1 (en) 2016-04-26
CN107209735A (zh) 2017-09-26
EP3245594A1 (en) 2017-11-22
JP2018508871A (ja) 2018-03-29
JP6710689B2 (ja) 2020-06-17

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