CN107204344A - TFT array substrate structure - Google Patents
TFT array substrate structure Download PDFInfo
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- CN107204344A CN107204344A CN201710370162.8A CN201710370162A CN107204344A CN 107204344 A CN107204344 A CN 107204344A CN 201710370162 A CN201710370162 A CN 201710370162A CN 107204344 A CN107204344 A CN 107204344A
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- array substrate
- drain electrode
- tft
- tft array
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- 239000000758 substrate Substances 0.000 title claims abstract description 36
- 238000002161 passivation Methods 0.000 claims abstract description 32
- 238000009413 insulation Methods 0.000 claims abstract description 28
- 239000012212 insulator Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 2
- 239000010408 film Substances 0.000 description 11
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 208000010392 Bone Fractures Diseases 0.000 description 5
- 206010017076 Fracture Diseases 0.000 description 5
- 229910004205 SiNX Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229910018503 SF6 Inorganic materials 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- WRQGPGZATPOHHX-UHFFFAOYSA-N ethyl 2-oxohexanoate Chemical compound CCCCC(=O)C(=O)OCC WRQGPGZATPOHHX-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- GRPQBOKWXNIQMF-UHFFFAOYSA-N indium(3+) oxygen(2-) tin(4+) Chemical group [Sn+4].[O-2].[In+3] GRPQBOKWXNIQMF-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of tft array substrate structure, first through hole (V1) is set in passivation insulation (8), the second through hole (V2) is set in passivation insulation (8) and gate insulator (3), and the first through hole (V1) and the second through hole (V2) laterally spaced setting, in the first through hole (V1), in second through hole (V2), and deposited between first through hole (V1) and the second through hole (V2) for being connected the 3rd drain electrode (D3) and the conductive film (9) of public pressure wire (Com), rounding problem can be avoided, take precautions against the risk that fracture and loose contact occur for conductive film, make the connection between electric discharge TFT and public pressure wire reliable, lift the yield and its reliability of tft array substrate.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of tft array substrate structure.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT-
LCD high definition, continuous, fine and smooth picture) can be shown, it is more and more popular with consumers.
TFT-LCD on existing market generally includes housing, the liquid crystal panel in housing and the back of the body in housing
Optical mode group.Liquid crystal panel is by a colored filter (Color Filter, CF) substrate, a thin-film transistor array base-plate (Thin
Film Transistor Array Substrate, TFT Array Substrate) and one it is configured at liquid between two substrates
Crystal layer (Liquid Crystal Layer) is constituted, and its operation principle is by applying driving voltage on two panels glass substrate
Come the rotation of the liquid crystal molecule that controls liquid crystal layer, the light of backlight module is reflected into generation picture.
TFT-LCD will show continuous, fine and smooth high-resolution picture, it is necessary to do bright dark continuity change between pixel (Pixel).
The luminance difference that the pixel of two consecutive variations can be formed by different switch time difference is realized, but this method is driven
Dynamic design is difficult to；Another method can cause upper/lower electrode by being filled with different electricity in same time to pixel
Or pressure difference is inconsistent between driving electrodes, so that liquid crystal deflection angle is inconsistent, light transmission rate is inconsistent, reaches bright dark continuous change
The requirement of change.Prior art generally realizes filling within identical charging interval different pixels by dragging down the current potential of different pixels
The effect that electric saturation degree is different, charging charge is different, current potential is inconsistent.
As shown in figure 1, being widely used in filling for control single pixel using the design method of 3 TFT as driver elements
Electric saturation degree, wherein gate lines G are used to open the first charging TFT T1, the second charging TFT T2 and electric discharge TFT T3, and first fills
Electric TFT T1 two phases corresponding with the data-signal write-in that second charging TFT T2 the two TFT mainly transmit data wire D
Adjacent pixel is charged, and electric discharge TFT T3 are directly electrically connected with the second charging TFT T2 drain electrode and the relatively low common electric voltage of current potential
Line Com, the electric charge with the second charging TFT T2 pixels being electrically connected with is exported to drag down the current potential of the pixel.So design
Advantage is：The current potential of one of two adjacent pixels can be effectively dragged down on the premise of aperture opening ratio is not sacrificed.
Please refer to Fig. 2 and Fig. 3, with reference to Fig. 1, in order to realize electric discharge TFT T3 drain D 3 and public pressure wire Com
Between connection, existing tft array substrate will pass through electric discharge TFT T3 drain D 3 and its lower semiconductor active layer 400
Through hole V1 ' and through the semiconductor active layer 400 and public pressure wire Com of the lower section of drain D 3 located at electric discharge TFT T3 it
Between gate insulator 200 public via V2 ' designs it is integral, pass through the deposition conduction in through hole V1 ' and public via V2 '
Film such as tin indium oxide (Indium Tin Oxide, ITO) connects electric discharge TFT T3 drain D 3 and public pressure wire Com.
This existing tft array substrate uses chemical etching and physics when making the integral through hole V1 ' and public via V2 '
The dry etching having concurrently is etched, semiconductor active layer 400 and gate insulator 200 positioned at the electric discharge TFT T3 lower section of drain D 3
In dry etching gas sulfur hexafluoride (SF6) in the presence of occur chemical reaction and form gaseous volatilization, and due to semiconductor active
Layer 400 (material composition is non-crystalline silicon (a-Si) and the non-crystalline silicon (N+a-Si) Jing Guo N-type heavy doping) and gate insulator 200
The material composition of (material composition is silicon nitride (SiNx)) is different, with SF6Etching reaction speed it is different, add electric discharge TFT T3
The metal section of drain D 3 it is exposed by through hole V1 ' and public via V2 ' with the section of semiconductor active layer 400, cause in TFT
T3 drain D 3 and the interface of semiconductor active layer 400 and the interface of semiconductor active layer 400 and gate insulator 200
Chamfering (Undercut) problem (being irised out with dotted ellipse) as shown in Figure 3 is formed, ITO climbings is easily caused and occurs fracture and connect
Bad risk is touched, the yield and its reliability of tft array substrate is influenceed.
The content of the invention
It is an object of the invention to provide a kind of tft array substrate structure, rounding problem can be avoided, conductive film is taken precautions against
Occur the risk of fracture and loose contact, make the connection between electric discharge TFT and public pressure wire reliable, lift tft array substrate
Yield and its reliability.
To achieve the above object, the present invention provides a kind of tft array substrate structure, including is cascading from bottom to top
The first metal layer, gate insulator, semiconductor active layer, second metal layer and passivation insulation；
The tft array substrate structure has multiple pixel regions arranged in array, in two longitudinally adjacent pixels
In region, the first metal layer includes public pressure wire and the gate line extended transversely, and the second metal layer includes edge
The data wire of Longitudinal extending, the first source electrode being connected with the data wire, the second source electrode being connected with the data wire, with it is described
The second drain electrode and the described second drain electrode that the first drain electrode and second source electrode that first source electrode is oppositely arranged are oppositely arranged connect
The 3rd source electrode connect and the 3rd drain electrode being oppositely arranged with the 3rd source electrode；The passivation insulation covering second metal layer,
Semiconductor active layer and gate insulator；
The passivation insulation is provided with the first through hole through the passivation insulation, and the first through hole exposes the 3rd
The part surface of drain electrode；The passivation insulation and gate insulator are provided with through the passivation insulation and gate insulator
Second through hole, second through hole exposes the part surface of public pressure wire；The first through hole and the second through hole are transversely
It is arranged at intervals；There is for connecting the 3rd deposition in the first through hole, in the second through hole and between first through hole and the second through hole
Drain electrode and the conductive film of public pressure wire.
The gate line, the first source electrode, with first drain electrode formed first charge TFT, the gate line, the second source electrode, with
Second drain electrode forms the second charging TFT, and the gate line, the 3rd source electrode and the 3rd drain electrode form electric discharge TFT；
First drain electrode, one pixel electrode of connection, another pixel electrode of the second drain electrode connection.
The opening shape of the first through hole and the second through hole is rectangular or circle.
The opening size of the first through hole is more than 5um.
The opening size of second through hole is more than 5um.
The distance that the first through hole is located at the border between first through hole and the second through hole away from the 3rd drain electrode is more than 4um.
The distance that second through hole is located at the border between first through hole and the second through hole away from the 3rd drain electrode is more than 4um.
The gate insulator and the material of passivation insulation are silicon nitride；The material of the conductive film is indium oxide
Tin.
Beneficial effects of the present invention：A kind of tft array substrate structure that the present invention is provided, sets in passivation insulation
One through hole, sets the second through hole in passivation insulation and gate insulator, and the first through hole and the second through hole are transversely
It is arranged at intervals, is deposited in the first through hole, in the second through hole and between first through hole and the second through hole for connecting the 3rd
Drain electrode and the conductive film of public pressure wire；Because the metal section of the 3rd drain electrode and the section of semiconductor active layer are passivated
Insulating barrier is covered, under the protective effect of passivation insulation, the 3rd drain electrode and semiconductor active layer interface and semiconductor active
The interface of layer and gate insulator is not in chamfering, so as to take precautions against the wind that fracture and loose contact occur for conductive film
Danger, makes the connection between electric discharge TFT and public pressure wire reliable, lifts the yield and its reliability of tft array substrate.
Brief description of the drawings
In order to be able to be further understood that the feature and technology contents of the present invention, refer to below in connection with the detailed of the present invention
Illustrate and accompanying drawing, however accompanying drawing only provide with reference to and explanation use, not for being any limitation as to the present invention.
In accompanying drawing,
Fig. 1 is the existing circuit structure diagram using 3 TFT as driver element；
Fig. 2 is the front view of existing tft array substrate structure；
Fig. 3 is corresponding to the sectional view at A-A in Fig. 2；
Fig. 4 is the front view of the tft array substrate structure of the present invention；
Fig. 5 is corresponding to the sectional view at B-B in Fig. 4.
Embodiment
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with being preferable to carry out for the present invention
Example and its accompanying drawing are described in detail.
Please refer to Fig. 4 and Fig. 5, the present invention provides a kind of tft array substrate structure, including stacks gradually from bottom to top
The first metal layer, gate insulator 3, semiconductor active layer 5, second metal layer and the passivation insulation 8 of setting.
The tft array substrate structure has multiple pixel regions arranged in array, in two longitudinally adjacent pixels
In region, the first metal layer includes public pressure wire Com and the gate lines G extended transversely, the second metal layer bag
Include the data wire D extended longitudinally, the first source S 1 being connected with the data wire D, the second source being connected with the data wire D
Pole S2, the first drain D 1 being oppositely arranged with first source S 1, the second drain electrode being oppositely arranged with second source S 2
D2, the 3rd source S 3 being connected with second drain D 2 and the 3rd drain electrode D3 being oppositely arranged with the 3rd source S 3；Institute
State the covering of passivation insulation 8 second metal layer, semiconductor active layer 5 and gate insulator 3.The semiconductor active layer 5 is each
Individual source electrode is covered with drain electrode, and the first source S 1 is attached with the first drain D 1, to the second source S 2 and the second drain D 2
It is attached, the 3rd source S 3 is attached with the 3rd drain electrode D3.
The gate lines G, the first source S 1, charge TFT T1, the gate lines G, the with the first drain D 1 formation first
Two source Ss 2 and the second drain D 2 formation the second charging TFT T2, the gate lines G, the 3rd source S 3 and the 3rd drain electrode D3 shapes
Into electric discharge TFT T3.First drain D 1 connects a pixel electrode P1, and second drain D 2 connects another pixel electrode P2.
Specifically, the material of the gate insulator 3 and passivation insulation 8 is SiNx.
Unlike the prior art, in the tft array substrate structure of the present invention, the passivation insulation 8, which is provided with, to be run through
The first through hole V1, the first through hole V1 of the passivation insulation 8 expose the 3rd drain electrode D3 part surface；The passivation is exhausted
Edge layer 8 is provided with the second through hole V2 through the passivation insulation 8 with gate insulator 3 with gate insulator 3, and described second leads to
Hole V2 exposes public pressure wire Com part surface；The first through hole V1 and the second through hole V2 is laterally spaced to be set；Institute
State in first through hole V1, there be for connecting three leakages deposition in the second through hole V2 and between first through hole V1 and the second through hole V2
Pole D3 and public pressure wire Com conductive film 9.
As shown in figure 5, the 3rd drain electrode D3 metal section and the section of semiconductor active layer 5 are passivated insulating barrier 8 and covered
Lid, due to the protective effect of passivation insulation 8, it is to avoid the 3rd drain electrode D3 has with the interface of semiconductor active layer 5 and semiconductor
There is chamfering in the interface of active layer 5 and gate insulator 3, and is only needed to using SiNx as material when making the first through hole V1
Passivation insulation 8 perform etching, only needed when making the second through hole V2 to passivation insulation 8 and same using SiNx as material
The gate insulator 3 of material is performed etching, and dry etching gas and SiNx reaction rate is uniform, from prepared by first through hole V1
Profile with the second through hole V2 is shallower, can take precautions against the risk that fracture and loose contact occur for conductive film 9, make electric discharge TFT
Connection between T3 and public pressure wire Com is reliable, lifts the yield and its reliability of tft array substrate.
Specifically, the material of the conductive film 9 is ITO.
With reference to Fig. 1, the gate lines G is used to open the first charging TFT T1, the second charging TFT T2 and electric discharge TFT
T3, the first charging TFT T1 are corresponding with the second data-signal write-in that TFT T2 the two TFT mainly transmit data wire D of charging
Two adjacent pixels charged, electric discharge TFT T3 source S 3, drain D 3 are electrically connected the second charging TFT T2's
Drain D 2, with the relatively low public pressure wire Com of current potential, by the electric charge with the second charging TFT T2 pixels being electrically connected with export with
Drag down the current potential of the pixel so that the current potential of two adjacent pixels is different.
Further, the first through hole V1 and the second through hole V2 opening shape is rectangular or circle.Described first
Through hole V1 opening size a1 is more than 5um；The opening size a2 of the second through hole V2 is more than 5um.
In order to ensure that there is enough horizontal spacings between the second through hole V2 and the first logical V1, stop to TFT
The semiconductor active layer 5 of the T3 lower section of drain D 3 is performed etching, and preferably described first through hole V1 is located at first away from the 3rd drain electrode D3
Border between through hole V1 and the second through hole V2 apart from b1 is more than 4um；The second through hole V2 is located at the away from the 3rd drain electrode D3
Border between one through hole V1 and the second through hole V2 apart from b2 is more than 4um.
In summary, tft array substrate structure of the invention, sets first through hole in passivation insulation, exhausted in passivation
Edge layer is with setting the second through hole, and the first through hole and the laterally spaced setting of the second through hole on gate insulator, described
Deposited in first through hole, in the second through hole and between first through hole and the second through hole for connecting the 3rd drain electrode and common electric voltage
The conductive film of line；Because the metal section of the 3rd drain electrode and the section of semiconductor active layer are passivated insulating barrier covering,
Under the protective effect of passivation insulation, the 3rd drain electrode and semiconductor active layer interface and semiconductor active layer and gate insulator
Interface be not in chamfering, so as to take precautions against conductive film occur fracture and loose contact risk, make electric discharge TFT with
Connection between public pressure wire is reliable, lifts the yield and its reliability of tft array substrate.
It is described above, for the person of ordinary skill of the art, can be with technique according to the invention scheme and technology
Other various corresponding changes and deformation are made in design, and all these changes and deformation should all belong to appended right of the invention
It is required that protection domain.
Claims (8)
1. a kind of tft array substrate structure, it is characterised in that including the first metal layer, the grid being cascading from bottom to top
Pole insulating barrier (3), semiconductor active layer (5), second metal layer and passivation insulation (8)；
The tft array substrate structure has multiple pixel regions arranged in array, in two longitudinally adjacent pixel regions
Interior, the first metal layer includes public pressure wire (Com) and the gate line (G) extended transversely, the second metal layer bag
Include the data wire (D) extended longitudinally, the first source electrode (S1) being connected with the data wire (D), be connected with the data wire (D)
The second source electrode (S2), with first source electrode (S1) be oppositely arranged first drain electrode (D1), with the second source electrode (S2) phase
Drained to the second of setting the drain electrode (D2), with described second the 3rd source electrode (S3) that (D2) be connected and with the 3rd source electrode
(S3) the 3rd drain electrode (D3) being oppositely arranged；The passivation insulation (8) covering second metal layer, semiconductor active layer (5), with
Gate insulator (3)；
The passivation insulation (8) is provided with the first through hole (V1) through the passivation insulation (8), the first through hole (V1)
Expose the part surface of the 3rd drain electrode (D3)；The passivation insulation (8) is provided with gate insulator (3) runs through the passivation
The second through hole (V2) of insulating barrier (8) and gate insulator (3), second through hole (V2) exposes public pressure wire (Com)
Part surface；The first through hole (V1) and the second through hole (V2) laterally spaced setting；In the first through hole (V1), the
In two through holes (V2) and between first through hole (V1) and the second through hole (V2) deposition have for be connected the 3rd drain (D3) with it is public
The conductive film (9) of pressure-wire (Com).
2. tft array substrate structure as claimed in claim 1, it is characterised in that the gate line (G), the first source electrode (S1),
With first the first charging TFT (T1) of drain electrode (D1) formation, the gate line (G), the second source electrode (S2) and second drain electrode (D2) shape
Into the second charging TFT (T2), the gate line (G), the 3rd source electrode (S3) and the 3rd drain electrode (D3) formation electric discharge TFT (T3)；
First drain electrode (D1) connects a pixel electrode (P1), and second drain electrode (D2) connects another pixel electrode (P2).
3. tft array substrate structure as claimed in claim 1, it is characterised in that the first through hole (V1) and the second through hole
(V2) opening shape is rectangular or circle.
4. tft array substrate structure as claimed in claim 3, it is characterised in that the opening size of the first through hole (V1)
(a1) it is more than 5um.
5. tft array substrate structure as claimed in claim 3, it is characterised in that the opening size of second through hole (V2)
(a2) it is more than 5um.
6. tft array substrate structure as claimed in claim 3, it is characterised in that the first through hole (V1) is away from the 3rd drain electrode
(D3) distance (b1) for being located at the border between first through hole (V1) and the second through hole (V2) is more than 4um.
7. tft array substrate structure as claimed in claim 3, it is characterised in that second through hole (V2) is away from the 3rd drain electrode
(D3) distance (b2) for being located at the border between first through hole (V1) and the second through hole (V2) is more than 4um.
8. tft array substrate structure as claimed in claim 1, it is characterised in that the gate insulator (3) is insulated with passivation
The material of layer (8) is silicon nitride；The material of the conductive film (9) is tin indium oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710370162.8A CN107204344B (en) | 2017-05-23 | 2017-05-23 | TFT array substrate structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710370162.8A CN107204344B (en) | 2017-05-23 | 2017-05-23 | TFT array substrate structure |
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| CN107204344A true CN107204344A (en) | 2017-09-26 |
| CN107204344B CN107204344B (en) | 2020-05-29 |
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ID=59905208
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| CN201710370162.8A Active CN107204344B (en) | 2017-05-23 | 2017-05-23 | TFT array substrate structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109298574A (en) * | 2018-11-20 | 2019-02-01 | 深圳市华星光电技术有限公司 | A kind of array substrate and display panel |
| WO2021120311A1 (en) * | 2019-12-17 | 2021-06-24 | Tcl华星光电技术有限公司 | Array substrate, display panel, and manufacturing method for array substrate |
Citations (5)
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|---|---|---|---|---|
| US20020081761A1 (en) * | 2000-12-27 | 2002-06-27 | Chien-Chih Chen | Method of manufacturing a display unit of a flat display panel having a wide viewing angle |
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| CN105957867A (en) * | 2016-04-28 | 2016-09-21 | 京东方科技集团股份有限公司 | Array substrate mother board, manufacture method and display device thereof |
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| WO2021120311A1 (en) * | 2019-12-17 | 2021-06-24 | Tcl华星光电技术有限公司 | Array substrate, display panel, and manufacturing method for array substrate |
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| CN107204344B (en) | 2020-05-29 |
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