CN107104077B - The production method of tft array substrate - Google Patents

The production method of tft array substrate Download PDF

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Publication number
CN107104077B
CN107104077B CN201710245925.6A CN201710245925A CN107104077B CN 107104077 B CN107104077 B CN 107104077B CN 201710245925 A CN201710245925 A CN 201710245925A CN 107104077 B CN107104077 B CN 107104077B
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China
Prior art keywords
tft
drain electrode
metal layer
layer
t3
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CN201710245925.6A
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Chinese (zh)
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CN107104077A (en
Inventor
王勐
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深圳市华星光电半导体显示技术有限公司
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Priority to CN201710245925.6A priority Critical patent/CN107104077B/en
Publication of CN107104077A publication Critical patent/CN107104077A/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

The present invention provides a kind of production method of tft array substrate, it is exposed with intermediate tone mask plate (3) for tool, so that the drain electrode (D3) of electric discharge TFT (T3) and its top at climbing retain the photoresist (PR) of thin layer in second metal layer (M2), the photoresist (PR) for the thin layer being retained in subsequent dry etch process protects gate insulating layer (GI) below at the climbing for the drain electrode (D3) for being located at electric discharge TFT (T3), avoid gate insulating layer (GI) at the climbing of the drain electrode (D3) of electric discharge TFT (T3) because overetch and undercutting problem occur for material difference, reduce the risk of conductive film (9) rupture of membranes, so that the bridge joint between the drain electrode (D3) and public pressure wire (Com) of electric discharge TFT (T3) is reliable, and it will not damage Aperture opening ratio is lost, so as to improve the display effect of panel, improves product yield.

Description

The production method of tft array substrate

Technical field

The present invention relates to field of display technology more particularly to a kind of production methods of tft array substrate.

Background technique

Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT- LCD high definition, continuous, fine and smooth picture) can be shown, it is more and more popular with consumers.

TFT-LCD on existing market generally includes shell, the liquid crystal display panel being set in the housing and the back being set in the housing Optical mode group.Liquid crystal display panel is by a colored filter (Color Filter, CF) substrate, a thin-film transistor array base-plate (Thin Film Transistor Array Substrate, TFT Array Substrate) and one it is configured at liquid between two substrates Crystal layer (Liquid Crystal Layer) is constituted, its working principle is that by applying driving voltage on two panels glass substrate Come control liquid crystal layer liquid crystal molecule rotation, by the light refraction of backlight module come out generate picture.

TFT-LCD will show continuous, fine and smooth high-resolution picture, need to do bright dark continuity variation between pixel (Pixel). The pixel of two consecutive variations can be by being filled with different electricity in the same time to pixel come so that upper/lower electrode or driving Pressure difference is inconsistent between electrode, to keep liquid crystal deflection angle inconsistent, light transmission rate is inconsistent, reaches wanting for bright dark consecutive variations It asks.The prior art usually realizes the charging saturation of the different pixels within the identical charging time by dragging down the current potential of different pixels The effect that degree is different, charging charge is different, current potential is inconsistent.

As shown in Figure 1, being widely used in filling for control single pixel by the design method of driving unit of 3 TFT Electric saturation degree, wherein the gate lines G in the first metal layer for open first charging TFT T1, second charging TFT T2, with put Electric TFT T3, the first charging TFT T1 and second charging the two TFT of TFT T2 mainly pass the data line D in second metal layer Defeated data-signal is written corresponding two adjacent pixels and charges, and electric discharge TFT T3 is directly electrically connected the second charging TFT The drain electrode of T2 and the lower public pressure wire Com of current potential export the charge for the pixel being electrically connected with the second charging TFT T2 To drag down the current potential of the pixel, wherein the drain D 3 of the electric discharge TFT T3 is located at second metal layer, and public pressure wire Com In the first metal layer.The advantages of designing in this way is: two adjacent pictures can be effectively dragged down under the premise of not sacrificing aperture opening ratio The current potential of one of element.

Please refer to Fig. 2 and Fig. 3, in conjunction with Fig. 1, in order to realize the drain D 3 and public pressure wire Com of electric discharge TFT T3 Between bridge joint, i.e. the bridge joint of second metal layer M2 and the first metal layer M1, existing tft array substrate be provided with via hole V ', The via hole V ' is through to gate insulating layer GI by protective layer PV, exposes the drain D 3 and part common voltage of part TFT T3 Line Com, conductive film 9 ' such as tin indium oxide (Indium Tin Oxide, ITO) are deposited on via hole V ' for connecting electric discharge The drain D 3 and public pressure wire Com of TFT T3.

As shown in Figure 4, Figure 5, the prior art makes the process of the via hole V ' are as follows: uses traditional panchromatic light regulating hood first (Full Tone Mask) FTM is exposed, the quasi- whole photoresist PR formed on the region via hole V ' of removal;Then with remaining light Hindering PR is that shielding layer carries out dry etching to protective layer PV and gate insulating layer GI, since second metal layer M2 is to dry etching The chemically etching feature of blocking and dry etching, the gate insulating layer at the climbing (Tapper) of the drain D 3 of TFT T3 GI is easy to appear undercutting (Under-cut) (region in Fig. 5 shown in virtual coil), forms sharp keen wedge angle.In subsequent conduction In 9 ' deposition process of film, as shown in figure 3, being easy to cause 9 ' rupture of membranes of conductive film at the undercutting of gate insulating layer GI, lead to electricity The bridge joint hindered between higher and electric discharge TFT T3 drain D 3 and public pressure wire Com is unreliable, to influence the display of panel Effect causes product yield to reduce.

Summary of the invention

The purpose of the present invention is to provide a kind of production methods of tft array substrate, can be before not losing aperture opening ratio It puts, avoids gate insulating layer from undercuting at the climbing of the drain electrode of electric discharge TFT, reduce the risk of conductive film rupture of membranes, make The bridge joint that must be discharged between the drain electrode and public pressure wire of TFT is reliable, and so as to improve the display effect of panel, it is good to improve product Rate.

To achieve the above object, the present invention provides a kind of production method of tft array substrate, including with intermediate tone mask plate The step of being exposed for tool, so that the drain electrode of electric discharge TFT and its top at climbing retain thin layer in second metal layer Photoresist, in subsequent dry etch process to gate insulating layer below at the climbing for the drain electrode for being located at the electric discharge TFT into Row protection.

The production method of the tft array substrate specifically includes the following steps:

Step S1, the first metal layer, gate insulating layer, semiconductor active layer, are sequentially formed from bottom to top on substrate Two metal layers and protective layer are coated with photoresist on the protective layer;

The gate insulating layer covers the first metal layer, and the first metal layer includes grid line and common voltage Line;

The protective layer covers the second metal layer, and the second metal layer includes data line, the first source electrode, the first leakage Pole, the second source electrode, the second drain electrode, third source electrode and third drain electrode;

The grid line, semiconductor active layer, the first source electrode and the first drain electrode constitute the first charging TFT, the grid Line, semiconductor active layer, the second source electrode and the second drain electrode constitute the second charging TFT, the grid line, semiconductor active layer, the Three source electrodes and third drain electrode constitute electric discharge TFT;

Step S2, intermediate tone mask plate is provided;

The intermediate tone mask plate include spaced first light shielding part with the second light shielding part, connect second shading Semi light transmitting part and the complete light transmission that is located at first light shielding part and semi light transmitting part between of the portion close to the first light shielding part side Portion;

The corresponding drain electrode for being located at the TFT that discharges in second metal layer of the semi light transmitting part and its top at climbing, it is described complete Full transmittance section is corresponding not to be discharged close to the drain electrode of the electric discharge TFT and TFT positioned at public pressure wire in the first metal layer The top of part that is covered of drain electrode;

Step S3, photoresist is exposed using the intermediate tone mask plate as tool, the complete transmittance section to be located at Photoresist under the complete transmittance section is all removed, and semi light transmitting part make in second metal layer discharge TFT drain electrode and its Top at climbing retains the photoresist of thin layer;

Step S4, dry etching is carried out using remaining photoresist after exposure as shielding layer, obtains being through to grid by protective layer The via hole of insulating layer.

The production method of the tft array substrate further includes step S5, on the via hole deposits conductive film, described to lead Conductive film bridges the public pressure wire in the drain electrode and the first metal layer of the TFT that discharges in the second metal layer.

The material of the first metal layer is the heap stack combination of one or more of copper, aluminium, molybdenum.

The material of the gate insulating layer be silica, silicon nitride, or both combination.

The material of the second metal layer is the heap stack combination of one or more of copper, aluminium, molybdenum.

The material of the protective layer be silica, silicon nitride, or both combination.

The material of the conductive film is tin indium oxide.

Beneficial effects of the present invention: a kind of production method of tft array substrate provided by the invention, with intermediate tone mask plate It is exposed for tool, so that the photoresist of the drain electrode for the TFT that discharges in second metal layer and its top reservation thin layer at climbing, The photoresist for the thin layer being retained in subsequent dry etch process is to grid below at the climbing for the drain electrode for being located at the electric discharge TFT Pole insulating layer is protected, avoid gate insulating layer electric discharge TFT drain electrode climbing at because material difference occur overetch and Undercutting problem reduces the risk of conductive film rupture of membranes, so that the bridge joint between the drain electrode and public pressure wire of electric discharge TFT is reliable, And aperture opening ratio will not be lost, so as to improve the display effect of panel, improve product yield.

Detailed description of the invention

For further understanding of the features and technical contents of the present invention, it please refers to below in connection with of the invention detailed Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.

In attached drawing,

Fig. 1 is existing tft array substrate using 3 TFT as the electrical block diagram of driving unit;

Fig. 2 is schematic top plan view of the existing tft array substrate at via hole;

Fig. 3 is corresponding to the schematic diagram of the section structure at A-A in Fig. 2;

Fig. 4, Fig. 5 are respectively the exposure process of prior art production via hole, the schematic diagram with dry etch process;

Fig. 6 is the schematic diagram of the step S1 of the production method of tft array substrate of the invention;

Fig. 7 is the schematic diagram of the step S2 of the production method of tft array substrate of the invention;

Fig. 8 is the schematic diagram of the step S3 of the production method of tft array substrate of the invention;

Fig. 9 is the schematic diagram of the step S4 of the production method of tft array substrate of the invention;

Figure 10 is the schematic diagram of the step S5 of the production method of tft array substrate of the invention;

Figure 11 is tft array substrate produced by the production method by tft array substrate of the invention in via hole Schematic top plan view;

Figure 12 is that the tft array substrate as produced by the production method of tft array substrate of the invention is with 3 TFT The electrical block diagram of driving unit.

Specific embodiment

Further to illustrate technological means and its effect adopted by the present invention, below in conjunction with preferred implementation of the invention Example and its attached drawing are described in detail.

The present invention provides a kind of production method of tft array substrate, comprising the following steps:

Step S1, referring to Fig. 6, in conjunction with Figure 12, the first metal layer M1, grid are sequentially formed from bottom to top on substrate 1 Insulating layer GI, semiconductor active layer 2, second metal layer M2 and protective layer PV are coated with photoresist PR on the protective layer PV.

The gate insulating layer GI covers the first metal layer M1, and the first metal layer M1 includes gate lines G and public affairs Common voltage line Com;

The protective layer PV covers the second metal layer M2, and the second metal layer M2 includes data line D, the first source electrode S1, the first drain D 1, the second source S 2, the second drain D 2, third source S 3 and third drain D 3;

Figure 12 is please referred to, the gate lines G, semiconductor active layer 2, the first source S 1 and the first drain D 1 constitute first Charge TFT T1, and the gate lines G, semiconductor active layer 2, the second source S 2 and the second drain D 2 constitute the second charging TFT T2, the gate lines G, semiconductor active layer 2, third source S 3 and third drain D 3 constitute electric discharge TFT T3.

Specifically, the preferred glass substrate of the substrate 1;The material of the first metal layer M1 is copper (Cu), aluminium (Al), molybdenum One or more of (Mo) heap stack combination;The material of the gate insulating layer GI is silica (SiOx), silicon nitride Or both (SiNx), combination;The material of the second metal layer M2 is the heap stack combination of one or more of Cu, Al, Mo; The material of the protective layer PV be silica, silicon nitride, or both combination.

Step S2, intermediate tone mask plate (Half Tone Mask, HTM) 3 is provided.

Referring to Fig. 7, the intermediate tone mask plate 3 include spaced first light shielding part 31 and the second light shielding part 32, Connect second light shielding part 32 close to the semi light transmitting part 33 of 31 side of the first light shielding part and be located at first light shielding part 31 with Complete transmittance section 34 between semi light transmitting part 33.

In conjunction with Fig. 8, the semi light transmitting part 33 is corresponding to be located at the drain D 3 of electric discharge TFT T3 in second metal layer M2 and its climbs Top at slope, the complete transmittance section 34 is corresponding to put positioned at public pressure wire Com in the first metal layer M1 close to described The top for the part that the drain electrode of electric TFT T3 and the drain D 3 for not being discharged TFT T3 are covered.

Step S3, described completely saturating referring to Fig. 8, being that tool is exposed photoresist PR with the intermediate tone mask plate 3 Light portion 34 removes the photoresist PR being located under the complete transmittance section 34 all, and semi light transmitting part 33 makes second metal layer The drain D 3 of TFT T3 of discharging in M2 and its top at climbing retain the photoresist PR of thin layer.

Step S4, referring to Fig. 9, in conjunction with Figure 11, dry etching is carried out using remaining photoresist PR after exposure as shielding layer, is obtained To the via hole V for being through to gate insulating layer GI by protective layer PV.

The via hole V expose partial discharge TFT T3 drain D 3 and discharge TFT T3 drain D 3 climbing at, with Part public pressure wire Com.After completing above-mentioned steps S4, the photoresist PR of retained thin layer can be to positioned at the electric discharge Gate insulating layer GI below is protected at the climbing of the drain D 3 of TFT T3, avoids gate insulating layer GI in electric discharge TFT T3 Drain D 3 climbing at overetch and undercutting problem occurs because of material difference, the gate insulating layer GI is located at the electric discharge At the climbing of the drain D 3 of TFT T3 at the climbing of the drain D 3 below for being partially protrude through the electric discharge TFT T3, and the gradient is flat It is slow.

And step S5, referring to Fig. 10, in conjunction with Figure 11 and Figure 12, conductive film 9 is deposited on the via hole V, it is described The drain D 3 and the public pressure wire in the first metal layer M1 that conductive film 9 bridges the TFT T3 that discharges in the second metal layer M2 Com。

Specifically, the material of the conductive film 9 is ITO.

Since at the climbing of the drain D 3 of electric discharge TFT T3 overetch and undercutting will not occur for the gate insulating layer GI Problem, but gentle gradient can reduce the risk of 9 rupture of membranes of conductive film, so that the drain D 3 and common electrical of electric discharge TFT T3 Bridge joint between crimping Com is reliable, and will not lose aperture opening ratio.

In conjunction with Figure 11 and Figure 12, through in tft array substrate made from the above method, the gate lines G is for opening first Charge TFT T1, second charging TFT T2, with electric discharge TFT T3, first charging TFT T1 with second charge TFT T2 the two The data-signal that data line D is transmitted mainly is written corresponding two adjacent pixels and charged by TFT, the source electrode for the TFT T3 that discharges S3, drain D 3 be electrically connected the second charging TFT T2 drain D 2, with the lower public pressure wire Com of current potential, will be with the The charge for the pixel that two charging TFT T2 are electrically connected is exported to drag down the current potential of the pixel, so that the electricity of two adjacent pixels Position is different.

In conclusion the production method of tft array substrate of the invention, is exposed using intermediate tone mask plate as tool, So that the photoresist of the drain electrode for the TFT that discharges in second metal layer and its top reservation thin layer at climbing, in subsequent dry etching The photoresist of retained thin layer protects gate insulating layer below at the climbing for the drain electrode for being located at the electric discharge TFT in the process Shield avoids gate insulating layer at the climbing of the drain electrode of electric discharge TFT because overetch occurs for material difference and undercutting problem, reduction are led The risk of conductive film rupture of membranes so that the bridge joint between the drain electrode and public pressure wire of electric discharge TFT is reliable, and will not lose opening Rate improves product yield so as to improve the display effect of panel.

The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology Other various corresponding changes and modifications are made in design, and all these change and modification all should belong to the appended right of the present invention It is required that protection scope.

Claims (8)

1. a kind of production method of tft array substrate, which is characterized in that be included on substrate (1) and sequentially form from bottom to top One metal layer (M1), gate insulating layer (GI), semiconductor active layer (2), second metal layer (M2) and protective layer (PV), in institute State coating photoresist (PR) on protective layer (PV);Gate insulating layer (GI) covering the first metal layer (M1), described first Metal layer (M1) includes grid line (G) and public pressure wire (Com);
The protective layer (PV) covers the second metal layer (M2), and the second metal layer (M2) includes data line (D), first Source electrode (S1), the first drain electrode (D1), the second source electrode (S2), the second drain electrode (D2), third source electrode (S3) and third drain electrode (D3);
The grid line (G), semiconductor active layer (2), the first source electrode (S1) and the first drain electrode (D1) constitute the first charging TFT (T1), the grid line (G), semiconductor active layer (2), the second source electrode (S2) and the second drain electrode (D2) constitute the second charging TFT (T2), the grid line (G), semiconductor active layer (2), third source electrode (S3) and third drain electrode (D3) constitute electric discharge TFT (T3);
The step of being exposed with intermediate tone mask plate (3) for tool, so that the leakage of middle electric discharge TFT (T3) of second metal layer (M2) Top at pole (D3) and its climbing retains the photoresist (PR) of thin layer, to positioned at the electric discharge in subsequent dry etch process Gate insulating layer (GI) below is protected at the climbing of the drain electrode (D3) of TFT (T3).
2. the production method of tft array substrate as described in claim 1, which is characterized in that specifically includes the following steps:
Step S1, sequentially forming the first metal layer (M1), gate insulating layer (GI), semiconductor from bottom to top on substrate (1) has Active layer (2), second metal layer (M2) and protective layer (PV) are coated with photoresist (PR) on the protective layer (PV);
The gate insulating layer (GI) covers the first metal layer (M1), the first metal layer (M1) include grid line (G), And public pressure wire (Com);
The protective layer (PV) covers the second metal layer (M2), and the second metal layer (M2) includes data line (D), first Source electrode (S1), the first drain electrode (D1), the second source electrode (S2), the second drain electrode (D2), third source electrode (S3) and third drain electrode (D3);
The grid line (G), semiconductor active layer (2), the first source electrode (S1) and the first drain electrode (D1) constitute the first charging TFT (T1), the grid line (G), semiconductor active layer (2), the second source electrode (S2) and the second drain electrode (D2) constitute the second charging TFT (T2), the grid line (G), semiconductor active layer (2), third source electrode (S3) and third drain electrode (D3) constitute electric discharge TFT (T3);
Step S2, intermediate tone mask plate (3) are provided;
The intermediate tone mask plate (3) include spaced first light shielding part (31) with the second light shielding part (32), connect described in Second light shielding part (32) close to the first light shielding part (31) side semi light transmitting part (33) and be located at first light shielding part (31) with Complete transmittance section (34) between semi light transmitting part (33);
The semi light transmitting part (33) is corresponding to be located in second metal layer (M2) at the drain electrode (D3) and its climbing of electric discharge TFT (T3) Top, the complete transmittance section (34) is corresponding to put positioned at public pressure wire (Com) in the first metal layer (M1) close to described The top for the part that the drain electrode of electric TFT (T3) and the drain electrode (D3) for not being discharged TFT (T3) are covered;
It step S3, is that tool is exposed photoresist (PR) with the intermediate tone mask plate (3), the complete transmittance section (34) makes The photoresist (PR) being located under the complete transmittance section (34) is obtained all to be removed, and semi light transmitting part (33) makes second metal layer (M2) drain electrode (D3) of electric discharge TFT (T3) and its top at climbing retain the photoresist (PR) of thin layer in;
Step S4, it is that shielding layer carries out dry etching with remaining photoresist (PR) after exposure, obtains being through to by protective layer (PV) The via hole (V) of gate insulating layer (GI).
3. the production method of tft array substrate as claimed in claim 2, which is characterized in that further include step S5, in the mistake Conductive film (9) are deposited on hole (V), the conductive film (9) bridges the leakage of electric discharge TFT (T3) in the second metal layer (M2) Public pressure wire (Com) in pole (D3) and the first metal layer (M1).
4. the production method of tft array substrate as claimed in claim 2, which is characterized in that the first metal layer (M1) Material is the heap stack combination of one or more of copper, aluminium, molybdenum.
5. the production method of tft array substrate as claimed in claim 2, which is characterized in that the gate insulating layer (GI) Material be silica, silicon nitride, or both combination.
6. the production method of tft array substrate as claimed in claim 2, which is characterized in that the second metal layer (M2) Material is the heap stack combination of one or more of copper, aluminium, molybdenum.
7. the production method of tft array substrate as claimed in claim 2, which is characterized in that the material of the protective layer (PV) For silica, silicon nitride, or both combination.
8. the production method of tft array substrate as claimed in claim 3, which is characterized in that the material of the conductive film (9) For tin indium oxide.
CN201710245925.6A 2017-04-14 2017-04-14 The production method of tft array substrate CN107104077B (en)

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CN108803168A (en) * 2018-06-05 2018-11-13 深圳市华星光电半导体显示技术有限公司 A kind of array substrate and preparation method thereof, liquid crystal display device

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