CN107195600A - Chip-packaging structure - Google Patents
Chip-packaging structure Download PDFInfo
- Publication number
- CN107195600A CN107195600A CN201710471323.2A CN201710471323A CN107195600A CN 107195600 A CN107195600 A CN 107195600A CN 201710471323 A CN201710471323 A CN 201710471323A CN 107195600 A CN107195600 A CN 107195600A
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- Prior art keywords
- chip
- protective cover
- wafer
- packaging structure
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
The invention discloses a kind of chip-packaging structure, including：Substrate；Wafer, the wafer is fixed on the surface of the substrate；Protection device; covered on outside the protection device on the wafer; the protection device includes protective cover and insulator spacer; the protection be located on the substrate and the protective cover at least a portion be located at the wafer the remote substrate side, the insulator spacer is filled between the protective cover and the wafer；Plastic shell, the plastic shell sets on the substrate and covered on outside in the protection device.Chip-packaging structure according to embodiments of the present invention; by setting protective cover on wafer; the circuit structure of crystal column surface can be played a protective role, strengthen the reliability of chip-packaging structure, improve the job stability and safety in utilization of the control system of chip-packaging structure.
Description
Technical field
The present invention relates to electronic technology field, more particularly, to a kind of chip-packaging structure.
Background technology
With society high speed development, semiconductor chip as the core devices of electronic technology in many industries it is a large amount of
Using, and greatly promoted the development of social productive forces.However as the extensive use of semiconductor chip, people are to semiconductor
The use requirement of chip is also improved constantly, therefore has emerged high performance processor, MCU, wifi chip and storage chip etc.
Polytype semiconductor chip.It is used for storing due to semiconductor chip, some important informations is transmitted, so its is reliable
Property, security turn into user's increasingly focus of attention.
At present, electromagnetic interference, artificial invasion etc. bring serious influence to the normal work of semiconductor chip.It is wherein artificial
Invasion is by chip progress destructiveness Kaifeng, obtaining the logical construction of chip internal, and then seek to invade the effective of chip
Approach.When chip is by above-mentioned harm, the phenomenons such as disorderly, shutdown occur in the system of chip controls, will be caused when serious
The personal information of user is stolen, and the system of chip controls is manipulated by illegal molecule, will cause serious to enterprises and individuals
Property loss.
The content of the invention
It is contemplated that at least solving one of technical problem present in prior art.Therefore, the present invention proposes one kind
Chip-packaging structure, with enhancing chip-packaging structure reliability, improves the advantage of the safety in utilization of chip-packaging structure.
Chip-packaging structure according to embodiments of the present invention, including：Substrate；Wafer, the wafer is fixed on the substrate
Surface on；Covered on outside protection device, the protection device on the wafer, the protection device include protective cover and insulation every
Off member, the protection is located on the substrate and at least a portion of the protective cover is located at the remote base of the wafer
The side of plate, the insulator spacer is filled between the protective cover and the wafer；Plastic shell, the plastic shell is set
Cover on the substrate and outside in the protection device.
Chip-packaging structure according to embodiments of the present invention, can be to crystal column surface by setting protective cover on wafer
Circuit structure play a protective role, improve chip-packaging structure reliability, it is ensured that the control system of chip-packaging structure
Job stability and safety in utilization.
According to some embodiments of the present invention, the insulator spacer is adhesive glue, and the protective cover is bonded in the crystalline substance
On circle and the substrate.
In some examples of the present invention, solids is provided with the adhesive glue.
Specifically, the solids is silica spheres or alumina balls.
In some examples of the present invention, the protective cover is formed as tabular.
According to some embodiments of the present invention, cover on the wafer and fixed on the substrate outside the protective cover.
In some examples of the present invention, the insulator spacer is identical with the material of the plastic shell.
According to some embodiments of the present invention, the protective cover is metalwork, and the protective cover connects altogether with the substrate
Connect.
Preferably, the thickness of the protective cover is 0.1mm-0.3mm.
Further, the protective cover is copper material materials and parts.
The additional aspect and advantage of the present invention will be set forth in part in the description, and will partly become from the following description
Obtain substantially, or recognized by the practice of the present invention.
Brief description of the drawings
The above-mentioned and/or additional aspect and advantage of the present invention will become from description of the accompanying drawings below to embodiment is combined
Substantially and be readily appreciated that, wherein：
Fig. 1 is the sectional view of the chip-packaging structure according to some embodiments of the present invention；
Fig. 2 is the sectional view of the chip-packaging structure of other embodiments according to the present invention；
Fig. 3 is the overall structure diagram of protective cover according to embodiments of the present invention.
Reference：
Chip-packaging structure 100,
Substrate 10,
Wafer 20, fixture 210,
Protection device 30, protective cover 310, top plate 3110, support member 3120, insulator spacer 320,
Plastic shell 40,
Connecting line 50.
Embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end
Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached
The embodiment of figure description is exemplary, is only used for explaining the present invention, and is not considered as limiting the invention.
In the description of the invention, it is to be understood that term " thickness ", " on ", " under ", "front", "rear", " left side ",
The orientation or position relationship of the instruction such as " right side ", " top ", " bottom " " interior ", " outer " be based on orientation shown in the drawings or position relationship,
It is for only for ease of the description present invention and simplifies description, rather than to indicate or imply that signified device or element must have specific
Orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can
To be mechanical connection or electrical connection；Can be joined directly together, can also be indirectly connected to by intermediary, Ke Yishi
The connection of two element internals.For the ordinary skill in the art, with concrete condition above-mentioned term can be understood at this
Concrete meaning in invention.
Chip-packaging structure 100 according to embodiments of the present invention, the chip package knot are described in detail below with reference to Fig. 1-Fig. 3
Structure 100 is used in the control panel of electric equipment.
As Figure 1-Figure 2, chip-packaging structure 100 according to embodiments of the present invention, including：Substrate 10, wafer 20, guarantor
Protection unit 30 and plastic shell 40.Wherein substrate 10 plays a part of support to wafer 20, alternatively, and the material of substrate 10 can be with
For aluminium, copper or cermet.Preferably, substrate 10 according to embodiments of the present invention is aluminium base, is made pottery compared to copper and metal
Porcelain, aluminium base 10 can minimize thermal resistance, aluminium base 10 is had fabulous heat-conductive characteristic, accelerate chip-packaging structure
100 radiating rate, can reduce the temperature of chip-packaging structure 100 in operation.Further, aluminium base 10 is more adapted to
In SMT techniques, it is possible to achieve the Automated assembly of chip-packaging structure 100, and the good mechanical performance of aluminium base 10, with more
High mechanical endurance, extends the service life of chip-packaging structure 100.
As Figure 1-Figure 2, wafer 20 is fixed on the surface of the substrate 10.Chip package knot according to embodiments of the present invention
Structure 100 may also include fixture 210, and fixture 210 is arranged between wafer 20 and substrate 10, for wafer 20 to be fixed on into base
On plate 10.Alternatively, fixture 210 is glued membrane, or binding agent.Specifically, the surface of wafer 20 is provided with pad, and sets
There is circuit structure, wafer 20 is fixed on the surface of substrate 10 by fixture 210, as Figure 1-Figure 2, in some of the present invention
In example, chip-packaging structure 100 includes connecting line 50, and connecting line 50 will be corresponding on the pad and substrate 10 on the surface of wafer 20
Pad conducting connection, completes the electrical connection of wafer 20 and substrate 10.
Covered on outside protection device 30 on wafer 20, wherein protection device 30 includes protective cover 310 and insulator spacer 320,
Protective cover 310 set on the substrate 10 and protective cover 310 at least a portion be located at wafer 20 remote substrate 10 side, insulate
Separator 320 is filled between protective cover 310 and wafer 20.It follows that line construction of the protective cover 310 to the surface of wafer 20
Play a part of protection, prevent the exposed circuit structure for making the surface of wafer 20 outside of wafer 20 from leaking, further prevent chip from sealing
The leakage of the information of assembling structure 100, lifts the safety in utilization of chip-packaging structure 100.Need to illustrate, protective cover
It can not be contacted with each other between 310 and wafer 20, wafer 20 contacts with each other with protective cover 310 can cause chip-packaging structure 100 to go out
Existing short circuit, and then destroy the circuit structure on the surface of wafer 20.
As Figure 1-Figure 2, plastic shell 40 sets on the substrate 10 and covered on outside in protection device 30.Plastic shell 40 will
Wafer 20, connecting line 50, protective cover 310 and insulator spacer 320 are encapsulated, and protection is played to chip-packaging structure 100
Effect.For example, when carrying out the assembling of chip-packaging structure 100, wafer 20 is fixed on the substrate 10 first, using connecting line 50
It is connected between wafer 20 and substrate 10, realizes the electrical connection of wafer 20 and substrate 10.Then protective cover 310 is welded by SMT
The mode connect is fixed on the surface of substrate 10, and insulator spacer 320 is filled between wafer 20 and protective cover 310, finally with modeling
Whole chip-packaging structure 100 is packaged by envelope shell 40, completes the assembling of chip-packaging structure 100.
Chip-packaging structure 100 according to embodiments of the present invention, can be right by setting protective cover 310 on wafer 20
The circuit structure on the surface of wafer 20 plays a protective role, and improves the reliability of chip-packaging structure 100, it is ensured that chip package knot
The job stability and safety in utilization of the control system of structure 100.
According to some embodiments of the present invention, insulator spacer 320 is adhesive glue, and protective cover 310 is bonded in the He of wafer 20
On substrate 10.It is understood that insulator spacer 320 is arranged into adhesive glue, it can facilitate and fill insulator spacer 320
Between wafer 20 and substrate 10, make whole chip-packaging structure 100 more firm.Preferably, solids is provided with adhesive glue.
Further, solids is silica spheres or alumina balls.Specifically, using adhesive glue and mixture composition insulation every
Off member 320, insulator spacer 320 is filled between wafer 20 and protective cover 310, so both can be by protective cover 310 and wafer
Separated between 20, it is ensured that be not in contact with each other between protective cover 310 and wafer 20, can facilitate again and fill insulator spacer 320
Between protective cover 310 and wafer 20, wafer 20 and protective cover 310 are bonded together, make whole chip-packaging structure 100 more
Plus firmly.
As shown in figure 1, in some embodiments of the invention, protective cover 310 is formed as tabular, protective cover 310 is set
Part between the top of wafer 20, protective cover 310 and wafer 20 is filled using insulator spacer 320, so that
Protective cover 310 it is simple in construction.
As shown in Fig. 2-Fig. 3, according to some embodiments of the present invention, cover on wafer 20 and be fixed on outside protective cover 310
On substrate 10.Specifically, protective cover 310 is used for the circuit structure for protecting the surface of wafer 20, prevents that circuit structure is exposed and lets out
Leak the information of chip.When carrying out the assembling of chip-packaging structure 100, covered on outside protective cover 310 on wafer 20, protective cover 310
Support member 3120 fixed form such as can be welded by SMT and is fixed together with substrate 10.Between protective cover 310 and wafer 20 not
Directly contact, insulator spacer 320 is filled in the space between protective cover 310 and wafer 20.Further, insulator spacer
320 is identical with the material of plastic shell 40, that is to say, that when processing chip-packaging structure 100, by protective cover 310
It is outer to cover on wafer 20 and after fixation on the substrate 10, it is integrally machined out using plastic material outside insulator spacer 320 and plastic packaging
Shell 40, consequently facilitating the machine-shaping of chip-packaging structure 100.
As shown in Figure 1-Figure 3, according to some embodiments of the present invention, protective cover 310 is metalwork, protective cover 310 and base
The common ground connection of plate 10.In some examples of the present invention, the protective cover 310 of metal material is arranged to flat board, protective cover 310 is consolidated
The top of insulator spacer 320 is scheduled on, connecting line 50 is provided between protective cover 310 and substrate 10, protective cover 310 and substrate is completed
Common ground connection between 10.As shown in Fig. 2-Fig. 3, in other examples of the present invention, the protective cover 310 of metal material can be with
Including top plate 3110 and support member 3120, wherein top plate 3110 is arranged on side of the wafer 20 away from substrate 10, support member 3120
It is arranged on the lower end of top plate 3110.Between support member 3120 and substrate 10 one is connected to by the way of eutectic weldering or SMT welding
Rise, complete the common ground connection between protective cover 310 and substrate 10.Need to illustrate, protective cover 310 is arranged to metal
Part, common ground connection is used by protective cover 310 and substrate 10, and whole chip-packaging structure 100 can be made to have a zero public electricity
Position reference plane, low impedance path is provided for interference voltage, it is to avoid the voltage breakdown chip-packaging structure produced by electrostatic induction
100, play a part of protecting electromagnetic interference, prevent the normal work of electromagnetic interference influence chip-packaging structure 100, lift chip
The safety in utilization and reliability of encapsulating structure 100.Need to illustrate, when protective cover 310 is working of plastics, protective cover
310 with substrate 10 assemble when, the support member 3120 of protective cover 310 can be fixed on the substrate 10 using binding agent.
Preferably, the thickness of protective cover 310 is 0.1mm-0.3mm.Through inventor's test of many times result verification, work as protective cover
When 310 thickness is 0.1mm-0.3mm, the effect of the anti-electromagnetic interference of protective cover 310 is best.Further, protective cover 310 is
Copper material materials and parts.The protective cover 310 of copper product preferably electromagnetic wave absorption can be radiated, and can play more preferable anti-electromagnetic interference
Effect.
The chip-packaging structure 100 according to the specific embodiment of the invention is described in detail below with reference to Fig. 2-Fig. 3, is worth understanding
, describe to be merely illustrative below, rather than to the concrete restriction of the present invention.
As shown in Fig. 2-Fig. 3, chip-packaging structure 100 includes substrate 10, wafer 20, connecting line 50, the and of plastic shell 40
Protection device 30, wherein substrate 10 use aluminium base 10, the selection binding agent of fixture 210.Protection device 30 includes protective cover 310
With insulator spacer 320, protective cover 310 uses copper material, and protective cover 310 includes top plate 3110 and four support members 3120,
Top plate 3110 is arranged on the top of insulator spacer 320, and surrounding support member 3120 is arranged at the lower end of top plate 3110.Insulation every
Off member 320 and plastic shell 40 are plastic material.
When carrying out the assembling of chip-packaging structure 100, wafer 20 is fixed on aluminium base 10 with fixture 210 first,
It will be electrically connected using connecting line 50 between wafer 20 and substrate 10.Then by protective cover 310 by way of SMT is welded
Four support members 3120 are welded on the substrate 10, complete the common ground connection between protective cover 310 and substrate 10.By insulator spacer
320 are filled in the space between wafer 20 and protective cover 310, realize isolating between wafer 20 and protective cover 310.Finally use
Substrate 10, wafer 20, connecting line 50 and protection device 30 are encapsulated by plastic shell 40, complete chip-packaging structure 100
Assembling.
Chip-packaging structure 100 according to embodiments of the present invention, by the protective cover that copper material is set on wafer 20
310, the circuit structure on the surface of wafer 20 can not only be played a protective role, strengthen the reliability of chip-packaging structure 100, together
When can also make protective cover 310 have anti-electromagnetic interference capability, can effectively prevent chip-packaging structure 100 at work by
The interference of electromagnetic wave, it is ensured that the job stability of the control system of chip-packaging structure 100, improves chip-packaging structure
100 safety in utilization.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " illustrative examples ",
The description of " example ", " specific example " or " some examples " etc. means to combine specific features, the knot that the embodiment or example are described
Structure, material or feature are contained at least one embodiment of the present invention or example.In this manual, to above-mentioned term
Schematic representation is not necessarily referring to identical embodiment or example.Moreover, specific features, structure, material or the spy of description
Point can in an appropriate manner be combined in any one or more embodiments or example.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that：Not
In the case of departing from the principle and objective of the present invention a variety of change, modification, replacement and modification can be carried out to these embodiments, this
The scope of invention is limited by claim and its equivalent.
Claims (10)
1. a kind of chip-packaging structure, it is characterised in that including：
Substrate；
Wafer, the wafer is fixed on the surface of the substrate；
Covered on outside protection device, the protection device on the wafer, the protection device includes protective cover and insulator spacer,
The protection is located on the substrate and at least a portion of the protective cover is located at the remote substrate of the wafer
Side, the insulator spacer is filled between the protective cover and the wafer；
Plastic shell, the plastic shell sets on the substrate and covered on outside in the protection device.
2. chip-packaging structure according to claim 1, it is characterised in that the insulator spacer is adhesive glue, described
Protective cover is bonded on the wafer and the substrate.
3. chip-packaging structure according to claim 2, it is characterised in that solids is provided with the adhesive glue.
4. chip-packaging structure according to claim 3, it is characterised in that the solids is silica spheres or oxygen
Change aluminium ball.
5. chip-packaging structure according to claim 2, it is characterised in that the protective cover is formed as tabular.
6. chip-packaging structure according to claim 1, it is characterised in that covered on outside the protective cover on the wafer and
Fix on the substrate.
7. chip-packaging structure according to claim 6, it is characterised in that the insulator spacer and the plastic shell
Material it is identical.
8. the chip-packaging structure according to any one of claim 1-7, it is characterised in that the protective cover is metal
Part, the protective cover and the substrate common ground connection.
9. chip-packaging structure according to claim 8, it is characterised in that the thickness of the protective cover is 0.1mm-
0.3mm。
10. chip-packaging structure according to claim 8, it is characterised in that the protective cover is copper material materials and parts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710471323.2A CN107195600A (en) | 2017-06-20 | 2017-06-20 | Chip-packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710471323.2A CN107195600A (en) | 2017-06-20 | 2017-06-20 | Chip-packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107195600A true CN107195600A (en) | 2017-09-22 |
Family
ID=59878036
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710471323.2A Pending CN107195600A (en) | 2017-06-20 | 2017-06-20 | Chip-packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107195600A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080158825A1 (en) * | 2006-12-29 | 2008-07-03 | Nokia Corporation | Electronic device and method of assembling an electronic device |
| CN102339763A (en) * | 2010-07-21 | 2012-02-01 | 飞思卡尔半导体公司 | Method for assembling integrated circuit device |
| US20160093796A1 (en) * | 2014-09-30 | 2016-03-31 | Shinko Electric Industries Co., Ltd. | Semiconductor device and method for manufacturing the same |
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2017
- 2017-06-20 CN CN201710471323.2A patent/CN107195600A/en active Pending
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Application publication date: 20170922 |
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