CN107170421B - pixel driving circuit - Google Patents
pixel driving circuit Download PDFInfo
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- CN107170421B CN107170421B CN201710579269.3A CN201710579269A CN107170421B CN 107170421 B CN107170421 B CN 107170421B CN 201710579269 A CN201710579269 A CN 201710579269A CN 107170421 B CN107170421 B CN 107170421B
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- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 72
- 239000003990 capacitor Substances 0.000 claims abstract description 23
- 230000005611 electricity Effects 0.000 claims description 10
- 238000010168 coupling process Methods 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000011017 operating method Methods 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
Abstract
The pixel driving circuit comprises a driving unit, a first transistor and a second transistor. Two ends of the driving unit are respectively coupled to the working voltage and the liquid crystal capacitor. Two ends of the first transistor are respectively coupled to the working voltage and the control end of the driving unit. The first end of the second transistor receives the data signal, the control end of the second transistor receives the first scanning signal, and the second end of the second transistor is coupled to the control end of the first transistor. When the first scanning signal turns on the second transistor, the second transistor outputs the data signal to the first transistor, the first transistor turns on to set the control end of the driving unit to a first voltage level based on the working voltage, and the control end of the driving unit is set to be increased from the first voltage level to a second voltage level through the leakage current of the first transistor.
Description
Technical field
This disclosure relates to a kind of pixel-driving circuits, and in particular to a kind of pixel for improving liquid crystal charging voltage is driven
Dynamic circuit.
Background technique
Now, LCD screen arrogates the market of flat-surface television and plane computer screen.The row of liquid crystal molecule in LCD screen
Column can be electrically charged the size of voltage and be controlled, and change polarizing angle and will cause different grayscale, thus control liquid crystal molecule with
Show the different image of light and shade.
However the scan frequency that resolution ratio needs to improve scanning signal is improved, and in order to improve scan frequency, each picture
Total duration shorten, charging time when corresponding screen switching each time also shortens, if charging to liquid crystal capacitance
Charging voltage it is insufficient, liquid crystal capacitance can not will be adjusted in a short time to target potential, liquid crystal rotation angle will be caused not
Optics penetrance that is enough and reducing panel.
Summary of the invention
One of present disclosure aspect is to be to provide a kind of pixel-driving circuit.Pixel-driving circuit includes that driving is single
Member has first end, second end and control terminal, and the first end of driving unit is coupled to operating voltage, and the second of driving unit
End is coupled to liquid crystal capacitance.The first transistor has first end, second end and control terminal, and the first end of the first transistor couples
To operating voltage, the second end of the first transistor is coupled to the control terminal of driving unit.Second transistor has first end, second
End and control terminal, the first end of second transistor receive data-signal, and the control terminal of second transistor receives the first scanning letter
Number, the second end of second transistor is coupled to the control terminal of the first transistor.Wherein, when the second crystal is connected in the first scanning signal
Guan Shi, second transistor output the data signal to the first transistor, and the first transistor conducting will be driven single based on operating voltage
The control terminal of member is set as first voltage level, by the leakage current of the first transistor by the control terminal setting of driving unit by the
One voltage level is promoted to second voltage level.
Time aspect of the present invention is to be to provide a kind of pixel-driving circuit.Pixel-driving circuit include liquid crystal capacitance,
Driving unit, control unit and reset cell.Driving unit has first end, second end and a control terminal, and the of driving unit
One end is coupled to operating voltage, and the second end of driving unit is coupled to liquid crystal capacitance, and driving unit is to charge to liquid crystal capacitance.
Control unit receives data-signal and is coupled to operating voltage, control of the control unit to control driving unit according to scanning signal
End processed.Reset cell has the first reset transistor single to deactivate driving to reset liquid crystal capacitance and the second reset transistor
Member.
Present disclosure is intended to provide simplifying for present disclosure and makes a summary, so that reader has substantially present disclosure
Understanding, not point out the critical elements of present disclosure embodiment or define scope of the present disclosure.
Detailed description of the invention
For above and other purpose, feature, advantage and embodiment of the invention can be clearer and more comprehensible, the explanation of attached drawing is such as
Under:
Fig. 1 is painted a kind of schematic diagram of pixel-driving circuit in the embodiment according to present disclosure；
Fig. 2 is painted the schematic diagram of the operation waveform of pixel-driving circuit in Fig. 1；
Fig. 3 is painted a kind of schematic diagram of pixel-driving circuit in the embodiment according to present disclosure；
Fig. 4 is painted the schematic diagram of the operation waveform of pixel-driving circuit in Fig. 3.
Description of symbols:
100: pixel-driving circuit
110: control unit
120: driving unit
130: reset cell
N1, N2, N3: endpoint
CST: capacitor
CLC: liquid crystal capacitance
T1、T2、T3、T4、TReset、TCLR: transistor
ILC: leakage current
GSCAN_P, GSCAN_N: scanning signal
GReset: reset signal
GCLR: clear signal
VCOM: reference voltage
GDATA: data-signal
VDD: operating voltage
200: driving method
S210, S220, S230, S240, S250: operating procedure
300: pixel-driving circuit
310: control unit
320: driving unit
330: reset cell
400: driving method
S410, S420, S430, S440, S450: operating procedure
Specific embodiment
About " first " used herein, " second " ... etc., not especially censure the meaning of order or cis-position, also
The non-element described just for the sake of difference with same technique term limiting the present invention or operation.
About " coupling " used herein or " connection ", can refer to two or multiple element mutually directly make entity or electricity
Property contact, or mutually put into effect indirectly body or in electrical contact, and " coupling " or " connection " also can refer to two or multiple element element phase
Interoperability or movement.
It is an embodiment of present disclosure with reference to Fig. 1, Fig. 1 is painted a kind of picture in the embodiment according to present disclosure
The schematic diagram of plain driving circuit 100.Pixel-driving circuit 100 includes control unit 110, driving unit 120 and reset cell
130, pixel-driving circuit 100 is coupled to the liquid crystal capacitance CLC and storage electricity of liquid crystal display panel (not being painted) one of pixel
Hold CST.Voltage level of the pixel-driving circuit 100 to set liquid crystal capacitance CLC and storage capacitors CST, makes liquid crystal display panel
Pixel energy show correct gray-scale intensity or color setting.
In practical application, liquid crystal display panel includes multiple pixels simultaneously, each pixel can have respective liquid crystal capacitance CLC with
And storage capacitors CST, pixel-driving circuit 100 have multiple groups control unit 110 as shown in Figure 1, driving unit 120 and again
It sets unit 130 and respectively drives multiple pixels.In order to illustrate upper succinct, only to drive single a picture in embodiment shown in FIG. 1
The liquid crystal capacitance CLC and storage capacitors CST of element are for example, existing those skilled in the art can be deduced corresponding multiple pixels by Fig. 1
Configuration mode.
In this embodiment, control unit 110 includes transistor T1 and transistor T2.Wherein transistor T2 has first
End, second end (node N1) and control terminal.The first end of transistor T2 is to receive data-signal GDATA, and the of transistor T2
Two ends are coupled to the control terminal of transistor T1, and the control terminal of transistor T2 is to control transistor T1 according to scanning signal GSCAN
The voltage level of control terminal.The enable transistor T2 when scanning signal GSCAN is high logic level, so that data-signal GDATA
It is sent to the control terminal of transistor T1, the forbidden energy transistor T2 when scanning signal GSCAN is low logic level.
Transistor T1 has first end, second end and control terminal.The first end of transistor T1 is to receive operating voltage
VDD, the second end of transistor T1 are coupled to driving unit 120 and reset cell 130, and the control terminal of transistor T1 is coupled to crystal
The second end of pipe T2.In this embodiment, the second end of transistor T1 is coupled to the 4th transistor T4's in driving unit 120
The first end of transistor TCLR in control terminal and reset cell 130.In an embodiment, transistor T1 is that monoxide is brilliant
Body pipe or silicon transistor.
In this embodiment, driving unit 120 includes transistor T4, and it is with first end, second end and control terminal.It is brilliant
The first end of body pipe T4 is coupled to the first end of liquid crystal capacitance CLC to receive operating voltage VDD, the second end of transistor T4
The control terminal of transistor TReset in (first end point is the node N3 in Fig. 1) and reset cell 130, transistor T4 couple
The first end of transistor TCLR into the second end and reset cell 130 of transistor T1.
In this embodiment, reset cell 130 includes transistor TReset and transistor TCLR.Transistor TReset has
First end, second end and control terminal.The first end of transistor TReset is coupled to second of the transistor T4 in driving unit 120
End and liquid crystal capacitance CLC, the second end of transistor TReset are coupled to ground terminal.The control terminal of transistor TReset is to basis
The voltage level of reset signal GReset control node N3.When reset signal GReset is high logic level, transistor
TReset conducting, the voltage level of node N3 is reset, and is that the voltage level of node N3 is reset to zero electricity in this embodiment
Press level (0V) or earthing potential.That is, transistor TReset is used to reset to be input to liquid crystal capacitance CLC and storage
The charging voltage of capacitor CST.
Transistor TCLR has first end (first end point is the node N2 in Fig. 1), second end and control terminal.Transistor
The first end of TCLR is coupled to the 4th transistor in the second end and driving unit 120 of the transistor T1 in control unit 110
The second end of the control terminal of T4, transistor TCLR is coupled to ground terminal.The control terminal of transistor TCLR is to according to clear signal
The voltage level of GCLR control node N2.When clear signal GCLR is high logic level, transistor TCLR conducting, by node N2
Voltage level resetting, in this embodiment, be the voltage level of node N2 is reset to no-voltage level (0V) or ground connection
Current potential.That is, transistor TCLR is used to reset the voltage level for the control terminal for being input to transistor T4.
Liquid crystal capacitance CLC has first end (first end point is the node N3 in Fig. 1) and second end.Liquid crystal capacitance CLC
First end be coupled to driving unit 120 and reset cell 130, the second end of liquid crystal capacitance CLC receives reference voltage VCOM.In
In this embodiment, the first end of liquid crystal capacitance CLC is coupled to the second end and resetting of the 4th transistor T4 in driving unit 120
The first end of transistor TReset in unit 130.
In addition, in this embodiment, as shown in Figure 1, storage capacitors CST and liquid crystal capacitance CLC coupled in parallel, storage capacitors
CST can stablize this target voltage level when liquid crystal capacitance CLC charges to target voltage level.
Fig. 1 and Fig. 2 is referred to together, and Fig. 2 is painted the schematic diagram of the operation waveform of pixel-driving circuit 100 in Fig. 1.In Fig. 2
In the embodiment of depicted operation waveform, it is assumed that operating voltage VDD is 20V, and reference voltage VCOM is according to the positive and negative anodes of picture
Property interacts switching with two voltage levels of 20V in 0V, and data-signal GDATA is set in most according to the gray-scale intensity or color of picture
Low level 0V between highest level 17V, in Fig. 2 period t00 between t08, it is assumed that this picture data letter to be shown
Number GDATA is highest level 17V.
In Fig. 2, it is reduced to low logic level (i.e. from 20V by high logic level in time point t00, reference voltage VCOM
It is reduced to 0V).That is, pixel-driving circuit 100 is operate within positive polarity in time point t00 between time point t08,
Reference voltage VCOM is 0V at this time.
In Fig. 2, the reset signal GReset in time point t01, reset cell 130 is promoted supreme by low logic level
Logic level, with enable transistor TReset, so that the voltage level of node N3 is reduced to 0V, node N3 and reference voltage VCOM
Potential difference be 0V, mean liquid crystal capacitance CLC both ends potential difference (i.e. charging voltage) be 0V.In this embodiment, pixel
Transistor TReset in driving circuit 100 is, so that charging voltage resets to isoelectric, to make liquid in order to which node N3 to be grounded
Brilliant capacitor CLC electric discharge resetting.
In Fig. 2, in time point t02, reset signal GReset is reduced to low logic level by high logic level, with forbidden energy
Transistor TReset.At this point, the voltage level of node N3 is quick condition.
In Fig. 2, supreme logic level is promoted (i.e. from 0V by low logic level in time point t03, data-signal GDATA
It is promoted to 17V), mean that data-signal GDATA is sent to the first end of transistor T2.
In Fig. 2, supreme logic level is promoted by low logic level, is meant in time point t04, scanning signal GSCAN
Transmit the control terminal of scanning signal GSCAN to transistor T2, thus enable transistor T2.In addition, transistor T1 is according to transistor
The voltage level enable of the second end of T2 or forbidden energy.When transistor T2 reaches data-signal GDATA according to scanning signal GSCAN
The control terminal of transistor T1 promotes the voltage level of node N2 after transistor T1 conducting, in this embodiment, node N2
Voltage level will be promoted to GDATA-VtT1 rapidly, VtT1 herein is the critical voltage (threshold of transistor T1
Voltage), it is assumed that VtT1 1.5V, the voltage level of node N2 is first promoted to 15.5V (17V-1.5V) at this time.
It is 20V, the second end (i.e. node N2) higher than transistor T1 that the first end of transistor T1, which is coupled to operating voltage VDD,
Voltage level, therefore leakage current ILC will be generated by the first end of transistor T1 to second end.Further, since transistor TCLR
Itself has a small built-in capacitor, when the built-in capacitor charging by the leakage current ILC of transistor T1 to transistor TCLR,
So that the voltage level of node N2 increases accordingly, make the electricity of node N2 by leakage current ILC as shown in time interval t04~t05
Level is pressed gradually to be promoted to 19.5V from 15.5V.That is, due to the critical voltage of transistor T1 itself, the voltage of node N2
Level is only capable of being promoted to 15.5V (GDATA-VtT1), can use the leakage current ILC by transistor T1 in this present embodiment,
The voltage level of node N2 is set further to be promoted to second voltage level (19.5V) by the first voltage level of script.Yu Yishi
It applies in example, transistor T1 is oxide transistor or silicon transistor.
In this embodiment, control terminal of the voltage level of node N2 to control transistor T4, the voltage position of node N2
Quasi- enable transistor T4 and make the voltage level of node N3 according to the variation of node N2 voltage level, time interval t04~
The voltage level of t05, node N3 will be promoted to N2-VtT4, and VtT4 herein is the critical voltage of transistor T4, it is assumed that VtT4 is
1.5V, the voltage level of node N3 is first promoted to 18V (19.5V-1.5V) at this time.
Since the potential difference that the charging voltage of liquid crystal capacitance CLC is the first end and second end of liquid crystal capacitance CLC (saves
The voltage level of point N3 subtracts the absolute value of reference voltage VCOM, as shown in Fig. 2, being 18V).
In this way, as scanning signal enable transistor T2, by the leakage current ILC of transistor T1 by driving unit
120 control terminal (voltage level of node N2), which is set, is promoted to second voltage level by first voltage level (15.5V)
(19.5V) causes the voltage level of node N3 that can be promoted to 18V indirectly, so that the charging voltage of pixel-driving circuit can reach
18V (voltage level-reference voltage VCOM of N3).In comparison, in currently existing scheme, the electric leakage of transistor T1 if it does not exist
ILC is flowed, charging voltage is only capable of reaching 14V under the influence of the critical voltage of the transistor of two concatenations.
In Fig. 2, low logic level is reduced to by high logic level, is meant in time point t05, data-signal GDATA
Data-signal GDATA is no longer sent to the control terminal of transistor T1.
In Fig. 2, supreme logic level is promoted by low logic level, means biography in time point t06, clear signal GCLR
Clear signal GCLR to transistor TCLR is sent, with enable transistor TCLR.As enable transistor TCLR, the first of transistor TCLR
End (i.e. node N2) can be pulled to ground connection.Therefore, the voltage drop of node N2 is down to 0V (as shown in Figure 2).
In Fig. 2 after time point t07, all signals are all in low logic level, this time is that liquid crystal capacitance is complete
At charging, into display state.
In Fig. 1 and embodiment shown in Fig. 2, time point t00 to time point t08, i.e. reference voltage VCOM are fixed
In 0V.When liquid crystal is fixed for a long time shows identical grayscale, it is easy to happen fixed and can not normally switches.In order to extend liquid crystal
The polarity of the voltage of driving circuit use can be periodically switched in the service life of material, make liquid crystal in positive deflection and negative bias
It is converted between turning, can be to avoid same rotation angle is fixed on for a long time the problem of, therefore, after time point t08, with reference to electricity
Press the VCOM reverse of polarity.
In Fig. 2, supreme logic level is promoted by low logic level and (is mentioned from 0V in time point t08, reference voltage VCOM
Rise to 20V).That is, pixel-driving circuit 100 is operate within negative polarity in time point t08 between time point t15, this
When reference voltage VCOM be 20V.
In Fig. 2, in time point t09, reset signal GReset promotes supreme logic level by low logic level, with enable
Transistor TReset, so that the voltage level of node N3 is reduced to 0V.Crystalline substance in this embodiment, in pixel-driving circuit 100
Body pipe TReset is, so that charging voltage resets to isoelectric, to make liquid crystal capacitance CLC electric discharge weight in order to which node N3 to be grounded
It sets.
In Fig. 2, in time point t10, reset signal GReset is reduced to low logic level by high logic level, with forbidden energy
Transistor TReset.At this point, the voltage level of node N3 is quick condition.
It is low logic level (i.e. 0V), data-signal GDATA transmission in time point t11, data-signal GDATA in Fig. 2
To the first end of transistor T2.
In Fig. 2, supreme logic level, scanning letter are promoted by low logic level in time point t12, scanning signal GSCAN
Number GSCAN is sent to the control terminal of transistor T1, thus enable transistor T1.Then, it is single to be sent to driving by data-signal GDATA
The control terminal of transistor T4 in member 120, since data-signal GDATA is low logic level, transistor T4 maintains shutdown,
But the built-in capacitor of leakage current ILC and transistor TCLR because of transistor T1, so that the voltage of node N3 is in the area t12~t13
Between be promoted to voltage quasi position 2V (being set to 0V in reset phase).
Since the potential difference that the charging voltage of liquid crystal capacitance CLC is the first end and second end of liquid crystal capacitance CLC (saves
The voltage level of point N3 subtracts the absolute value of reference voltage VCOM, as shown in Fig. 2, being 18V), therefore, as data-signal GDATA
Be negative polarity chron, can also promote the charging voltage of liquid crystal.
In Fig. 2, low logic level is reduced to by high logic level, is meant in time point t13, scanning signal GSCAN
Data-signal GDATA is no longer sent to the control terminal of transistor T4.
In Fig. 2, supreme logic level is promoted by low logic level in time point t14, clear signal GCLR, is meant clear
Except signal GCLR is sent to transistor TCLR, with enable transistor TCLR.Therefore, the voltage of node N2 resets to no-voltage position
It is quasi-.In this embodiment, the transistor TCLR in pixel-driving circuit 100 is in order to which the voltage of node N2 is reset to no-voltage
Level.
In Fig. 2, after time point t15, all signals are all in low logic level, this time is that liquid crystal capacitance is complete
At charging, into display state.
Another pixel driver is painted in the embodiment according to present disclosure also referring to Fig. 3 and Fig. 4, Fig. 3
The schematic diagram of circuit 300, Fig. 4 are painted the schematic diagram of the operation waveform of pixel-driving circuit 300.Preceding embodiment is compared, in Fig. 3
In pixel-driving circuit 300 can be operated according to the reference voltage VCOM of corresponding opposed polarity.
Pixel-driving circuit 300 includes control unit 310, driving unit 320 and reset cell 330, pixel driver electricity
Road 300 is coupled to the liquid crystal capacitance CLC and storage capacitors CST of liquid crystal display panel (not being painted) one of pixel.
In this embodiment, control unit 310 includes transistor T1, transistor T2 and transistor T3.Driving unit 320
Include transistor T4.Reset cell 330 includes transistor TReset and transistor TCLR.
The characteristic of transistor T1 and transistor T2 and transistor T1 shown in FIG. 1 and transistor T2 shown in Fig. 3, ruler
Very little, coupling method is all identical.
Transistor T3 has first end, second end and control terminal.The first end of transistor T3 is to receive data-signal
GDATA, the second end of transistor T3 are coupled to the control of the second end of transistor T1, the 4th transistor in driving unit 320
The first end (this endpoint is node N2 shown in Fig. 3) at end and transistor TCLR, the control terminal of transistor T3 is to basis
The voltage level of scanning signal GSCAN_N control node N2.The enable transistor when scanning signal GSCAN_N is high logic level
T3, data-signal GDATA are sent to driving unit 320, the forbidden energy transistor when scanning signal GSCAN_N is low logic level
T3。
Transistor TReset and transistor TCLR and reset cell shown in FIG. 1 in reset cell 330 shown in Fig. 3
The characteristic of transistor TReset and transistor TCLR in 130, size, coupling method are all identical.
The transistor T4's in transistor T4 and driving unit shown in FIG. 1 320 in driving unit 320 shown in Fig. 3
Characteristic, size, coupling method are all identical.
As shown in Figure 1, the pixel-driving circuit 300 of Fig. 3 also has the storage capacitors with liquid crystal capacitance CLC coupled in parallel
CST, storage capacitors CST can stablize this target voltage level when liquid crystal capacitance CLC charges to target voltage level.
In this embodiment, when data-signal GDATA is positive polarity chron with respect to reference voltage VCOM, scanning signal GSCAN_
P is high logic level and scanning signal GSCAN_N is low logic level, with enable transistor T2.Conversely, working as data-signal
GDATA is negative polarity chron with respect to operation signal VCOM, and scanning signal GSCAN_P is low logic level and scanning signal GSCAN_N
For high logic level, with enable transistor T3.
Fig. 3 and Fig. 4 is referred to together, and Fig. 4 is painted the schematic diagram of the operation waveform of pixel-driving circuit 300 in Fig. 3.In Fig. 4
In the embodiment of depicted operation waveform, it is assumed that operating voltage VDD is 20V, and reference voltage VCOM is according to the positive and negative anodes of picture
Property interacts switching with two voltage levels of 18V in 0V, and data-signal GDATA is set in most according to the gray-scale intensity or color of picture
Low level 0V between highest level 17V, in Fig. 4 period t00 between t08, it is assumed that this picture data letter to be shown
Number GDATA is highest level 17V.
In Fig. 4, it is reduced to low logic level (i.e. from 18V by high logic level in time point t00, reference voltage VCOM
It is reduced to 0V).That is, pixel-driving circuit 300 is operate within positive polarity in time point t00 between time point t08,
Reference voltage VCOM is 0V at this time.
In Fig. 4, the reset signal GReset in time point t01, reset cell 330 is promoted supreme by low logic level
Logic level, with enable transistor TReset, so that the voltage level of node N3 is reduced to 0V, node N3 and reference voltage VCOM
Potential difference be 0V, mean liquid crystal capacitance CLC both ends potential difference (i.e. charging voltage) be 0V.In this embodiment, pixel
Transistor TReset in driving circuit 300 is, so that charging voltage resets to isoelectric, to make liquid in order to which node N3 to be grounded
Brilliant capacitor CLC electric discharge resetting.
In Fig. 4, in time point t02, reset signal GReset is reduced to low logic level by high logic level, with forbidden energy
Transistor TReset.At this point, the voltage level of node N3 is quick condition.
In Fig. 4, supreme logic level is promoted (i.e. from 0V by low logic level in time point t03, data-signal GDATA
It is promoted to 17V), mean that data-signal GDATA is sent to the first end of transistor T2.
In Fig. 4, supreme logic level is promoted by low logic level, is meaned in time point t04, scanning signal GSCAN_P
The control terminal of transmission scanning signal GSCAN_P to transistor T2, thus enable transistor T2.In addition, transistor T1 is according to crystalline substance
The voltage level enable of the second end of body pipe T2 or forbidden energy.When transistor T2 according to scanning signal GSCAN by data-signal GDATA
Reaching the control terminal of transistor T1 promotes the voltage level of node N2 after transistor T1 conducting, in this embodiment, section
The voltage level of point N2 will be promoted to rapidly GDATA-VtT1, the critical voltage (threshold that VtT1 herein is transistor T1
Voltage), it is assumed that VtT1 1.5V, the voltage level of node N2 is first promoted to 15.5V (17V-1.5V) at this time.
It is 20V, the second end (i.e. node N2) higher than transistor T1 that the first end of transistor T1, which is coupled to operating voltage VDD,
Voltage level, therefore leakage current ILC will be generated by the first end of transistor T1 to second end.Further, since transistor TCLR
Itself has a small built-in capacitor, when the built-in capacitor charging by the leakage current ILC of transistor T1 to transistor TCLR,
So that the voltage level of node N2 with raising, make the electricity of node N2 by leakage current ILC as shown in time interval t04~t05
Level is pressed gradually to be promoted to 19.5V from 15.5V.That is, due to the critical voltage of transistor T1 itself, the voltage of node N2
Level is only capable of being promoted to 15.5V (GDATA-VtT1), can use the leakage current ILC by transistor T1 in this present embodiment,
The voltage level of node N2 is set further to be promoted to second voltage level (19.5V) by the first voltage level of script.Yu Yishi
It applies in example, transistor T1 is oxide transistor or silicon transistor.
In this embodiment, control terminal of the voltage level of node N2 to control transistor T4, the voltage position of node N2
Quasi- enable transistor T4 and make the voltage level of node N3 according to the variation of node N2 voltage level, time interval t04~
The voltage level of t05, node N3 will be promoted to N2-VtT4, and VtT4 herein is the critical voltage of transistor T4, it is assumed that VtT4 is
1.5V, the voltage level of node N3 is first promoted to 18V (19.5V-1.5V) at this time.
Since the potential difference that the charging voltage of liquid crystal capacitance CLC is the first end and second end of liquid crystal capacitance CLC (saves
The voltage level of point N3 subtracts the absolute value of reference voltage VCOM, as shown in figure 4, being 18V).
In this way, as scanning signal enable transistor T2, by the leakage current ILC of transistor T1 by driving unit
120 control terminal (voltage level of node N2), which is set, is promoted to second voltage level by first voltage level (15.5V)
(19.5V) causes the voltage level of node N3 that can be promoted to 18V indirectly, so that the charging voltage of pixel-driving circuit can reach
18V (voltage level-reference voltage VCOM of N3).In comparison, in currently existing scheme, the electric leakage of transistor T1 if it does not exist
ILC is flowed, charging voltage is only capable of reaching 14V under the influence of the critical voltage of the transistor of two concatenations.
In Fig. 4, low logic level is reduced to by high logic level, is meant in time point t05, data-signal GDATA
Data-signal GDATA is no longer sent to the control terminal of transistor T1.
In Fig. 4, supreme logic level is promoted by low logic level, means biography in time point t06, clear signal GCLR
Clear signal GCLR to transistor TCLR is sent, with enable transistor TCLR.Therefore, the voltage drop of node N2 is down to 0V.
In Fig. 4, time interval t07~t08, all signals are all in low logic level, this time is liquid crystal capacitance
Charging is completed, into display state.
In Fig. 4, supreme logic level is promoted by low logic level and (is mentioned from 0V in time point t08, reference voltage VCOM
Rise to 18V).That is, pixel-driving circuit 300 is operate within negative polarity in time point t08 between time point t15, this
When reference voltage VCOM be 18V.
In Fig. 4, in time point t09, reset signal GReset promotes supreme logic level by low logic level, with enable
Transistor TReset, so that the voltage level of node N3 is reduced to 0V.Crystalline substance in this embodiment, in pixel-driving circuit 300
Body pipe TReset is, so that charging voltage resets to isoelectric, to make liquid crystal capacitance CLC electric discharge weight in order to which node N3 to be grounded
It sets.
In Fig. 4, in time point t10, reset signal GReset is reduced to low logic level by high logic level, with forbidden energy
Transistor TReset.At this point, the voltage level of node N3 is quick condition.
In Fig. 4, low logic level (i.e. 0V), data-signal GDATA are maintained in time point t11, data-signal GDATA
It is sent to the first end of transistor T2.
In Fig. 4, supreme logic level, scanning are promoted by low logic level in time point t12, scanning signal GSCAN_N
Signal GSCAN_N controls the control terminal of transistor T3, thus enable transistor T3.Then, data-signal GDATA is sent to driving
The control terminal of transistor T4 in unit 320 maintains transistor T4 shutdown since data-signal GDATA is low logic level, and
So that the voltage of node N3 maintains 0V (being set to 0V when in resetting) in the section t12~t13.
Since the potential difference that the charging voltage of liquid crystal capacitance CLC is the first end and second end of liquid crystal capacitance CLC (saves
The voltage level of point N3 subtracts the absolute value of reference voltage VCOM, as shown in figure 4, being 18V), therefore, as data-signal GDATA
Be negative polarity chron, can also promote the charging voltage of liquid crystal.
In Fig. 4, low logic level is reduced to by high logic level, is meaned in time point t13, scanning signal GSCAN_N
Data-signal GDATA is no longer sent to the control terminal of transistor T4.
In Fig. 4, supreme logic level is promoted by low logic level in time point t14, clear signal GCLR, is meant clear
Except signal GCLR is sent to transistor TCLR, with enable transistor TCLR.Therefore, the voltage of node N2 resets to no-voltage position
It is quasi-.In this embodiment, the transistor TCLR in pixel-driving circuit 300 is in order to which the voltage of node N2 is reset to no-voltage
Level enables driving unit 320 to close.
In Fig. 4, after time point t15, all signals are all in low logic level, this time is that liquid crystal capacitance is complete
At charging, into display state.
Embodiment compared to Fig. 1, the control unit 310 of Fig. 3 include also transistor T3, are switched in reference voltage VCOM
High voltage level (when namely time point t08 to time point t15 adopts negative polarity driving), transistor T3 can be directly according to data
Signal GDATA sets the voltage level of node N2, in this way, which the voltage level of node N2 will not be because of the electric leakage of transistor T1
It flows and deviates.If the voltage level of node N2 is increased because of the leakage current of transistor T1, the voltage of node N3 will be influenced together
Level increases (such as being increased to 7V by 0V), and the charging voltage at the both ends liquid crystal capacitance CLC will be made to reduce (20V-7V=13V).
Control unit 310 directly adjusts the voltage level of node N2 by transistor T3, it is advantageously ensured that the voltage level of node N2 is not
It can be deviated because of the leakage current of transistor T1.
That is, using pixel-driving circuit 300 shown in Fig. 3 embodiment, in positive polarity driving, using crystal
The leakage current of pipe T1 improves the voltage level (charging voltage is enable to be promoted) of node N2；In negative polarity driving, crystalline substance can avoid
The voltage level (charging voltage is avoided to reduce) of the influence of leakage current node N2 of body pipe T1.
In conclusion according to some embodiments of the pixel-driving circuit of present disclosure, the design of pixel-driving circuit
Can by be added two group transistors (that is, setting transistor TReset and transistor TCLR), allow positive-negative half-cycle transition when, transistor
It can smoothly close.In addition, the design of pixel-driving circuit can promote liquid crystal charging electricity with the leakage current ILC of operating voltage
Pressure, and then promote the penetrance of panel.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any art technology
Personnel, without departing from the spirit and scope of the present invention, when various variation and retouching, therefore protection scope of the present invention can be made
Subject to view appended claims institute defender.
Claims (9)
1. a kind of pixel-driving circuit, includes:
One driving unit, has a first end, a second end and a control terminal, and the first end of the driving unit is coupled to one
The second end of operating voltage, the driving unit is coupled to a liquid crystal capacitance；
One the first transistor, has a first end, a second end and a control terminal, and the first end of the first transistor couples
To the operating voltage, the second end of the first transistor is coupled to the control terminal of the driving unit；And
One second transistor, has a first end, a second end and a control terminal, and the first end of the second transistor receives
The control terminal of one data-signal, the second transistor receives one first scanning signal, the second end coupling of the second transistor
It is connected to the control terminal of the first transistor,
Wherein, when the second transistor is connected in first scanning signal, which exports the data-signal to this
The control terminal of the driving unit is set as one first electricity based on the operating voltage by the first transistor, the first transistor conducting
Level is pressed, the control terminal of the driving unit is set by a leakage current of the first transistor and is mentioned by the first voltage level
Rise to a second voltage level.
2. pixel-driving circuit as described in claim 1 also includes one first reset transistor, first reset transistor tool
There are a first end, a second end and a control terminal, the first end of first reset transistor is coupled to the driving unit, should
The second end of first reset transistor is coupled to a ground terminal, and the control terminal of first reset transistor receives a resetting letter
Number.
3. pixel-driving circuit as claimed in claim 2, when wherein the driving unit is connected, which provides a liquid crystal
Charging voltage charges to the liquid crystal capacitance and a storage capacitors in parallel with the liquid crystal capacitance, then when the first resetting crystal
When pipe is connected according to the reset signal, which is coupled to the ground connection for the liquid crystal capacitance and the storage capacitors
End is to reset the liquid crystal capacitance.
4. pixel-driving circuit as described in claim 1 also includes one second reset transistor, second reset transistor tool
There are a first end, a second end and a control terminal, the first end of second reset transistor is coupled to the driving unit
The second end of the control terminal, second reset transistor is coupled to a ground terminal, the control terminal of second reset transistor
Receive a clear signal.
5. pixel-driving circuit as claimed in claim 4, wherein after driving unit conducting, second reset transistor
It is connected according to the clear signal and the control terminal of the driving unit is coupled to the ground terminal and uses the closing driving unit.
6. pixel-driving circuit as described in claim 1, also includes:
One third transistor, has a first end, a second end and a control terminal, and the first end of the third transistor receives
The control terminal of the data-signal, the third transistor receives one second scanning signal, the second end coupling of the third transistor
It is connected to the control terminal of the driving unit.
7. pixel-driving circuit as claimed in claim 6, wherein one end of the liquid crystal capacitance is coupled to the driving unit, the liquid
The other end of brilliant capacitor is coupled to a reference voltage, which alternately has positive polarity or negative polarity, when this is with reference to electricity
Pressure is positive polarity chron, which the second transistor is connected, when the reference voltage reference voltage is negative polarity chron,
The third transistor is connected second scanning signal.
8. a kind of pixel-driving circuit, includes:
One liquid crystal capacitance；
One driving unit, has a first end, a second end and a control terminal, and the first end of the driving unit is coupled to one
The second end of operating voltage, the driving unit is coupled to the liquid crystal capacitance, and the driving unit is to charge to the liquid crystal capacitance；
One control unit receives a data-signal and is coupled to the operating voltage, and the control unit is to according to scan signal
Control the control terminal of the driving unit；And
One reset cell has one first reset transistor to reset the liquid crystal capacitance and one second reset transistor to close
The driving unit is closed,
Wherein after the driving unit is connected, second reset transistor according to a clear signal be connected and by the driving unit
The control terminal be coupled to a ground terminal use close the driving unit.
9. pixel-driving circuit as claimed in claim 8, when wherein the driving unit is connected, which provides a liquid crystal
Charging voltage charges to the liquid crystal capacitance and a storage capacitors in parallel with the liquid crystal capacitance, then when the first resetting crystal
When pipe is connected according to a reset signal, which is coupled to a ground connection for the liquid crystal capacitance and the storage capacitors
End is to reset the liquid crystal capacitance.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106116148A TWI618045B (en) | 2017-05-16 | 2017-05-16 | Pixel driving circuit |
| TW106116148 | 2017-05-16 |
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| Publication Number | Publication Date |
|---|---|
| CN107170421A CN107170421A (en) | 2017-09-15 |
| CN107170421B true CN107170421B (en) | 2019-05-21 |
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| CN201710579269.3A Active CN107170421B (en) | 2017-05-16 | 2017-07-17 | pixel driving circuit |
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| TW (1) | TWI618045B (en) |
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| CN111768742B (en) * | 2020-07-17 | 2021-06-01 | 武汉华星光电技术有限公司 | Pixel driving circuit and display panel |
| CN112447140B (en) * | 2020-11-30 | 2021-09-21 | 武汉天马微电子有限公司 | Organic light emitting display panel and display device |
| CN114664263A (en) * | 2020-12-23 | 2022-06-24 | 群创光电股份有限公司 | Light emitting circuit |
| TWI782722B (en) * | 2021-09-28 | 2022-11-01 | 友達光電股份有限公司 | Sensing device and operation method thereof |
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| US9064473B2 (en) * | 2010-05-12 | 2015-06-23 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical display device and display method thereof |
| KR102063642B1 (en) * | 2013-08-07 | 2020-01-09 | 삼성디스플레이 주식회사 | Display panel and display apparatus having the same |
| TWI544266B (en) * | 2015-06-03 | 2016-08-01 | 友達光電股份有限公司 | Pixel circuit |
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| CN107170421A (en) | 2017-09-15 |
| TWI618045B (en) | 2018-03-11 |
| TW201901642A (en) | 2019-01-01 |
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