CN107147389B - High-speed ring oscillator suitable for triple-modular redundancy anti-SET reinforcement technology - Google Patents
High-speed ring oscillator suitable for triple-modular redundancy anti-SET reinforcement technology Download PDFInfo
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- 238000005859 coupling reaction Methods 0.000 claims abstract description 42
- 239000003990 capacitor Substances 0.000 claims abstract description 38
- 230000010355 oscillation Effects 0.000 abstract description 9
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- 230000003471 anti-radiation Effects 0.000 description 2
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
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- H—ELECTRICITY
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Abstract
The invention discloses a high-speed ring oscillator suitable for a triple-modular redundancy anti-SET reinforcement technology, which is based on a SET reinforcement differential voltage-controlled oscillator of a capacitive coupling phase synchronization modular redundancy technology, and consists of three delay loops (namely a first delay loop, a second delay loop and a third delay loop), three coupling capacitors (namely a first coupling capacitor C1, a second coupling capacitor C2 and a third coupling capacitor C3) and a voting capacitor (a first voting circuit). The first delay loop, the second delay loop and the third delay loop form a third loop, the phase synchronization of the three loops is realized through coupling capacitors C1, C2 and C3, the inputs of the three loops are identical, and the control voltage ends Vcont of the delay loops in the three loops are all connected with the control voltage. The invention provides a high-speed ring oscillator which has strong anti-SET capability and improves the VCO oscillation frequency.
Description
Technical Field
The invention relates to the field of anti-radiation integrated circuits, in particular to a Single-Event Transient (SET) -reinforced high-speed annular Voltage Controlled Oscillator (VCO) based on a triple-mode redundancy technology.
Background
The chip working in the radiation environment is bombarded by high-energy particles to ionize electron-hole at the junction of the chip circuit, so that the voltage or current of the junction produces transient fluctuation, and the circuit produces wrong output to produce SET effect. Research has shown that integrated circuits are susceptible to SET and various failures.
The loop VCO is mainly used for circuits such as frequency multiplication, frequency synthesis, and clock generation. When the VCO in a stable operation state of the clock system is bombarded by high-energy particles, the output may generate phase and frequency deviations, and even oscillation is stopped.
The techniques associated with the present invention are described in the following documents:
chinese patent CN 101958713B, SET-reinforced differential voltage-controlled oscillator based on triple-modular redundancy technology, proposes triple-modular redundancy VCO anti-SET reinforcement technology.
Fig. 1 is a VCO structure based on a conventional differential VCO implemented directly using a triple-mode redundancy technique, and is composed of a first differential VCO, a second differential VCO, a third differential VCO, and a first voting circuit. The control voltage is connected with control voltage input ends Vcont of the first differential VCO, the second differential VCO and the third differential VCO, the output OUT of the first differential VCO is connected with an input end A of the first voting circuit, the output OUT of the second differential VCO is connected with an input end B of the first voting circuit, the output OUT of the third differential VCO is connected with an input end C of the first voting circuit, and the output Z of the first voting circuit serves as the output of the whole circuit.
FIG. 2 shows that the inventive technique consists of a first delay loop, a second delay loop, a third delay loop, a first voting circuit and a second voting circuit. The first delay loop, the first voting circuit and the second voting circuit form a first loop, the second delay loop, the first voting circuit and the second voting circuit form a second loop, and the third delay loop, the first voting circuit and the second voting circuit form a third loop. The input of the three loops is identical, the control voltage ends Vcont of the delay loops IN the three loops are all connected with the control voltage, the differential inputs IN+ of the first delay loop, the second delay loop and the third delay loop are all connected with the output Z2 of the second voting circuit, the differential inputs IN-of the first delay loop, the second delay loop and the third delay loop are all connected with the output Z1 of the first voting circuit, the differential output OUT1+ of the first delay loop is connected with the input A1 of the first voting circuit, the differential output OUT2+ of the second delay loop is connected with the input B1 of the first voting circuit, the differential output OUT3+ of the third delay loop is connected with the input C1 of the first voting circuit, the differential output OUT 1-of the first delay loop is connected with the input A2 of the second voting circuit, the differential output OUT 2-of the second delay loop is connected with the input B2 of the second voting circuit, and the differential output OUT 3-of the third delay loop is connected with the input C2 of the second voting circuit, so that the differential structure based on the triple-modular redundancy technology is formed.
For the VCO structure directly implemented by the triple-mode redundancy technology, the common terminal of the three differential VCO loops is only the control voltage Vcont, which can only ensure that the oscillation frequencies of the three differential VCO loops are the same, but the loop phases cannot be controlled, so that the clock phases generated by the three loops are random, and the voting circuit cannot output a correct clock. For the triple-modular redundancy technique in which a voting circuit is introduced into the delay loop, the voter is different from the structure of the delay unit, and the delay of the ring oscillator is increased, resulting in limited oscillation frequency of the VCO. Thus, how to improve high-speed VCO design against SET capability is the most difficult and challenging problem.
Disclosure of Invention
The invention provides a high-speed ring oscillator which has strong anti-SET capability and improves the VCO oscillation frequency.
The technical scheme of the invention is realized as follows:
a high-speed ring oscillator suitable for triple-modular redundancy anti-SET reinforcement technology comprises three loops formed by a first delay loop, a second delay loop and a third delay loop, wherein the three loops realize phase synchronization through coupling capacitors C1, C2 and C3; the inputs of the three loops are the same, and the control voltage end Vcont of each delay loop in the three loops is connected with the control voltage; the first voting circuit is also included;
the output end CO11 of the delay unit 1 in the first delay loop is respectively connected with one end of the phase coupling capacitor C1 and the input end of the delay unit 2 in the first delay loop; the output end CO12 of the delay unit 2 in the first delay loop is connected with the input end of the delay unit 3 in the first delay loop; the output end CO13 of the delay unit 3 in the first delay loop is respectively connected with one end of the phase coupling capacitor C3 and the input end of the delay unit 1 in the first delay loop, and the output end CO13 of the delay unit 3 in the first delay loop is also connected with the input end A of the first voting circuit;
the output end CO21 of the delay unit 1 in the second delay loop is connected with the other end of the phase coupling capacitor C1 and the input end of the delay unit 2 in the second delay loop, the output end CO22 of the delay unit 2 in the second delay loop is respectively connected with one end of the phase coupling capacitor C2 and the input end of the delay unit 3 in the second delay loop, and the output end CO23 of the delay unit 3 in the second delay loop is connected with the input end of the delay unit 1 in the second delay loop and the input end B of the first voting circuit;
the output end CO31 of the delay unit 1 in the third delay loop is connected with the input end of the delay unit 2 in the third delay loop, and the output end CO32 of the delay unit 2 in the third delay loop is respectively connected with the other end of the phase coupling capacitor C2 and the input end of the delay unit 3 in the third delay loop; the output end CO33 of the delay unit 3 in the third delay loop is connected with the other end of the phase coupling capacitor C3, and the input end of the delay unit 1 in the third delay loop, and the output end CO33 of the delay unit 3 in the third delay loop is also connected with the input end C of the first voting circuit;
the output terminal O of the first voting circuit is connected to the output of the VCO.
The invention provides a high-speed ring oscillator suitable for a triple-modular redundancy anti-SET reinforcement technology, which adopts a capacitive coupling phase synchronization technology, wherein a first delay ring and a second delay ring realize phase synchronization through a coupling capacitor C1, a second delay ring and a third delay ring realize phase synchronization through a coupling capacitor C2, the third delay ring and the first delay ring realize phase synchronization through a coupling capacitor C3, so that the phase synchronization of three loops is realized, the outputs of the three loops are connected with the input end of a voting circuit, and correct VCO output signals are voted in a mode of selecting one from two.
The invention can achieve the following technical effects:
1. the coupling capacitors are adopted to effectively synchronize the phases of three VCO loops, thereby reducing loop delay introduced by the voting circuit and improving the oscillation frequency of the anti-radiation VCO.
2. The triple-mode redundant VCO structure is realized, and the sensitivity degree of the VCO to the SET is effectively reduced. When a certain VCO loop is bombarded by single particles, the output signals of the delay units of the VCO will generate phase deviation, while the output signals of the delay units of the other two VCO loops are normal and have the same phase, and the voting circuit obtains the correct clock signal by selecting the output signals of two identical delay units in the three VCO loops, thereby achieving the aim of shielding the wrong clock signal and greatly reducing the sensitivity of the VCO to the SET.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a VCO circuit implemented directly using triple-modular redundancy techniques in the prior art.
Fig. 2 shows a VCO circuit implemented using triple modular redundancy techniques incorporating voting circuits in the delay loop as in the prior art.
Fig. 3 is a circuit of a high-speed ring oscillator suitable for triple-modular redundancy anti-SET reinforcement technology according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 3, a high-speed ring oscillator suitable for a triple-modular redundancy anti-SET reinforcement technology includes three loops formed by a first delay loop, a second delay loop and a third delay loop, wherein the three loops realize phase synchronization through coupling capacitors C1, C2 and C3; the inputs of the three loops are the same, and the control voltage end Vcont of each delay loop in the three loops is connected with the control voltage; the first voting circuit is also included;
the output end CO11 of the delay unit 1 in the first delay loop is respectively connected with one end of the phase coupling capacitor C1 and the input end of the delay unit 2 in the first delay loop; the output end CO12 of the delay unit 2 in the first delay loop is connected with the input end of the delay unit 3 in the first delay loop; the output end CO13 of the delay unit 3 in the first delay loop is respectively connected with one end of the phase coupling capacitor C3 and the input end of the delay unit 1 in the first delay loop, and the output end CO13 of the delay unit 3 in the first delay loop is also connected with the input end A of the first voting circuit;
the output end CO21 of the delay unit 1 in the second delay loop is connected with the other end of the phase coupling capacitor C1 and the input end of the delay unit 2 in the second delay loop, the output end CO22 of the delay unit 2 in the second delay loop is respectively connected with one end of the phase coupling capacitor C2 and the input end of the delay unit 3 in the second delay loop, and the output end CO23 of the delay unit 3 in the second delay loop is connected with the input end of the delay unit 1 in the second delay loop and the input end B of the first voting circuit;
the output end CO31 of the delay unit 1 in the third delay loop is connected with the input end of the delay unit 2 in the third delay loop, and the output end CO32 of the delay unit 2 in the third delay loop is respectively connected with the other end of the phase coupling capacitor C2 and the input end of the delay unit 3 in the third delay loop; the output end CO33 of the delay unit 3 in the third delay loop is connected with the other end of the phase coupling capacitor C3, and the input end of the delay unit 1 in the third delay loop, and the output end CO33 of the delay unit 3 in the third delay loop is also connected with the input end C of the first voting circuit;
the output terminal O of the first voting circuit is connected to the output of the VCO.
The invention provides a high-speed ring oscillator suitable for a triple-modular redundancy anti-SET reinforcement technology, which is a SET reinforcement differential voltage-controlled oscillator based on a capacitive coupling phase synchronization modular redundancy technology, wherein the capacitive coupling phase synchronization technology is adopted, a first delay loop and a second delay loop realize phase synchronization through a coupling capacitor C1, the second delay loop and a third delay loop realize phase synchronization through a coupling capacitor C2, the third delay loop and the first delay loop realize phase synchronization through a coupling capacitor C3, so that the phase synchronization of three loops is realized, the output ends of the three loops are connected with the input end of a voting circuit, and the correct VCO output signal is voted in a mode of two alternatives.
The invention provides a high-speed ring oscillator suitable for a triple-modular redundancy anti-SET reinforcement technology, which is characterized in that when three loops of a VCO are not bombarded by SET, under the control of control voltage, a delay unit chain circuit generates a periodic oscillation output signal with consistent phase through a phase coupling capacitor and outputs the periodic oscillation output signal to a voting circuit to generate signal output. At this time, the differential outputs of the delay circuits of the three VCO loops are normal, that is, the oscillation frequencies and phases of the output signals are completely identical, and the first voting circuit receives three completely synchronized clock signals to generate a correct output clock.
When a certain loop is bombarded by high-energy particles, the phase of the output signal of the delay loop of the first loop is deviated when the SET occurs by the first delay loop, the output signals of the delay circuits of the second loop and the third loop are normal, and the voting circuit receives two synchronous clock signals generated by the three loops to generate a correct output clock. Thus, the voting circuit can mask the output signal of the first loop that is affected by the SET to produce a bias to produce the correct output clock.
The invention adopts the capacitive coupling technology to realize the phase between the rings to realize the step-through, is suitable for delay units of various ring oscillators, is suitable for ring oscillators with various delay stages, and is not limited to multimode redundancy anti-SET ring oscillators with triple-mode redundancy.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (1)
1. The high-speed ring oscillator suitable for the triple-modular redundancy anti-SET reinforcement technology is characterized by comprising three loops formed by a first delay loop, a second delay loop and a third delay loop, wherein the three loops realize phase synchronization through phase coupling capacitors C1, C2 and C3; the first delay loop and the second delay loop realize phase synchronization through a coupling capacitor C1, the second delay loop and the third delay loop realize phase synchronization through a coupling capacitor C2, and the third delay loop and the first delay loop realize phase synchronization through a coupling capacitor C3, so that the phase synchronization of three loops is realized; the inputs of the three loops are the same, and the control voltage end Vcont of each delay loop in the three loops is connected with the control voltage; the first voting circuit is also included;
the output end CO11 of the delay unit 1 in the first delay loop is respectively connected with one end of the phase coupling capacitor C1 and the input end of the delay unit 2 in the first delay loop; the output end CO12 of the delay unit 2 in the first delay loop is connected with the input end of the delay unit 3 in the first delay loop; the output end CO13 of the delay unit 3 in the first delay loop is respectively connected with one end of the phase coupling capacitor C3 and the input end of the delay unit 1 in the first delay loop, and the output end CO13 of the delay unit 3 in the first delay loop is also connected with the input end A of the first voting circuit;
the output end CO21 of the delay unit 1 in the second delay loop is connected with the other end of the phase coupling capacitor C1 and the input end of the delay unit 2 in the second delay loop, the output end CO22 of the delay unit 2 in the second delay loop is respectively connected with one end of the phase coupling capacitor C2 and the input end of the delay unit 3 in the second delay loop, and the output end CO23 of the delay unit 3 in the second delay loop is connected with the input end of the delay unit 1 in the second delay loop and the input end B of the first voting circuit;
the output end CO31 of the delay unit 1 in the third delay loop is connected with the input end of the delay unit 2 in the third delay loop, and the output end CO32 of the delay unit 2 in the third delay loop is respectively connected with the other end of the phase coupling capacitor C2 and the input end of the delay unit 3 in the third delay loop; the output end CO33 of the delay unit 3 in the third delay loop is connected with the other end of the phase coupling capacitor C3, and the input end of the delay unit 1 in the third delay loop, and the output end CO33 of the delay unit 3 in the third delay loop is also connected with the input end C of the first voting circuit;
the output terminal O of the first voting circuit is connected to the output of the VCO.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101958713A (en) * | 2010-09-28 | 2011-01-26 | 中国人民解放军国防科学技术大学 | Triple-modular redundancy technology-based single event transient (SET) reinforcement differential voltage-controlled oscillator (VCO) |
| CN105515577A (en) * | 2015-12-29 | 2016-04-20 | 中国科学院电子学研究所 | Anti-SET solidified ring oscillator |
| CN206759423U (en) * | 2017-06-07 | 2017-12-15 | 佛山科学技术学院 | A kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy |
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| US7973576B2 (en) * | 2008-05-21 | 2011-07-05 | Mediatek Inc. | Voltage controlled oscillators and phase-frequency locked loop circuit using the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101958713A (en) * | 2010-09-28 | 2011-01-26 | 中国人民解放军国防科学技术大学 | Triple-modular redundancy technology-based single event transient (SET) reinforcement differential voltage-controlled oscillator (VCO) |
| CN105515577A (en) * | 2015-12-29 | 2016-04-20 | 中国科学院电子学研究所 | Anti-SET solidified ring oscillator |
| CN206759423U (en) * | 2017-06-07 | 2017-12-15 | 佛山科学技术学院 | A kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy |
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