CN107634758A - A kind of phaselocked loop low noise source switch-charge pump - Google Patents
A kind of phaselocked loop low noise source switch-charge pump Download PDFInfo
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- CN107634758A CN107634758A CN201710831632.6A CN201710831632A CN107634758A CN 107634758 A CN107634758 A CN 107634758A CN 201710831632 A CN201710831632 A CN 201710831632A CN 107634758 A CN107634758 A CN 107634758A
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- pmos
- nmos tube
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- charge pump
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Abstract
A kind of phaselocked loop low noise source switch-charge pump, including：First PMOS, the second PMOS, the first current source, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the 6th PMOS, first NMOS tube, the second NMOS tube, the second current source, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, wherein, the grid end of 5th PMOS receives the first pulse signal, and source, drain terminal short circuit are simultaneously connected with the drain terminal of the 3rd PMOS；The grid end of 6th PMOS receives the first pulse signal, and source receives 1/2 times of supply voltage, and drain terminal is connected with the drain terminal of the 3rd PMOS；The grid end of 5th NMOS tube receives the rp pulse of the second pulse signal, and source, drain terminal short circuit are simultaneously connected with the drain terminal of the 3rd NMOS tube.The phaselocked loop low noise source switch-charge pump of the present invention, goes for low pressure applications, and can offset due to noise caused by the charge share of switching tube.
Description
Technical field
The present invention relates to PHASE-LOCKED LOOP PLL TECHNIQUE field, more particularly to a kind of phaselocked loop low noise source switch-charge pump.
Background technology
Phaselocked loop (PLL, Phase Lock Loop) can produce one and input reference clock is protected in frequency and phase
Consistent clock is held, is widely used in synchronous applications.Charge pump type phaselocked loop (CPLL) is by its high speed, low-power consumption, frequency
Wide, the inexpensive advantage of rate capture range is widely used.
Fig. 1 is the circuit theory diagrams of charge pump type phaselocked loop common in the art, as shown in figure 1, charge pump type is locked
Phase ring is by phase frequency detector (PFD), charge pump (CP), loop filter (LPF), voltage controlled oscillator (VCO) and frequency divider
(Divider) this five part is formed.Wherein, the error pulse (UP, DN) that charge pump (CP) exports phase frequency detector (PFD) turns
Error current is changed to, then control voltage is generated after being integrated by loop filter (LPF) follows voltage controlled oscillator (VCO) generation
The clock of reference clock frequency.
Charge pump (CP) is phaselocked loop (PLL) important component, and the switch of current source introduces in charge pump (CP)
Non-ideal effects can have a strong impact on phaselocked loop (PLL) performance.It is common according to the difference of the position switched in charge pump (CP)
Charge pump is broadly divided into：Switch grid end charge pump, switch drain terminal charge pump, switch source charge pump.Electric charge
Switch in pump (CP) carries out switch motion according to pulse signal UP, DN, and can use metal-oxide-semiconductor as switch.
Fig. 2-Fig. 4 is respectively grid end common in the art, drain terminal, the circuit theory diagrams of source switch-charge pump, its
In, the drain terminal, source switch-charge pump in Fig. 3-4 are more suitable for high-speed applications.Drain terminal switch-charge pump in Fig. 3, is being switched
During action, the metal-oxide-semiconductor as current source can have the conversion from linear zone to saturation region, so as to produce current spikes, increase
Output signal Vctrl fluctuation.
In order to reduce current spikes caused by switch motion, buffer is additionally arranged in drain terminal switch-charge pump, Fig. 5 is existing
There are the circuit theory diagrams of the common drain terminal switch-charge pump containing buffer in technology, as shown in figure 5, the drain terminal containing buffer is opened
Charge pump is closed, because switch directly closes on output end, output signal Vctrl can be acted directly on by switching the switching noise of introducing
On.And in order to reduce effect of the switching noise of switch to output signal Vctrl, it is necessary to reduce the chi of the switching tube as switch
It is very little, but under low pressure applications, voltage margin is limited, and reducing the size of switching tube means to increase the resistance of switching tube, will make electricity
Press nargin more insufficient.
Fig. 6 is the circuit concrete structure diagram of source switch-charge pump in Fig. 4, as shown in fig. 6, the source switch-charge pump,
First, second PMOS MP1、MP2Grid end be connected, the second PMOS MP2Grid end, drain terminal short circuit and with first electricity
Stream source IUPIt is connected, the first current source IUPGround connection；
First, second PMOS MP1、MP2Source respectively with the three, the 4th PMOS MP3、MP4Drain terminal be connected, the 3rd,
4th PMOS MP3、MP4Source be connected and receive supply voltage VDD, form loop；
3rd PMOS MP3Grid end receive the first pulse signal UP rp pulse
4th PMOS MP4Grid end ground connection；
First, second NMOS tube MN1、MN2Grid end be connected, the second NMOS tube MN2Grid end, drain terminal short circuit and with second electricity
Stream source IDNIt is connected, the second current source IDNReceive supply voltage VDD；
First, second NMOS tube MN1、MN2Source respectively with the three, the 4th NMOS tube MN3、MN4Drain terminal be connected, the 3rd,
4th NMOS tube MN3、MN4Source be connected and be grounded, form loop；
3rd NMOS tube MN3Grid end receive the second pulse signal DN, the 4th NMOS tube MN4Grid end receive supply voltage
VDD；
First PMOS MP1, the first NMOS tube MN1Drain terminal be connected, output signal output Vctrl.
The source switch-charge pump, switching noise will not act directly on output end, can increase out in low pressure applications
The size of pipe is closed, but charge share caused by switching tube can still produce the performance of noise reduction phaselocked loop (PLL).
In summary, it is necessary to propose a kind of phaselocked loop low noise source switch-charge pump suitable for low pressure applications, and
It can offset due to noise caused by the charge share of switching tube.
The content of the invention
In order to solve the shortcomings of the prior art, it is an object of the invention to provide a kind of phaselocked loop low noise source to open
Charge pump is closed, goes for low pressure applications, and can offset due to noise caused by the charge share of switching tube.
To achieve the above object, phaselocked loop low noise source switch-charge pump provided by the invention, including：
First PMOS, the second PMOS, the first current source, the 3rd PMOS, the 4th PMOS, the 5th PMOS,
Six PMOSs,
First NMOS tube, the second NMOS tube, the second current source, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, its
In,
The grid end of 5th PMOS receives the first pulse signal, source, drain terminal short circuit and with the 3rd PMOS
Drain terminal be connected；
The grid end of 6th PMOS receives first pulse signal, and source receives 1/2 times of supply voltage, drain terminal with
The drain terminal of 3rd PMOS is connected；
The grid end of 5th NMOS tube receives the rp pulse of the second pulse signal, source, drain terminal short circuit and with it is described
The drain terminal of 3rd NMOS tube is connected.
Further, in addition to, the 6th NMOS tube, its grid end receives the rp pulse of second pulse signal, source
1/2 times of supply voltage is received, drain terminal is connected with the drain terminal of the 3rd NMOS tube.
The phaselocked loop low noise source switch-charge pump of the present invention, suitable for applied to low supply voltage and with smaller
Noise, be advantageously implemented the charge pump type phaselocked loop (CPLL) of low noise, charge pump (CP) linearity can also be increased.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
Obtain it is clear that or being understood by implementing the present invention.
Brief description of the drawings
Accompanying drawing is used for providing a further understanding of the present invention, and a part for constitution instruction, and with the present invention's
Embodiment together, for explaining the present invention, is not construed as limiting the invention.In the accompanying drawings：
Fig. 1 is the circuit theory diagrams of charge pump type phaselocked loop common in the art；
Fig. 2 is the circuit theory diagrams of grid end switch-charge pump common in the art；
Fig. 3 is the circuit theory diagrams of drain terminal switch-charge pump common in the art；
Fig. 4 is the circuit theory diagrams of source switch-charge pump common in the art；
Fig. 5 is the circuit theory diagrams of the drain terminal switch-charge pump common in the art containing buffer；
Fig. 6 is the circuit concrete structure diagram of source switch-charge pump in Fig. 4；
Fig. 7 is the circuit theory diagrams according to the phaselocked loop low noise source switch-charge pump of the present invention；
Fig. 8 is the output of the source switch-charge pump and the phaselocked loop low noise source switch-charge pump of the present invention in Fig. 6
The comparison of wave shape figure of signal.
Embodiment
The preferred embodiments of the present invention are illustrated below in conjunction with accompanying drawing, it will be appreciated that described herein preferred real
Apply example to be merely to illustrate and explain the present invention, be not intended to limit the present invention.
Fig. 7 is the circuit theory diagrams of the phaselocked loop low noise source switch-charge pump of the present invention, as shown in fig. 7, of the invention
Phaselocked loop low noise source switch-charge pump,
5th PMOS MP5Grid end receive the first pulse signal UP, source, drain terminal short circuit and with the 3rd PMOS MP3's
Drain terminal is connected；
6th PMOS MP6Grid end receive the first pulse signal UP, source receives 1/2 times of supply voltage VDD, drain terminal
With the 3rd PMOS MP3Drain terminal be connected；
5th NMOS tube MN5Grid end receive the second pulse signal DN rp pulseSource, drain terminal short circuit and with
Three NMOS tube MN3Drain terminal be connected；
6th NMOS tube MN6Grid end receive the second pulse signal DN rp pulseSource receives 1/2 times of power supply
Voltage VDD, drain terminal and the 3rd NMOS tube MN3Drain terminal be connected.
The operation principle of the phaselocked loop low noise source switch-charge pump of the present invention is illustrated in detail below：
First PMOS MP1, the first NMOS tube MN1In electric current be respectively the first current source IUP, the second current source IDNIn
Electric current.When the first pulse signal UP is high level, the first PMOS MP1The 3rd connected PMOS MP3Conducting；When the first arteries and veins
When to rush signal UP be low level, the first PMOS MP1The 3rd connected PMOS MP3Disconnect；When the second pulse signal DN is high electricity
Usually, the first NMOS tube MN1The 3rd connected NMOS tube MN3Conducting；When the second pulse signal DN is low level, the first NMOS
Pipe MN1The 3rd connected NMOS tube MN3Disconnect.
5th PMOS MP5Source, drain terminal short circuit and with the 3rd PMOS MP3Drain terminal be connected, the 5th PMOS MP5's
Grid end and the 3rd PMOS MP3Grid end receive pulse signal (control voltage) opposite polarity, the 5th PMOS MP5Can be with
Offset the 3rd PMOS MP3Clock feedthrough introduce charge share, so as to reduce the noise on output signal Vctrl；
6th PMOS MP6Drain terminal and the 3rd PMOS MP3Drain terminal be connected, the 6th PMOS MP6Source receive 1/2
Supply voltage VDD again, the pulse signal and the 3rd PMOS M that grid end receivesP3Grid end receive pulse signal (control electricity
Pressure) opposite polarity, the 6th PMOS MP6The 3rd PMOS M can be offsetP3Channel charge injection introduce charge share,
So as to reduce the noise on output signal Vctrl.
5th NMOS tube MN5Source, drain terminal short circuit and with the 3rd NMOS tube MN3Drain terminal be connected, the 5th NMOS tube MN5's
Grid end and the 3rd NMOS tube MN3Grid end receive pulse signal (control voltage) opposite polarity, the 5th NMOS tube MN5Can be with
Offset the 3rd NMOS tube MN3Clock feedthrough introduce charge share, so as to reduce the noise on output signal Vctrl；
6th NMOS tube MN6Drain terminal and the 3rd NMOS tube MN3Drain terminal be connected, the 6th NMOS tube MN6Source receive 1/2
Supply voltage VDD again, the pulse signal and the 3rd NMOS tube M that grid end receivesN3Grid end reception pulse signal (control electricity
Pressure) opposite polarity, the 6th NMOS tube MN6The 3rd NMOS tube M can be offsetN3Channel charge injection introduce charge share,
So as to reduce the noise on output signal Vctrl.
6th PMOS MP6, the 6th NMOS tube MN6Source receive 1/2 times of supply voltage VDD, when the first pulse is believed
When number UP, the second pulse signal DN are low level, the first PMOS M can be thoroughly turned offP1, the first NMOS tube MN1, increase electricity
The linearity of lotus pump (CP).
With reference to specific embodiment, having for phaselocked loop low noise source switch-charge pump of the invention is set forth in
Beneficial effect.In order to more intuitively illustrate beneficial effects of the present invention, calculate respectively under the same terms (device size is identical), figure
The waveform of source switch-charge pump and the output signal Vctrl of the phaselocked loop low noise source switch-charge pump of the present invention in 6,
By output signal Vctrl undulating value, compare the source switch-charge pump and the phaselocked loop low noise source of the present invention in Fig. 6
The noise reduction situation of switch-charge pump.
In the present embodiment, the size of each main metal-oxide-semiconductor is as follows：
(W/L)_MP1=8/0.3, (W/L) _ MP3=6/0.15, (W/L) _ MP5=3/0.15, (W/L) _ MP6=0.93/
0.15；
(W/L)_MN1=10/0.5, (W/L) _ MN3=6/0.15, (W/L) _ MN5=3/0.15, (W/L) _ MN6=0.93/
0.15；
Wherein, (W/L) _ for metal-oxide-semiconductor width and length ratio.
Fig. 8 is the output of the source switch-charge pump and the phaselocked loop low noise source switch-charge pump of the present invention in Fig. 6
Signal Vctrl comparison of wave shape figure.As shown in figure 8, the output signal Vctrl of source switch-charge pump in Fig. 6 undulating value
For 1.1mV, and the output signal Vctrl of the phaselocked loop low noise source switch-charge pump of present invention undulating value is 0.36mV.
Limited in one's ability, and the phaselocked loop low noise source switch of the present invention of the reduction switching noise of source switch-charge pump in Fig. 6
Switching noise at least can be reduced to original 1/3 by charge pump.
The phaselocked loop low noise source switch-charge pump of the present invention, suitable for applied to low supply voltage and with smaller
Noise, be advantageously implemented the charge pump type phaselocked loop (CPLL) of low noise, charge pump (CP) linearity can also be increased.
One of ordinary skill in the art will appreciate that：The preferred embodiments of the present invention are the foregoing is only, and are not had to
In the limitation present invention, although the present invention is described in detail with reference to the foregoing embodiments, for those skilled in the art
For, its technical scheme that can be still recorded to foregoing embodiments is modified, or which part technical characteristic is entered
Row equivalent substitution.Within the spirit and principles of the invention, any modification, equivalent substitution and improvements made etc., all should include
Within protection scope of the present invention.
Claims (2)
- A kind of 1. phaselocked loop low noise source switch-charge pump, it is characterised in that including：First PMOS, the second PMOS, the first current source, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the 6th PMOS,First NMOS tube, the second NMOS tube, the second current source, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, wherein,The grid end of 5th PMOS receives the first pulse signal, source, drain terminal short circuit and with the leakage of the 3rd PMOS End is connected；6th PMOS, its grid end receive first pulse signal, and its source receives 1/2 times of supply voltage, its drain terminal It is connected with the drain terminal of the 3rd PMOS；5th NMOS tube, its grid end receive the rp pulse of the second pulse signal, its source and drain terminal short circuit, and with it is described The drain terminal of 3rd NMOS tube is connected.
- 2. phaselocked loop low noise source switch-charge pump according to claim 1, it is characterised in that also include, the 6th NMOS tube, its grid end receive the rp pulse of second pulse signal, and its source receives 1/2 times of supply voltage, its drain terminal with The drain terminal of 3rd NMOS tube is connected.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710831632.6A CN107634758A (en) | 2017-09-15 | 2017-09-15 | A kind of phaselocked loop low noise source switch-charge pump |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710831632.6A CN107634758A (en) | 2017-09-15 | 2017-09-15 | A kind of phaselocked loop low noise source switch-charge pump |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113557667A (en) * | 2019-05-23 | 2021-10-26 | 华为技术有限公司 | Phase-locked loop |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1338822A (en) * | 2000-07-28 | 2002-03-06 | 日本电气株式会社 | Switch noise inhibiting semiconductor device phase lock loop circuit and charge pumping circuit |
| US20040178834A1 (en) * | 2003-03-13 | 2004-09-16 | Lee Kun Seok | Phase-locked loop integrated circuits that support clock signal updates during dead zone compensation time intervals |
| CN101026358A (en) * | 2006-02-24 | 2007-08-29 | 日本电气株式会社 | Offset elimination amplifier and its control method, and display device using same |
| CN204928798U (en) * | 2015-06-30 | 2015-12-30 | 武汉科技大学 | Developments are filled discharge current and are matchd charge pump circuit |
-
2017
- 2017-09-15 CN CN201710831632.6A patent/CN107634758A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1338822A (en) * | 2000-07-28 | 2002-03-06 | 日本电气株式会社 | Switch noise inhibiting semiconductor device phase lock loop circuit and charge pumping circuit |
| US20040178834A1 (en) * | 2003-03-13 | 2004-09-16 | Lee Kun Seok | Phase-locked loop integrated circuits that support clock signal updates during dead zone compensation time intervals |
| CN101026358A (en) * | 2006-02-24 | 2007-08-29 | 日本电气株式会社 | Offset elimination amplifier and its control method, and display device using same |
| CN204928798U (en) * | 2015-06-30 | 2015-12-30 | 武汉科技大学 | Developments are filled discharge current and are matchd charge pump circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113557667A (en) * | 2019-05-23 | 2021-10-26 | 华为技术有限公司 | Phase-locked loop |
| CN113557667B (en) * | 2019-05-23 | 2024-06-04 | 华为技术有限公司 | Phase-locked loop |
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Application publication date: 20180126 |