CN107146765A - Test structure and method of testing - Google Patents
Test structure and method of testing Download PDFInfo
- Publication number
- CN107146765A CN107146765A CN201710322961.8A CN201710322961A CN107146765A CN 107146765 A CN107146765 A CN 107146765A CN 201710322961 A CN201710322961 A CN 201710322961A CN 107146765 A CN107146765 A CN 107146765A
- Authority
- CN
- China
- Prior art keywords
- metal wire
- wafer
- metal
- test structure
- bonding region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The invention provides a kind of test structure and method of testing, the test structure includes the first metal wire and the second metal wire, first metal wire is arranged on the first surface of the first wafer, second metal wire is arranged on the second surface of the second wafer, the second surface of the first surface of first wafer and second wafer is subjected to bonding technology, and first metal wire is crossed to form metal bonding region with second metal wire.In the present invention provides test structure and method of testing, by the way that the first wafer with the first metal wire is bonded with the second wafer with the second metal wire, the first metal wire and the second metal wire is set to be crossed to form metal bonding region, by measure metal bonding region contact resistance can after accurate Characterization bonding technology between metal diffusion and recrystallization fine or not degree, test structure is due to not comprising non-essential through hole resistance and metal wire resistance, so as to prevent the influence of through hole resistance, metal wire resistance and misregistration etc..
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of test structure and method of testing.
Background technology
With the development of science and technology, in semiconductor fabrication, three-dimensional stacked (3D is more and more used on wafer
Wafer stacking) technology, physical connection and electric connection between wafer can be realized by bonding techniques.Wherein, electrically connect
Connecing can be realized by silicon hole (through silicon via), also can form gold by spreading and recrystallizing between metal
Belong to bond area.
The fine or not degree of electric connection determines the quality for the chip to be formed, and conventional method is measurement through hole at present
The resistance of (single via and via chain) characterizes the fine or not degree of electric connection.Wherein metal spreads and recrystallized
The fine or not degree of electric connection can be characterized by measuring the intermetallic contact resistance of bonded interface, by measuring bonded interface
Intermetallic contact resistance, and then the fine or not degree of metal diffusion and recrystallization can be reflected.However, being existing skill as shown in Figure 1
The structural representation being electrically connected between art metal, but the actual measurement result measured in bonding face a except carrying out bonding technology shape
Into contact resistance outside, include the additional resistance that brings of through hole resistance 1, metal wire resistance 2 and misregistration 3 toward contact.By
In with more disturbing factor so that the measurement result of actual measurement is difficult to really reflect metal diffusion and recrystallized in bonding
The fine or not degree of the metal contact resistance in face.
Therefore, it is that those skilled in the art need solution that how the metal contact resistance of accurate para-linkage wafer, which is measured,
Certainly the problem of.
The content of the invention
It is an object of the invention to provide a kind of test structure and method of testing, solve how accurate para-linkage wafer
The problem of metal contact resistance is measured.
In order to solve the above technical problems, the present invention provides a kind of test structure, including the first metal wire and the second metal wire,
First metal wire is arranged on the first surface of the first wafer, and second metal wire is arranged on the second table of the second wafer
On face, the second surface of the first surface of first wafer and second wafer is subjected to bonding technology, and makes described the
One metal wire is crossed to form metal bonding region with second metal wire.
Optionally, in the test structure, first metal wire intersects vertically to form institute with second metal wire
State metal bonding region.
Optionally, in the test structure, the line width of first metal wire is 10nm~10um；Second metal
The line width of line is 10nm~10um.
Optionally, in the test structure, the bonding technology is the hybrid bonded technique of wafer, mixed by the wafer
Closing bonding technology makes the intersection of first metal wire and second metal wire enter row metal diffusion and/or recrystallize.
Optionally, in the test structure, the material bag of the material of first metal wire and second metal wire
Include one kind and its alloy in copper, gold, aluminium, tungsten, nickel and lead.
The present invention also provides a kind of method of testing, comprises the following steps：
The first wafer and the second wafer are provided, the first surface of first wafer has the first metal wire, described second
The second surface of wafer has the second metal wire；
The second surface of the first surface of first wafer and second wafer is subjected to bonding technology, and made described
First metal wire is crossed to form metal bonding region with second metal wire；
Measure the resistance in the metal bonding region.
Optionally, in the method for testing, the resistance in the metal bonding region, four end are measured by four-end method
Method includes：
Power supply is provided for one end of first metal wire, the current value of one end of second metal wire is measured；
The first potential of the other end of first metal wire is measured, the second of the other end of second metal wire is measured
Potential；
The resistance in the strong conjunction region of the metal is the electrical potential difference and the electric current of first potential and second potential
The ratio of value.
Optionally, in the method for testing, first metal wire is made to intersect vertically to be formed with second metal wire
The metal bonding region.
Optionally, in the method for testing, the line width of first metal wire is 10nm~10um；Second metal
The line width of line is 10nm~10um.
Optionally, in the method for testing, by the first surface of first wafer and the second surface of the second wafer
The hybrid bonded technique of wafer is carried out, the metal bonding region is entered row metal diffusion and/or is recrystallized.
In summary, in the present invention provides test structure and method of testing, by by first with the first metal wire
Wafer is bonded with the second wafer with the second metal wire, the first metal wire and the second metal wire is crossed to form metallic bond
Region is closed, can be spread by the contact resistance measured in the metal bonding region of bonding face between metal after accurate Characterization bonding technology
And the fine or not degree of recrystallization, test structure is due to not comprising non-essential through hole resistance and metal wire resistance, and in alignment
Region area is bonded under unfavorable condition constant, so as to prevent the influence of through hole resistance, metal wire resistance and misregistration etc..
Brief description of the drawings
Fig. 1 is the structural representation two being electrically connected between prior art metal
Fig. 2 is the structural representation of the test structure of the embodiment of the present invention；
Fig. 3 is the flow chart of the method for testing of the embodiment of the present invention.
Embodiment
In order that objects, features and advantages of the present invention can be more obvious understandable, accompanying drawing is referred to.It should be clear that this explanation
Structure, ratio, size depicted in book institute accompanying drawings etc., only to coordinate the content disclosed in specification, for being familiar with this
The personage of technology understands and read, and is not limited to enforceable qualifications of the invention, therefore do not have technical essence meaning
Justice, the modification of any structure, the change of proportionate relationship or the adjustment of size are not influenceing effect of the invention that can be generated and institute
Under the purpose that can reach, all should still it fall in the range of disclosed technology contents can be covered.
As shown in Fig. 2 the present invention provides a kind of test structure, including the first metal wire 10 and the second metal wire 20, it is described
First metal wire 10 is arranged on the first surface of the first wafer, and second metal wire 20 is arranged on the second table of the second wafer
On face, the second surface of the first surface of first wafer and second wafer is subjected to bonding technology, and makes described the
One metal wire 10 is crossed to form metal bonding region 30 with second metal wire 20.
In the present embodiment, first metal wire 10 and second metal wire 20 intersect vertically to form the metallic bond
Region 30 is closed, what namely the first metal wire 10 of metal bonding region 30 and the second metal wire 20 were formed in the intersection of bonding face
Region with contact resistance, has less contact area when intersecting vertically, and when intermetallic contact is bad, measures gold
The resistance of category bond area can preferably embody, and in other embodiments, the first metal wire and the second metal wire can be with random angles
Degree is intersecting.It is understood that the first metal wire and the second metal wire be shaped form or linear can, to metal bonding area
Domain is not influenceed, and linear is employed in the present embodiment and is illustrated just for the sake of convenient, intersects vertically and only needs to satisfaction first
Metal wire and the second metal wire be in intersection it is linear be mutually perpendicular in other embodiments, as long as intersecting area is straight line,
Even if not being that vertically can also reach the purpose of the application, such as, into 30 or 60 degree of angles, this angle can be in structure design
When it is pre-set.
Optionally, the line width of first metal wire 10 is 10nm~10um, and the line width of second metal wire 20 is
10nm~10um, the test needs for meeting different product are embodied by the first metal wire and the second metal wire of different line widths.
In a particular embodiment, the first metal wire can also use equal line width with the second metal wire.
In order to preferably realize that metal wire intersects, the bonding technology is the hybrid bonded technique of wafer (HVbrid wafer
Bonding), the hybrid bonded skill of wafer is a kind of conductor/dielectric bonding techniques, including various metal/oxides and/or nitridation
The combination of thing, the intersection of first metal wire 10 and second metal wire 20 is made by the hybrid bonded technique of the wafer
Enter row metal diffusion and/or recrystallize, in a particular embodiment, can be bonded in an environment of high temperature, can also be right
The laggard line unit of activation of the second surface of the first surface of first wafer and the second wafer Jing Guo plasma treatment is closed, and passes through crystalline substance
Bonding between circle can form 3D integrated circuits, can be applied to stacked memory, high vision sensor and stacking-type system core
Piece (SoC) etc..
In the selection of material, the material of the material of first metal wire 10 and second metal wire 20 is copper, gold,
One kind and its alloy in aluminium, tungsten, nickel and lead, above-mentioned material is can be with material extremely, for example, copper has in semiconductor technology
There is good electrical characteristic, while having preferable mechanical stability etc..
The present invention also provides a kind of method of testing, as shown in figure 3, the method for testing comprises the following steps：
S10, the first wafer of offer and the second wafer, the first surface of first wafer have the first metal wire, described
The second surface of second wafer has the second metal wire；
S20, the second surface progress bonding technology by the first surface of first wafer and the second wafer, and make described
First metal wire is crossed to form metal bonding region with second metal wire；
S30, the resistance in the measurement metal bonding region.
In the present embodiment, the resistance in the metal bonding region is measured by four-end method, the four-end method includes：For institute
The one end for stating the first metal wire provides power supply, can be voltage source or current source, measure the electricity of one end of second metal wire
Flow valuve, you can be grounded one end of the second metal wire, by one end of first metal wire and second metal wire
One end forms loop and measured；The first potential of the other end of first metal wire is measured, second metal wire is measured
The other end the second potential there is provided power supply be first metal wire the other end and second metal wire it is another
End forms potential, that is, with voltage；The resistance in the metal bonding region is first potential and second potential
Electrical potential difference and the current value ratio, the resistance in the metal bonding region is can obtain by Ohm's law R=U/I.Its
In, related measurement can be realized by probe, one end of one end of the first metal wire and the other end and the first metal wire with
The other end can all form corresponding test point by related process.
In the present embodiment, first metal wire is made to intersect vertically to form the metal bonding with second metal wire
Region, is intersected vertically and may easily be determined contact area, and the metal that can be formed by intersecting vertically is good for and closes region to confirm phase
Whether the wafer being mutually bonded accurately corresponds to, under normal circumstances, and intersecting vertically can be by the contraposition between the wafer that is mutually bonded
Mark is aligned, and the resistance that metal bonding region is formed can be in predetermined scope, so as to accurate reflection bonding technology
Middle metal diffusion and the stability of recrystallization, eliminate don't-care condition as via process, smithcraft, Alignment Process etc. are brought
Interference, is conducive to quantitative analysis and sets up long term data storehouse.
Optionally, the line width of first metal wire is 10nm~10um, the line width of second metal wire for 10nm~
10um, the test needs for meeting different product are embodied by the first metal wire and the second metal wire of different line widths.Specific
Embodiment in, the first metal wire can also use equal line width with the second metal wire.
In order to preferably realize that metal wire intersects, by the first surface of first wafer and the second surface of the second wafer
The hybrid bonded technique of wafer is carried out, the metal bonding region is entered row metal diffusion and/or is recrystallized, makes the metal bonding
The contact resistance in region is more stable.
In summary, in the present invention provides test structure and method of testing, by by first with the first metal wire
Wafer is bonded with the second wafer with the second metal wire, the first metal wire and the second metal wire is crossed to form metallic bond
Region is closed, can diffusion and recrystallization between metal after accurate Characterization bonding technology by the contact resistance for measuring metal bonding region
Fine or not degree, test structure is due to not comprising non-essential through hole resistance and metal wire resistance, and in the case of misregistration
Bond area area is constant, so as to prevent the influence of through hole resistance, metal wire resistance and misregistration etc..
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Scope.
Claims (10)
1. a kind of test structure, it is characterised in that the test structure includes：
First metal wire, first metal wire is arranged on the first surface of the first wafer；
Second metal wire, second metal wire is arranged on the second surface of the second wafer；
The second surface of the first surface of first wafer and second wafer is subjected to bonding technology, and makes described first
Metal wire is crossed to form metal bonding region with second metal wire.
2. test structure according to claim 1, it is characterised in that first metal wire hangs down with second metal wire
Directly it is crossed to form the metal bonding region.
3. test structure according to claim 1 or 2, it is characterised in that the line width of first metal wire be 10nm~
10um；The line width of second metal wire is 10nm~10um.
4. test structure according to claim 1 or 2, it is characterised in that the bonding technology is the hybrid bonded work of wafer
Skill, makes the intersection of first metal wire and second metal wire enter row metal and expands by the hybrid bonded technique of the wafer
Dissipate and/or recrystallize.
5. test structure according to claim 1 or 2, it is characterised in that the material of first metal wire and described the
The material of two metal wires includes one kind and its alloy in copper, gold, aluminium, tungsten, nickel and lead.
6. a kind of method of testing, it is characterised in that the method for testing comprises the following steps：
The first wafer and the second wafer are provided, the first surface of first wafer has the first metal wire, second wafer
Second surface have the second metal wire；
The second surface of the first surface of first wafer and second wafer is subjected to bonding technology, and makes described first
Metal wire is crossed to form metal bonding region with second metal wire；
Measure the resistance in the metal bonding region.
7. method of testing according to claim 6, it is characterised in that the metal bonding region is measured by four-end method
Resistance, the four-end method includes：
Power supply is provided for one end of first metal wire, the current value of one end of second metal wire is measured；
The first potential of the other end of first metal wire is measured, the second electricity of the other end of second metal wire is measured
Gesture；
The resistance in the metal bonding region is the electrical potential difference and the current value of first potential and second potential
Ratio.
8. the method for testing according to claim 6 or 7, it is characterised in that make first metal wire and second gold medal
Category line intersects vertically to form the metal bonding region.
9. the method for testing according to claim 6 or 7, it is characterised in that the line width of first metal wire be 10nm~
10um；The line width of second metal wire is 10nm~10um.
10. the method for testing according to claim 6 or 7, it is characterised in that by the first surface of first wafer and
The second surface of two wafers carries out the hybrid bonded technique of wafer, the metal bonding region is entered row metal diffusion and/or is tied again
It is brilliant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710322961.8A CN107146765A (en) | 2017-05-09 | 2017-05-09 | Test structure and method of testing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710322961.8A CN107146765A (en) | 2017-05-09 | 2017-05-09 | Test structure and method of testing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107146765A true CN107146765A (en) | 2017-09-08 |
Family
ID=59778626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710322961.8A Pending CN107146765A (en) | 2017-05-09 | 2017-05-09 | Test structure and method of testing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107146765A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110739396A (en) * | 2019-11-11 | 2020-01-31 | 武汉新芯集成电路制造有限公司 | chip structures, round crystal structures and manufacturing method thereof |
| CN111413560A (en) * | 2020-03-10 | 2020-07-14 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Wafer bonding quality reliability test structure and reliability test method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6040239A (en) * | 1997-08-22 | 2000-03-21 | Micron Technology, Inc. | Non-oxidizing touch contact interconnect for semiconductor test systems and method of fabrication |
| JP2011228491A (en) * | 2010-04-20 | 2011-11-10 | Denso Corp | Semiconductor device, and method of manufacturing the same |
| CN203707089U (en) * | 2014-02-18 | 2014-07-09 | 中芯国际集成电路制造(北京)有限公司 | Test structure for monitoring wafer bonding quality |
| CN104465420A (en) * | 2013-09-18 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for acquiring the resistance of water-level bonding structure and semiconductor structure thereof |
-
2017
- 2017-05-09 CN CN201710322961.8A patent/CN107146765A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6040239A (en) * | 1997-08-22 | 2000-03-21 | Micron Technology, Inc. | Non-oxidizing touch contact interconnect for semiconductor test systems and method of fabrication |
| JP2011228491A (en) * | 2010-04-20 | 2011-11-10 | Denso Corp | Semiconductor device, and method of manufacturing the same |
| CN104465420A (en) * | 2013-09-18 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for acquiring the resistance of water-level bonding structure and semiconductor structure thereof |
| CN203707089U (en) * | 2014-02-18 | 2014-07-09 | 中芯国际集成电路制造(北京)有限公司 | Test structure for monitoring wafer bonding quality |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110739396A (en) * | 2019-11-11 | 2020-01-31 | 武汉新芯集成电路制造有限公司 | chip structures, round crystal structures and manufacturing method thereof |
| CN110739396B (en) * | 2019-11-11 | 2023-08-08 | 武汉新芯集成电路制造有限公司 | Chip structure, wafer structure and manufacturing method thereof |
| CN111413560A (en) * | 2020-03-10 | 2020-07-14 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Wafer bonding quality reliability test structure and reliability test method |
| CN111413560B (en) * | 2020-03-10 | 2022-06-10 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Wafer bonding quality reliability test structure and reliability test method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9030216B2 (en) | Coaxial four-point probe for low resistance measurements | |
| US7105856B1 (en) | Test key having a chain circuit and a kelvin structure | |
| JP2005526250A (en) | Method for calibration and de-embedding, device set for de-embedding, and vector network analyzer | |
| CN107146765A (en) | Test structure and method of testing | |
| KR20230006866A (en) | Method for measuring temperature-modulation characteristics of test samples | |
| CN108666227A (en) | Semiconductor devices and its manufacturing method and inspection equipment for semiconductor devices | |
| TWI286215B (en) | Ground-single-ground pad layout for device tester structure | |
| US11402426B2 (en) | Inductive testing probe apparatus for testing semiconductor die and related systems and methods | |
| CN103837809B (en) | The IC layout of test MOSFET matching and method of testing | |
| CN105209924B (en) | Fixture is used in method of testing substrate and substrate detection | |
| US11846670B2 (en) | Chip testing board and chip testing method | |
| US9831139B2 (en) | Test structure and method of manufacturing structure including the same | |
| CN105445636A (en) | Semiconductor testing circuit and method for detecting conductive properties of tested piece | |
| CN207367924U (en) | Wafer and its wafer permit Acceptance Tests structure | |
| CN105203852B (en) | Test board and testing scheme for integrated passive devices | |
| CN204102893U (en) | A kind of semi-conductor test structure | |
| CN104347594B (en) | Silicon through hole test structure, silicon through hole test method and silicon through hole formation method | |
| CN206920483U (en) | Probe card and semiconductor test apparatus | |
| TWI580980B (en) | Method of measuring electrical length in semiconductor testing apparatus and method of conductive region of wafer alignment | |
| Stucchi et al. | Accurate measurements of small resistances in vertical interconnects with small aspect ratios | |
| CN115825569A (en) | Test method | |
| KR100529453B1 (en) | Needle for probe card and method for fabricating the same | |
| JPH05343492A (en) | Inspecting and monitoring method for conductive pattern | |
| JPS618939A (en) | Semiconductor device | |
| TW201533435A (en) | Device and method for measuring internal stress of electronic component |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170908 |