CN107135200A

CN107135200A - High-speed serial bus data transmission method for uplink based on FPGA

Info

Publication number: CN107135200A
Application number: CN201710197939.5A
Authority: CN
Inventors: 沈聪; 李裕; 羿昌宇; 张海辉; 吴敏; 武龙
Original assignee: China Aeronautical Radio Electronics Research Institute
Current assignee: China Aeronautical Radio Electronics Research Institute
Priority date: 2017-03-29
Filing date: 2017-03-29
Publication date: 2017-09-05

Abstract

The invention discloses a kind of high-speed serial bus data transmission method for uplink based on FPGA, comprising user data process step, comprise the steps of：Step 1, packet header is extracted from FPGA FIFO, judge whether data to be sent are more than 256 bytes by packet header, if performing step 2 more than 256 bytes, if performing step 3 less than 256 bytes；Step 2, the data of preceding 256 byte in FIFO are sent to SRIO IP kernel and the data of 256 byte are emptied, judge whether the remaining data in FIFO is more than 256 bytes again, if more than step 2 is repeated if 256 bytes, until remaining data is less than 256 bytes, step 3 is performed；Step 3, the IP kernel that the data in FIFO are sent to SRIO.When carrying out the SRIO data transmission on FPGA using the present invention, with relatively low, the characteristics of data-handling efficiency is higher that be delayed.

Description

High-speed serial bus data transmission method for uplink based on FPGA

Technical field：

Number is sent the present invention relates to a kind of reduction system high speed universal serial bus (serial RapidIO, hereinafter referred to as SRIO) Sent according to the IP kernel in the method for delay, more particularly to reduction FPGA (hereinafter referred to as FPGA) using SRIO The design method of data delay.

Background technology：

RapidIO be earliest by Mercury Computer systems companies of the U.S. be its computation-intensive signal The independently developed bussing technique of reason system.RapidIO is a kind of packet packet switch switching fabric, in network processing unit, centre The communication managed between device and digital signal processor has high speed, low latency, reliable and stable interconnectivity.Its key property is tool There is extremely low retardance and high bandwidth, the high-speed data being suitable between chip and chip, plate and plate, system and system is passed It is defeated.More than 10Gbps bandwidth (specifications of RapidIO 2.0 can provide 100Gbps bandwidth) can be provided, its all agreement is all It is unrelated with software by hard-wired.RapidIO has simplified end points definition, can be mounted in FPGA, only account for chip area Sub-fraction.The FPGA manufacturers of main flow each devise corresponding IP kernel now.

In the function such as the communication commonly used in current system or product and image procossing, the often delay to data transfer has High requirement.Although RapidIO buses communication protocol postpones extremely low in itself, after being integrated in FPGA, data are from user Port, which is input to end points output, needs the various processing procedures of IP kernel by SRIO, including data group bag, unpacks, distributes, flowing Amount control and mistake manages etc., cause inherent delay to rise.

Meanwhile, SRIO agreements regulation maximum 256 bytes per bag data.As shown in figure 1, user is when sending data, generally A serial input output internal memory (abbreviation FIFO once) can be set up in FPGA to cache as transmission.To the data volume of transmission During more than 256 byte, just wait until that the data in FIFO are reached after 256 bytes, then enter data into the input of IP kernel to be sent out Send operation.To transmission data volume be less than 256 byte when, then wait a period of time without follow-up data enter FIFO after input IP again The input of core is transmitted operation.By this way operation FPGA on SRIO send data can cause data send delay compared with Greatly, the delay about 100us that data are exported to physical layer is sent from program, with following drawback：

(1) data-handling efficiency is low.Source and opposite end can be wasted when waiting data volume enough or waiting pending data to reach The resource of FPGA or processor carries out the calculating and detection of data volume, reduces data-handling efficiency.

(2) the high application of real-time is caused not realize.The function such as some communications, data processing and image procossing it is real-time Property require it is higher, if data are too high from reception delay is sent to, may result in these functional faults or can not realize.

The content of the invention：

The goal of the invention of the present invention is to provide a kind of high-speed serial bus data transmission method for uplink based on FPGA, should when using When the SRIO data that method carries out on FPGA are sent, it is delayed relatively low, data-handling efficiency is higher.

The goal of the invention of the present invention is achieved through the following technical solutions：

A kind of high-speed serial bus data transmission method for uplink based on FPGA, includes user data process step, the user Data processing step is comprised the steps of：

Step 1.1, packet header is extracted from FPGA FIFO, whether data to be sent are judged by packet header More than 256 bytes, if performing step 1.2 more than 256 bytes, if performing step 1.3 less than 256 bytes；

Steps 1.2, the data of preceding 256 byte in FIFO are sent to SRIO IP kernel and the data of 256 byte are emptied, Judge whether the remaining data in FIFO is more than 256 bytes again, if more than step 1.2 is repeated if 256 bytes, until remaining Data are less than 256 bytes, perform step 1.3；

Step 1.3, the IP kernel that the data in FIFO are sent to SRIO.

According to features described above, data step also is sent comprising user's input, user's input sends data step and included Following steps：

Whether step 2.1, the FIFO judged on FPGA have data；

Step 2.2, if being waited until if having data, the data in FIFO are sent；By data to be sent if no data Composition data bag, and write in FIFO, wherein, the packet is included in packet header, the packet header comprising number According to packet length.

Brief description of the drawings：

Fig. 1 is that tradition sends data flow using SRIO IP kernel.

Fig. 2 is the structure chart of the packet header described in embodiment.

Fig. 3 is program the general frame.

Fig. 4 is the flow chart of the high-speed serial bus data transmission method for uplink based on FPGA in embodiment.

Fig. 5 is the structural representation of the experimental system used in embodiment.

Embodiment：

With reference to embodiment and accompanying drawing, the present invention is described in further detail.

Fig. 5 is the composition frame chart of an experimental system used in the present embodiment.Whole experimental system mainly includes two pieces There are a piece of XC5VFX70T FPGA and the FPGA development boards of optical module respectively and receive and dispatch totally two optical fiber cables.With two optical fiber Line interconnects the transmitting-receiving port of the optical module of two boards respectively, and xilinx SRIO IP kernel and transmission are loaded in each FPGA Data program.Data are sent to the FPGA on another piece of development board with the FPGA on one of development board, Xilinx can be passed through ChipScope softwares measure delay to monitor FPGA all of the port.

Fig. 3 is the entire block diagram of data transmission method for uplink, and wherein FIFO will be sent as the caching for sending data for temporary User data, its big I weighed according to selected FPGA memory size, notes the size of data of often secondary transmission The capacity of the FIFO can not be more than, otherwise data can lose.Simultaneously as the data to SRIP IP kernel, which are often wrapped, can not be more than 256 Byte, and the data that user to be sent are likely larger than 256 bytes, so needing data control block to be responsible for parsing packet bag Head, extracts the IP kernel that the destination address in packet header is allocated to SRIO, according to the data for the bag data indicated in packet header Amount to carry out subpackage work to data.Packet header structure as shown in Fig. 2 in 64 data 0~15 show send data The address of destination node, 16~31 show data to be sent length, remaining 32~63 can place data.Such as Fig. 4 institutes Show, it is as follows that what data were sent implements step：

The first step, SRIO initialization and link establishment.

1) judge whether port_initialized signals are drawn high after electricity on FPGA, draw high and show that port initialization is completed；

2) judge whether link_initialized signals are drawn high, draw high and show that link initialization is completed.

Second step, user's input sends data：

1) judge whether FIFO empty pins are drawn high, it is sky to draw high expression FIFO, can write data；Drag down then table Showing has data in FIFO, continue waiting for；

2) that draws high FIFO writes enable pin, and by data composition packet write-in FIFO to be sent, data write-in is finished Afterwards, drag down FIFO writes enable pin.

3rd step, processes user data

1) first data taken out in FIFO are packet header, judge whether data to be sent are more than by packet header 256 bytes, if being performed 4) more than 256 bytes, if being performed 5) less than 256 bytes；

2) data of preceding 256 byte in FIFO are sent to SRIO IP kernel and empty the data of 256 byte, then judged Whether the remaining data in FIFO is more than 256 bytes, if more than step 4 is repeated if 256 bytes, until remaining data is less than 5) 256 bytes, perform；

3) data in FIFO are sent to SRIO IP kernel, FIFO empty pins can now be drawn high.

4th step, is examined

Judged by ChipScope softwares data sent from write-in FIFO to SRIO ports between time delay be about 3.5us。

Described above, only example of the present invention, involved chip is not only limited to this 1 section, any Fpga chip is all applied in the present invention, so protection scope of the present invention is not limited thereto, it is any to be familiar with this technology neck The technical staff in domain is in technical scope of the present invention, the change or replacement done, and should all cover the protection in the present invention In the range of.Therefore, protection scope of the present invention should be defined by the protection domain of claims.

Claims

1. a kind of high-speed serial bus data transmission method for uplink based on FPGA, includes user data process step, the number of users Comprised the steps of according to process step：

Step 1.1, packet header is extracted from FPGA FIFO, judge whether data to be sent are more than by packet header 256 bytes, if performing step 1.2 more than 256 bytes, if performing step 1.3 less than 256 bytes；, wherein, the packet bag Data packet length is included in head；

Step 1.2, the data of preceding 256 byte in FIFO are sent to SRIO IP kernel and the data of 256 byte are emptied, then sentenced Whether the remaining data in disconnected FIFO is more than 256 bytes, if more than step 1.2 is repeated if 256 bytes, until remaining data Less than 256 bytes, step 1.3 is performed；

Step 1.3, the IP kernel that the data in FIFO are sent to SRIO.

2. a kind of high-speed serial bus data transmission method for uplink based on FPGA, is also inputted comprising user according to claim 1 Data step is sent, user's input sends data step and comprised the steps of：

Whether step 2.1, the FIFO judged on FPGA have data；

Step 2.2, if being waited until if having data, the data in FIFO are sent；Data to be sent are constituted if no data Packet, and write in FIFO.