CN107134822B

CN107134822B - Battery charging overcurrent protection circuit

Info

Publication number: CN107134822B
Application number: CN201710277207.7A
Authority: CN
Inventors: 李育超
Original assignee: Fujian Fuxin Electronic Technology Co ltd
Current assignee: Fujian Fuxin Electronic Technology Co ltd
Priority date: 2017-04-25
Filing date: 2017-04-25
Publication date: 2023-05-16
Anticipated expiration: 2037-04-25
Also published as: CN107134822A

Abstract

A battery charging overcurrent protection circuit comprises P-type field effect transistors PM1, PM4 and PM5; n-type field effect transistors NM3, NM4 and NM5; the source electrode of PM1 is connected with VDD, the grid electrode is connected with bias, and the drain electrode is connected with the grid electrode of NM5; the drain electrode of the PM1 is also connected with the source electrode of the PM4, and the grid electrode of the PM4 is connected with the CS and the drain electrode is grounded; the drain electrode of NM5 is connected with VDD, and the source electrode is connected with the drain electrode of NM 3; the grid electrode of the NM3 is connected with the grid electrode of the NM4, and the source electrode is grounded; the bias is also connected with the gate of PM5, the source is connected with VDD, the drain is connected with the drain of NM4, and the drain of PM5 is also connected with the gate of NM 4; the source electrode of the NM4 is grounded; the effect of optimizing the battery charging overcurrent protection is achieved.

Description

Battery charging overcurrent protection circuit

Technical Field

The invention relates to the technical field of battery charging, in particular to a circuit design for battery charging overcurrent protection.

Background

Along with the wide application of lithium batteries and the improvement of the charging speed of the lithium batteries, the function and performance requirements of a lithium battery protection IC matched with a lithium battery pack are also synchronously developed. The lithium battery charging overcurrent protection function has become an indispensable function for the protection IC of the higher-end lithium battery.

Some of the circuits now in use have several distinct disadvantages: the requirements on the process are high, the process is not suitable for mass production, the detection failure possibly occurs due to mismatch, the process deviation of the detection threshold voltage is large, the detection precision is poor, and the series of different charging overcurrent threshold specifications and the like cannot be met.

Disclosure of Invention

Therefore, it is necessary to provide a new battery charging circuit to achieve the effect of optimizing the battery charging overcurrent protection.

In order to achieve the above object, the present inventors provide a battery charging overcurrent protection circuit including P-type field effect transistors PM1, PM4, PM5; n-type field effect transistors NM3, NM4 and NM5;

the source electrode of PM1 is connected with VDD, the grid electrode is connected with bias, and the drain electrode is connected with the grid electrode of NM5; the drain electrode of the PM1 is also connected with the source electrode of the PM4, and the grid electrode of the PM4 is connected with the CS and the drain electrode is grounded; the drain electrode of NM5 is connected with VDD, and the source electrode is connected with the drain electrode of NM 3; the grid electrode of the NM3 is connected with the grid electrode of the NM4, and the source electrode is grounded; the bias is also connected with the gate of PM5, the source is connected with VDD, the drain is connected with the drain of NM4, and the drain of PM5 is also connected with the gate of NM 4; the source electrode of the NM4 is grounded;

the VDD is also connected with one end of a current source, and the other end of the current source is connected with the vn electrode of the comparator; the other end of the current source is also connected with one end of a reference voltage trimming circuit, and the other end of the reference voltage trimming circuit is grounded;

the source electrode of NM5 is also connected with the vp electrode of the comparator.

Where VDD is the supply voltage, which may be the external voltage on the chip circuit, bias is the bias voltage.

Compared with the prior art, the technical scheme has the following advantages: (1) Compared with the existing implementation circuit, the implementation circuit for detecting the charging overcurrent protection has low matching requirement on devices of a selected process;

(2) Compared with the existing implementation circuit, the common-mode input voltage of the comparator used in the implementation circuit for the charging overcurrent protection detection can be more than 0V, and the conventional comparator can realize high matching and high gain, so that the detection precision of the charging overcurrent protection threshold point is improved;

(3) Compared with the existing implementation circuit, the implementation circuit for detecting the charging overcurrent protection has higher flexibility, different charging overcurrent protection points can be obtained through trimming, and the applicability is wider;

(4) Compared with the existing implementation circuit, the implementation circuit for detecting the charging overcurrent protection has higher precision, smaller difference of overcurrent protection points among chips and good batch consistency;

(5) Compared with the existing implementation circuit, the implementation circuit for detecting the charging overcurrent protection has low process requirements and wider application range.

Drawings

Fig. 1 is a schematic diagram of an internal and peripheral application circuit of a lithium battery protection IC in a lithium battery pack according to an embodiment of the present invention;

fig. 2 is a schematic circuit diagram of a first type of implementation of detection of charging overcurrent protection according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a second type of implementation of detection of charging overcurrent protection according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a charging overcurrent detection circuit according to an embodiment of the invention.

Detailed Description

In order to describe the technical content, constructional features, achieved objects and effects of the technical solution in detail, the following description is made in connection with the specific embodiments in conjunction with the accompanying drawings.

Referring to fig. 1, the function and performance requirements of a lithium battery protection IC matched with a lithium battery pack are synchronously developed along with the wide application of the lithium battery and the improvement of the charging speed of the lithium battery. The lithium battery charging overcurrent protection function has become an indispensable function for the protection IC of the higher-end lithium battery. Fig. 1 is a schematic block diagram of the internal and peripheral applications of a high-end lithium battery protection IC:

in fig. 1, b+ is the positive electrode of the battery pack, and is usually connected to the positive output terminal of the external charger during charging; and B-is a battery pack cathode, and is usually connected with an external charger cathode during charging. The B-voltage is negative in the normal charging process and is generally between-0.05V and-0.3V, the B-voltage is transmitted to the CS input pin of the protection IC through the resistor R2, and the voltage is unchanged, namely the voltage of the CS input pin in the normal charging process is also between-0.05V and-0.3V. Then, the CS voltage is transmitted to the internal charging overcurrent detection module VD4 of the IC, and when the negative voltage of the CS is lower than the threshold voltage set by VD4 and is maintained for more than a certain delay time, the output pin COUT of the chip is set to a low level, and the charging function of the system is stopped, that is, the charging overcurrent protection occurs.

How to realize a stable and reliable charging overcurrent protection function inside a high-end lithium battery protection IC has become one of the keys of the current design. Specifically, the over-current protection during charging is that the charging current is too large due to some abnormal reasons during the charging process of the lithium battery pack connected with the charger, and when the charging current is greater than a certain set value, the system cuts off the charging loop to stop charging. Since the current in the charging loop is difficult to detect, it is common practice to determine whether the charging overcurrent occurs by detecting the voltage at the CS terminal. In the charging process, the voltage of the CS terminal is negative, and the larger the charging current is, the more the voltage of the CS terminal is negative, so the charging overcurrent protection function can be set as follows: when the system detects that the voltage of CS is lower than a certain threshold value (the voltage value is negative), the system judges that the charging overcurrent occurs, triggers the charging overcurrent protection action and cuts off the charging loop.

In order to realize the function of detecting the overcharge of the VD4 module, a negative voltage comparator and a negative reference voltage generating circuit are theoretically needed, but a simple, economical and feasible circuit for generating the negative reference voltage is not easy to realize. The prior art basically avoids directly designing a negative voltage generating circuit, and adopts other feasible methods to realize the charging overcurrent detection function.

The prior art has the following two implementation methods: 1. the comparison of the negative voltages is achieved with a dual differential pair comparator. 2. The comparison of the negative voltages is achieved with a zero-crossing comparator.

A schematic diagram of the charge over-current protection implemented in the first type of conventional technology is shown in fig. 2;

in fig. 2, a differential pair is added to the common differential pair circuit, two input ends (M0 and M3) of four input ports of the differential pair are connected to zero potential, M1 of signals of the other two input ends is connected to positive reference Voltage (VCIP), M2 is connected to the CS end, and the signal OUT is an output signal.

The working principle is as follows: since the aspect ratios of the devices PM0, PM1, PM2 are the same, constituting a current mirror arrangement, the currents flowing through them are the same, namely: i0 For differential pair transistors M0 and M1, because the gate of M0 is at 0, the gate of M1 is at positive potential, and their source potentials are the same, resulting in a current flowing through device M0 that is greater than the current flowing through device M1, namely: i0 =im0+im1, im0=i+δi, im1=i- δi, im0> Im1; for the differential pair transistors M2 and M3, since the gate potential of M3 is 0, the gate potential of M2 is normally negative and their source potentials are the same, resulting in a current flowing through device M2 that is greater than the current flowing through device M3, namely: i1 =im2+im3, im2=i+δi1, im3=i- δi1, im2> im3.

Thus, the current flowing through device NM0 is: inm0 =im0+im3=i+δi+i- δi1=2i+ (δi- δi1), the current flowing through the device NM1 is: inm1 = im1+ im2 = I- δi + I + δi1 = 2i+ (δi1- δi), as can be seen from the two formulas above, when δi = δi1,

the current Im0 flowing through the device NM0 is equal to the current Im1 flowing through the device NM1, and to make δi=δi1 be satisfied, the gate potential cs= -VCIP of the device M2 is required, at this time, the comparator is in an equilibrium state, when the potential of CS is greater than-VCIP, the device NM1 will enter a linear region, and the output signal OUT outputs a high level; when the potential of CS is less than-VCIP, the device M1 will enter the linear region and the output signal OUT will output a low level. This enables the comparator function with a flip-flop-VCIP to be used to obtain the desired over-charge protection value by changing the value of VCIP. The circuit skillfully utilizes a double differential pair, and has a structure that two input ends are grounded and one input end is connected with positive reference voltage, so that negative voltage comparison is realized, and a negative reference voltage generating circuit is avoided.

The second type of detection schematic diagram for implementing charging overcurrent protection is shown in fig. 3: in the normal charging process shown in fig. 3, the CS terminal voltage is a relatively small negative value, typically-0.05V to-0.30V. The relation between the voltage at the CS terminal and the charging current is: the larger the charging current, the more negative the CS voltage. When the voltage at the CS terminal is lower than a certain negative voltage, the system determines that a charging overcurrent condition occurs. For this purpose, a zero-crossing comparator is provided, which is implemented by introducing a booster circuit at its input. In the figure, the grid electrodes of the device P1 and the device N1 are grounded, under normal conditions (when no charge overcurrent occurs), CS voltage is a small negative value, the grid source voltage of N1 is smaller than the threshold voltage of the grid source voltage, N1 is in a cut-off state, and P1 is always in a conduction state, so that the N end of a comparator is pulled to a power supply voltage, the comparator outputs a low level, when the charge overcurrent occurs, CS voltage becomes more negative, N1 is conducted, the driving capability of N1 is designed to be far stronger than that of P1, so that N1 is in a linear region after being conducted, the potential of N end is pulled to be lower than zero potential, the comparator is turned over, and a high level is output. Triggering the charging overcurrent protection action.

The first class of defects of the detection circuit for realizing the charging overcurrent protection are seen. After careful analysis, this circuit has several significant drawbacks: the requirements on the process are high, the process is not suitable for mass production, detection failure can be caused by mismatch, and the like. The specific analysis concerning these drawbacks is as follows: in the previous analysis we assumed that i0=i1=2i, i.e. PM0 and PM1 were perfectly matched by default, but in practice this was not possible, the matching between the current mirrors met the following condition:

in a lithium battery protection IC, the current Id is of a nA level, so that the overdrive voltage Vgs-Vth value of the MOS transistor is very small and is generally below 100 mV; whereas the threshold voltage Vth mismatch of PM0 and PM1 satisfies the following condition:

σVth＝0.1*tox/sqr(W*L) (2)

the threshold voltage mismatch of the resulting device is also mv-level, which results in a less than ideal match between the current mirrors PM0 and PM1, visually, i.e. the currents I0 and I1 are not equal and may be very different, and in case of very different currents I0 and I1, the comparator may not work properly.

To better illustrate the degree of mismatch (mismatch) of the galvanometers PM0 and PM1 and how the comparator fails to function properly, specific data are brought into the process for computational analysis, and process data are referred to obtain: tox=200a, the width to length ratio of PM0 and PM1 is set to W/l=3um/12 um, the current mirror current id=52na, and the above specific data is taken into formula (2):

σVth＝0.1*tox/sqr(W*L)＝0.1*200A/sqr(3um*12um)＝3.34mV (3)

δvth follows a gaussian distribution, meaning that there is a Vth shift of 0.5% for the transistor that averages more than 3 δ. When Vth is shifted by 3δvth, the current mismatch current between the current mirrors is obtained from equation (1) as:

as can be seen from the above formula, even in the case of a perfect matching of the current mirror dimensions, there is about 0.5% of current mismatch (mismatch) of the current mirror reaching 40% due to mismatch (Vth) between the devices, and in the case of such serious mismatch (mismatch), the negative voltage comparator may be in an abnormal operation state, the charging overcurrent protection function of the system may be disabled, and the reason why the system may not operate normally in the case of 40% of current mismatch (mismatch) of the current mirror is analyzed in detail below.

From the previous data, it can be seen that the current of current mirror PM0 is i0=52na, since PM1 and PM0 present 40% mismatch,

the current resulting in current mirror PM1 is i1=i0 (1-40%) =52na×60% =31.2 nA, as analyzed previously, the currents of device M0 and device M1 are: im0=i+δi, im1=i- δi, and the currents through which they flow differ by 2δi, when their difference currents 2δi >31.2nA, even if the current of device PM1 in part B flows entirely through the branch in which M2 is located, i.e. im2=i1, device NM1 will still be in the linear region, so that the output signal OUT will remain at a high level all the time. That is, the output signal OUT cannot be inverted to a low level no matter how low the gate potential of M2 is. Thus, the comparator cannot judge whether the system has over-current charging or not, and further cannot effectively protect the system. The above case also only considers the mismatch of current between current mirrors due to the threshold voltage mismatch (mismatch), and does not consider the mismatch of device-to-device dimensions. Therefore, the circuit structure is used for realizing the charging overcurrent protection function, and after the chip is produced in batch, the problem is that part of the chip charging overcurrent protection function is invalid, the product yield is greatly reduced, and the economy is not achieved.

Because of this disadvantage, the circuit of this structure is not stable and safe in commercial products and is not feasible.

And then looking at the defects of the second class of detection circuits for realizing the charging overcurrent protection. The second type of circuit has the characteristic of simple structure, can easily realize the charge over-protection function, but has the defects and limitations that the process deviation of detecting the threshold voltage is large, the detection precision is poor, the specification serialization of different charge over-current threshold values can not be met, and the like. For this reason, firstly, the threshold voltage of the nmos device is used as the reference voltage to judge, and the threshold voltage vth of the device is related to the deviation caused by the process, so that the charging overcurrent protection points of the chips are different, and the precision is difficult to be ensured. Secondly, the threshold value of the device is fixed, a series of different charging overcurrent protection points are difficult to repair and regulate through a simple repair and regulation circuit so as to meet the actual needs of different specifications, and the applicability of the circuit structure is greatly limited due to the defects in the two aspects and cannot be adopted in mass commercial production.

From the two existing charge overcurrent detection implementation modes, the technology is imperfect, and has obvious defects, namely 1, the requirement on device matching design is high. 2. The common mode input voltage of the required comparator is about 0V when in operation, and a simple circuit can obtain high gain. 3. The detection accuracy of the charging overcurrent threshold is difficult to guarantee. 4. The charging overcurrent protection points with different specifications cannot be obtained through simple trimming.

The invention aims to provide a novel charging overcurrent protection detection implementation mode, which has the following advantages compared with the prior art:

A. the matching design requirements between devices are not so strict, and the product yield after the chip mass production can be effectively improved; B. the common mode input voltage of the comparator is more than 0V when in operation, so that the high-gain comparator can be easily realized; C. the requirements on the process are not high, the universality of the circuit is better, and the circuit can be realized by adopting a common process. D. The charging overcurrent protection points with different specifications can be obtained easily through the trimming circuit. E. Can meet the requirement of high precision.

In the embodiment shown in fig. 4, the invention provides a battery charging overcurrent protection circuit, which comprises P-type field effect transistors PM1, PM4 and PM5; n-type field effect transistors NM3, NM4 and NM5;

It is known that during charging, the voltage at the CS terminal is negative, and whether charging over-current protection occurs is detected, that is, whether the CS voltage is lower than a certain negative voltage is detected, if a common comparator is directly used to implement the charging over-current protection, the system needs a circuit capable of obtaining negative voltages with different values through trimming, so that one end of the comparator is connected to a required negative voltage, and the other end of the comparator is connected to the CS terminal, and the charging over-current detection and protection function can be implemented. Therefore, the invention provides a simple, effective and economic circuit structure for realizing negative voltage detection, thereby effectively realizing charging overcurrent detection and protection. The specific implementation principle is as follows: the negative input end of the comparator is connected with a fixed positive voltage (different voltage values can be obtained through trim), the positive input end is connected with the CS end through a level shift circuit (level_shift), so that after the voltage sampled by the CS end is subjected to potential lifting, a positive voltage value is obtained, the obtained positive voltage value is used for being compared with the potential of the negative end of the comparator, the direct comparison by negative pressure is avoided, and the potential of the positive input end of the comparator is as follows:

vp＝Vcs+Vsg4-Vgs5＝Vcs+(Vsg4-Vgs5) (5)

wherein vp is the differential pair positive input terminal voltage; vcs is the voltage value of the CS terminal and is a negative value; vsg4 is the source gate voltage value of the device PM 4; vgs5 is the gate-source voltage value of the nmos device; the magnitude of Vsg4 and Vgs5 are related to the respective aspect ratio and current flowing. In an actual circuit, the specific sizes of Vsg4 and Vgs5 can be set according to the requirement, then a proper Vsg4-Vgs5 difference value is obtained, and the negative voltage of the CS end is shifted to an appropriate positive voltage value, so that direct negative voltage comparison can be avoided.

I ₅ ＝(1/2)*μ _n C _ox (W/L)(V _gs5 -V _thn ) ² (6)

Obtaining

I ₄ ＝(1/2)*μ _p C _ox (W/L)(|V _gs4 |-|V _thp |) ² (8)

Obtaining

Bringing Vsg4 and Vgs5 into equation (5), respectively, yields:

and (3) further finishing to obtain:

it can be seen from the above formula that the voltage vp after level shifting of Vcs is related to the Vthp-Vthn difference, and the two values of Vthp-Vthn are related to the process, and the values of Vthp and Vthn are different under different process corners, that is, the voltage vp obtained after level shifting is related to the process, so that the charging overcurrent protection point is consistent for a chip with a certain specification, that is, the corresponding Vcs value is consistent, so that the vp value corresponding to a chip with the same specification is inconsistent, however, the problem can be solved by trimming the circuit at the time of testing. The trimming circuit is also an original design and is used for adjusting the error difference caused by the process, and the deviation generated by the process corner is eliminated by trimming to obtain different vn values so as to obtain a consistent charging overcurrent protection point. In some simplified embodiments, the trimming circuit can be directly replaced by an equivalent adjustable resistor, so that the technical effect of reducing the cost can be achieved.

In addition, the voltage of vp and vn nodes is set to be more than 0V on the circuit design, and the common mode input voltage is positive when the comparator works. Therefore, a more conventional comparator circuit is adopted, and special processing is not needed for the interior and process matching of the comparator, so that higher voltage gain can be obtained, and the accuracy of detecting the threshold voltage of the charging overcurrent is improved.

In summary, the circuit has higher applicability, has low technical requirements and comparator design requirements, and can ensure the precision by simply trimming the circuit.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the statement "comprising … …" or "comprising … …" does not exclude the presence of additional elements in a process, method, article or terminal device comprising the element. Further, herein, "greater than," "less than," "exceeding," and the like are understood to not include the present number; "above", "below", "within" and the like are understood to include this number.

It will be appreciated by those skilled in the art that the various embodiments described above may be provided as methods, apparatus, or computer program products. These embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. All or part of the steps in the methods according to the above embodiments may be implemented by a program for instructing related hardware, and the program may be stored in a storage medium readable by a computer device, for performing all or part of the steps in the methods according to the above embodiments. The computer device includes, but is not limited to: personal computers, servers, general purpose computers, special purpose computers, network devices, embedded devices, programmable devices, intelligent mobile terminals, intelligent home devices, wearable intelligent devices, vehicle-mounted intelligent devices and the like; the storage medium includes, but is not limited to: RAM, ROM, magnetic disk, magnetic tape, optical disk, flash memory, usb disk, removable hard disk, memory card, memory stick, web server storage, web cloud storage, etc.

The embodiments described above are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a computer device to produce a machine, such that the instructions, which execute via the processor of the computer device, create means for implementing the functions specified in the flowchart block or blocks and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer device-readable memory that can direct a computer device to function in a particular manner, such that the instructions stored in the computer device-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer apparatus to cause a series of operational steps to be performed on the computer apparatus to produce a computer implemented process such that the instructions which execute on the computer apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While the embodiments have been described above, other variations and modifications will occur to those skilled in the art once the basic inventive concepts are known, and it is therefore intended that the foregoing description and drawings illustrate only embodiments of the invention and not limit the scope of the invention, and it is therefore intended that the invention not be limited to the specific embodiments described, but that the invention may be practiced with their equivalent structures or with their equivalent processes or with their use directly or indirectly in other related fields.

Claims

1. The battery charging overcurrent protection circuit is characterized by comprising P-type field effect transistors PM1, PM4 and PM5; n-type field effect transistors NM3, NM4 and NM5;

the source electrode of PM1 is connected with VDD, the grid electrode is connected with bias, and the drain electrode is connected with the grid electrode of NM5; the drain electrode of the PM1 is also connected with the source electrode of the PM4, and the grid electrode of the PM4 is connected with the CS and the drain electrode is grounded; the drain electrode of NM5 is connected with VDD, and the source electrode is connected with the drain electrode of NM 3; the grid electrode of the NM3 is connected with the grid electrode of the NM4, and the source electrode is grounded; the bias is also connected with the gate of PM5, the source of PM5 is connected with VDD, the drain is connected with the drain of NM4, and the drain of PM5 is also connected with the gate of NM 4; the source electrode of the NM4 is grounded; wherein VDD is the supply voltage and bias is the bias voltage;