CN107133014B - Broadband spectrum monitoring system and method for generating high-speed pseudo-random sequence signal - Google Patents
Broadband spectrum monitoring system and method for generating high-speed pseudo-random sequence signal Download PDFInfo
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Abstract
The invention discloses a broadband frequency spectrum monitoring system and a method for generating a high-speed pseudo-random sequence signal, which comprise a signal pre-conditioning module, a power divider, a mixer, a low-pass filter, an intermediate frequency amplifier, an FPGA module and a reconstruction algorithm device, wherein the output end of the signal pre-conditioning module is connected with the input end of the power divider, the FPGA module generates the high-speed pseudo-random sequence signal and signals output by four paths of output ends of the power divider are input to the input end of the mixer, the four paths of output ends of the mixer are connected with the input end of the intermediate frequency amplifier through the low-pass filter, the four paths of output ends of the intermediate frequency amplifier are connected with the FPGA module, and the FPGA module is connected with the reconstruction algorithm device.
Description
Technical Field
The invention relates to a broadband frequency spectrum monitoring system and a method for generating a high-speed pseudo-random sequence signal by the broadband frequency spectrum monitoring system.
Background
The nyquist sampling theorem shows that: analog to Digital converters, the sampling frequency of the ADC must be greater than or equal to twice the highest frequency of the signal in order to reconstruct the original Analog signal from discrete sampled values without distortion. In the face of increasingly large signal monitoring bandwidth, a broadband spectrum monitoring system designed by adopting a traditional Nyquist sampling method can greatly increase the hardware cost of sampling, and meanwhile, the mass data volume generated by sampling can bring huge pressure to the storage, transmission and operation of data. The Modulated Wideband Converter MWC based on the compressive sensing theory can carry out blind sampling on a Wideband sparse signal at a sampling rate far lower than the Nyquist rate, reconstructs an original signal at a high probability through a reconstruction algorithm, and has a wide application prospect in the design of a Wideband spectrum monitoring system.
The schematic block diagram of a modulated wideband converter is shown in fig. 1, where the received frequency range is first scaled to 0, fnyq/2]The broadband sparse signal x (t) is divided into m paths of same signals fnyqRepresenting a wideband sparse signalThe Nyquist sampling rate of the maximum bandwidth signal enters m parallel channels simultaneously; then respectively has a period T with m pathspPseudo-random sequence p ofi(t) performing a mixing process. Wherein the code rate of the pseudo-random sequence cannot be less than fnyq(ii) a Then each pass through a cut-off frequency of 1/(2T)s) The ideal low-pass filter h (t); finally with fs＝1/TsThe filtered signal is sampled at a sampling rate of (a) to obtain a sub-nyquist sampling sequence yi[n]The original signal x (t) is recovered by a reconstruction algorithm.
However, since the modulation wideband converter theory has many limitations on hardware, especially when processing ultra-wideband sparse signals, the code rate of the pseudo-random sequence is required to be not less than the nyquist sampling rate of the signal. The generation of high-speed pseudo-random sequences is a difficult problem, and the design and implementation of the modulation broadband converter are greatly limited.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a broadband frequency spectrum monitoring system and a method for generating a high-speed pseudo-random sequence signal by using the same.
In order to achieve the purpose, the invention provides the following technical scheme:
the broadband frequency spectrum monitoring system comprises a signal pre-conditioning module, a power divider, a mixer, a low-pass filter, an intermediate frequency amplifier, an FPGA module and a reconstruction algorithm device, wherein the output end of the signal pre-conditioning module is connected with the input end of the power divider, the FPGA module generates high-speed pseudo-random sequence signals and signals output by four paths of output ends of the power divider are input to the input end of the mixer, four paths of output ends of the mixer are connected with the input end of the intermediate frequency amplifier through the low-pass filter, four paths of output ends of the intermediate frequency amplifier are connected with the FPGA module, and the FPGA module is connected with the reconstruction algorithm device.
The FPGA module comprises an ADC module and a GTX module, wherein the GTX module in the FPGA module generates high-speed pseudo-random sequence signals and signals output by four paths of output ends of the power divider are input to the input end of the frequency mixer, the four paths of input ends of the intermediate frequency amplifier are connected with the ADC module in the FPGA module, and the GTX module comprises a data transmission bus and a parallel-serial output module at the sending end of the GTX module.
The signal pre-conditioning module comprises a low noise amplifier, an adjustable attenuator and an amplifier module, wherein the low noise amplifier is connected with the amplifier module through the adjustable attenuator, and the output end of the amplifier module in the signal pre-conditioning module is connected with the input end of the power divider.
The high-speed pseudo-random sequence signal is generated by adopting a RocktIO high-speed serial data transmission technology.
The mixer is designed using an ADL5801 chip.
The intermediate frequency amplifier is designed by using an OPA847 chip.
The low noise amplifier is designed by adopting a BGB707L7ESD chip.
A method of generating a high speed pseudorandom sequence signal, the method comprising the steps of:
1. randomly generating a matrix with 4 rows and 127 columns by using MATLAB software, and corresponding each row of random numbers of the matrix to a pseudorandom sequence in a period;
2. changing-1 in the matrix into 0 to form a pseudo random code, and storing the pseudo random code in a RAM block of the FPGA;
3. and starting the GTX module, forming a group of 16 pseudo random codes in the RAM block, sending the pseudo random codes to a data transmission bus of the GTX module in parallel to obtain parallel data, and sending the parallel data out in a serial mode through a parallel-parallel serial-out module of a sending end of the GTX module to obtain a high-speed pseudo random sequence signal.
Compared with the prior art, the invention has the beneficial effects that:
firstly, a signal pre-conditioning module, a power divider, a mixer, a low-pass filter, an intermediate frequency amplifier and an FPGA module are designed on a board card, so that noise interference is reduced, and the stability of a system is improved;
secondly, designing a high-speed pseudo-random sequence generator by utilizing a GTX module in the FPGA to meet the requirement of a modulation broadband converter system for processing broadband sparse signals;
thirdly, a four-channel modulation broadband converter hardware system capable of processing the sparse multi-band signal of 50MHz-500MHz is designed, and the frequency spectrum of the original signal can be effectively reconstructed.
Description of the drawings:
FIG. 1 is a functional block diagram of a modulated broadband converter;
FIG. 2 is a block diagram of the system of the present invention;
FIG. 3 is a circuit schematic of a low noise amplifier;
FIG. 4 is a circuit schematic of the adjustable attenuator;
FIG. 5 is a circuit schematic of an amplifier module;
FIG. 6 is a schematic circuit diagram of the power divider;
FIG. 7 is a circuit schematic of a mixer;
fig. 8 is a circuit schematic of the low-pass filter 6;
FIG. 9 is a frequency characteristic of a low pass filter circuit;
FIG. 10 is a circuit schematic of an intermediate frequency amplifier;
FIG. 11 is a block diagram of a clock network for a high speed pseudo random sequence generator;
FIG. 12 is a high speed pseudorandom sequence time domain waveform diagram;
FIG. 13 is a time domain spectrogram of a high-speed pseudorandom sequence;
FIG. 14 is a measured waveform of a 100MHz sinusoidal signal after MWC mixing and filtering;
FIG. 15 is a spectrum of a sample sequence of a 100MHz sinusoidal signal after being under-sampled by an MWC;
FIG. 16 is a spectral reconstruction of a 100MHz sinusoidal signal after MWC undersampling;
fig. 17 is a measured waveform of a QPSK signal after MWC mixing and filtering;
fig. 18 is a spectrum of a sampled sequence of a QPSK signal after MWC undersampling;
fig. 19 is a spectral reconstruction of a QPSK signal after MWC undersampling;
fig. 20 is a measured waveform of a single carrier signal + QPSK signal after MWC mixing and filtering;
FIG. 21 is a sampled sequence spectrum of a single carrier signal + QPSK signal after MWC undersampling;
fig. 22 is a MWC undersampled spectral reconstruction of a single carrier + QPSK signal.
Detailed Description
As shown in fig. 2, the broadband spectrum monitoring system includes a signal preconditioning module 1, a power divider 4, a mixer 5, a low-pass filter 6, an intermediate frequency amplifier 7, an FPGA module 2, and a reconstruction algorithm 3, wherein an output end of the signal preconditioning module 1 is connected to an input end of the power divider 4, signals generated by the FPGA module 2 and outputted by four output ends of the power divider 4 are all inputted to an input end of the mixer 5, four output ends of the mixer 5 are all connected to an input end of the intermediate frequency amplifier 7 through the low-pass filter 6, four output ends of the intermediate frequency amplifier 7 are connected to the FPGA module 2, and the FPGA module 2 is connected to the reconstruction algorithm 3.
As shown in fig. 2, the FPGA module 2 includes an ADC module 22 and a GTX module 21, the GTX module 21 in the FPGA module generates a high-speed pseudo random sequence signal and signals output from four output terminals of the power divider 4 are input to an input terminal of the mixer 5, four input terminals of the intermediate frequency amplifier 7 are connected to the ADC module 22 in the FPGA module, and the GTX module 21 includes a data transmission bus and a parallel-serial output module at a GTX module transmitting terminal.
As shown in fig. 2, the signal pre-conditioning module 1 includes a low noise amplifier 11, an adjustable attenuator 12, and an amplifier module 13, where the low noise amplifier 11 is connected to the amplifier module 13 through the adjustable attenuator 12, and an output end of the amplifier module 13 in the signal pre-conditioning module is connected to an input end of the power divider 4.
The high-speed pseudo-random sequence signal is generated by adopting a RocktIO high-speed serial data transmission technology.
The low noise amplifier 11 is designed by using a BGB707L7ESD chip, as shown in fig. 3, the chip U1 is a BGB707L7 ESD. LNA _1N is an input that receives a wideband signal from an antenna. LNA _ OUT is an output end connected to the rear end adjustable attenuator 12.
As shown in FIG. 4, the chip U9-A is model DAT-31R5-PP + for the circuit schematic of the adjustable attenuator 12. The BE terminal is an enable port, and the output port of the adjustable attenuator 12 is ATT _ OUT.
As shown in fig. 5, a schematic circuit diagram of the amplifier module 13 is shown, wherein the chip U23 is model GVA-63 +. The amplifying output end is GVA _ OUT.
As shown in fig. 6, the circuit schematic diagram of the power divider 4 is shown, in which U17, U24, and U25 are three TCP-2-33W + chips of the same model. An RF0 port, an RF1 port, an RF2 port and an RF3 port are respectively connected with each mixer.
As shown in fig. 7, the mixer 5 is designed by using an ADL5801 chip, and the circuit schematic of the mixer 5 is shown. The model number of the chip U10 is ADL 5801. LO _ TXN1 and LO _ TXP1 are mixer differential inputs that come from high speed pseudo-random sequences generated by the GTX modules of the FPGA. IFOP _1 and IFON _1 are intermediate frequency output ends of the mixers and are connected with low-pass filters at the rear ends.
As shown in fig. 8, the low-pass filter 6 has a circuit diagram with a cutoff frequency of 33 MHz. The inductance value L1 ═ L4 ═ L3 ═ L6 ═ 606.82nH, and the inductance value L2 ═ L5 ═ 648.34 nH. The capacitance value C1 ═ C2 ═ C3 ═ C442 pF. FIG. 9 is a frequency characteristic of a low pass filter circuit;
as shown in fig. 10, the circuit schematic of the intermediate frequency amplifier, the intermediate frequency amplifier 7 is designed by using an OPA847 chip. Wherein IFAP _1 and IFAN _1 are low-frequency differential signals output after being filtered by the low-pass filter, and the IF1_ OUT port is a single-ended signal output by the intermediate-frequency amplifier. The differential gain is 9.06, the bandwidth is 430MHz, the baseband signal in 33MHz can be effectively amplified, and the common mode noise of the signal is reduced.
Method for generating a high speed pseudo random sequence signal said method comprising the steps of:
1. randomly generating a matrix with 4 rows and 127 columns by using MATLAB software, and corresponding each row of random numbers of the matrix to a pseudorandom sequence in a period;
2. changing-1 in the matrix into 0 to form a pseudo random code, and storing the pseudo random code in a RAM block of the FPGA;
3. and starting the GTX module, forming a group of 16 pseudo random codes in the RAM block, sending the pseudo random codes to a data transmission bus of the GTX module in parallel to obtain parallel data, and sending the parallel data out in a serial mode through a parallel-parallel serial-out module of a sending end of the GTX module to obtain a high-speed pseudo random sequence signal.
A RocketIO high-speed serial data transmission technique is employed to generate the high-speed pseudorandom sequence. The high-speed serial data Transceiver GTX (GTX) of the Xilinx FPGA has a plurality of data transmission channels, can meet the requirement of multi-channel mixing of a modulation broadband converter, and has extremely high transmission rate. In the XilinxVirtex5 series FPGA, the serial transmission rate can be set to 150Mb/s to 6.5Gb/s, and the highest rate can be achieved to be far higher than the Nyquist rate of signals in the system. The multi-path pseudo-random sequences generated by multiple groups of GTXs in the FPGA are easy to keep consistent.
In the hardware implementation of the modulation broadband converter, the sampling clock of the ADC and the reference clock for generating the pseudo-random sequence need to be kept synchronous or homologous to each other, so that the sampling data and the pseudo-random code can be strictly correlated to each other, thereby realizing accurate reconstruction of the original signal. Therefore, generating a 1.6Gb/s pseudorandom sequence with GTX requires providing the GTX with a 100MHz reference clock external to the FPGA. The clock module of the ADC generates a 20MHz clock signal to the frequency synthesizer 844003-01. The frequency synthesizer generates a 100MHz low voltage differential signal as the external reference clock for the GTX. A block diagram of a clock network for a high speed pseudorandom sequence generator is shown in fig. 11.
MATLAB software is used for randomly generating 4 rows and 127 columns of matrixes, and the equal probability randomly takes a value of +/-1. Each row of random numbers of the matrix corresponds to a pseudo-random sequence within a period. The-1 in the matrix is changed to 0 and loaded into the RAM block of the FPGA. After GTX starts, every 16 pseudo random codes In the RAM block are taken as a group and are sent to a data transmission bus TXDATA In Parallel, then Parallel data are sent Out In a Serial mode through a Parallel-Parallel Serial-Out module (PISO) module of a GTX sending end based on a high-speed Serial clock with good internal frequency multiplication of GTX, and a high-speed differential pseudo random sequence is obtained.
The time domain waveform and the frequency spectrum of the high-speed pseudorandom sequence are observed by an oscilloscope, and the code rate is 1.6Gb/s as shown in figures 12 and 13.
The broadband spectrum monitoring system is tested by respectively utilizing the single carrier frequency signal and the QPSK signal, and then the power synthesizer is utilized to synthesize the single carrier frequency signal and the QPSK signal into a sparse dual-band signal to verify the sensing capability of a hardware system of the modulation broadband converter on the broadband spectrum.
First, single carrier frequency signal testing. A signal source is used for generating a single-tone signal of 100MHz, the single-tone signal is divided into four paths by a power divider 4, the four paths of single-tone signal are mixed with a periodic pseudorandom sequence and are subjected to a low-pass filter, four paths of intermediate frequency signals are obtained, and the time domain waveforms of the four paths of single-tone signals are observed by an oscilloscope as shown in fig. 14. Analyzing the spectrum of the four sampling sequences is shown in fig. 15, the 100MHz frequency points are shifted many times, and a plurality of single-tone frequency points appear in the baseband. The recovery of the spectrum of the input signal by the reconstruction algorithm is shown in fig. 16. As can be seen from the results in fig. 16, the spectrum of the single carrier signal of 100MHz was successfully detected.
Second, QPSK signal testing. A QPSK signal with a carrier frequency of 400MHz and a bandwidth of 2MHz is generated by using a signal source, a filtered intermediate frequency signal is obtained by a low pass filter of the system, and four paths of signals observed by an oscilloscope are shown in fig. 17. After four sampling sequences are obtained, the spectrum of the four sampling sequences is analyzed as shown in fig. 18, after the QPSK signal is mixed with the periodic pseudorandom sequence, the spectrum of the signal is moved to the whole frequency band, and the spectrum of each sampling sequence is composed of a plurality of frequency bands. Fig. 19 shows the reconstructed signal spectrum, and it can be seen that a QPSK signal with a carrier frequency of 400MHz and a bandwidth of 2MHz is successfully detected.
Third, single carrier + QPSK signal test. And synthesizing the single carrier frequency signals and the QPSK signals of the two experiments into a sparse dual-band signal by using a power synthesizer to serve as an input signal of the system. Four paths of intermediate frequency signals are output by the system, and the actually measured waveforms are shown in figure 20. The frequency spectrum of the four signals sampled by the ADC module 22 is shown in fig. 21, and includes a plurality of single-frequency-point signals in addition to a plurality of band signals. It is shown that the sample sequence contains a mixture of single tone signals and QPSK signals. The spectrum of the finally reconstructed signal is shown in fig. 22, and the spectrum of the mixed signal is successfully recovered.
The sparse multi-band signal reconstruction method can complete reconstruction of sparse multi-band signals, has good spectrum sensing performance, and reduces noise interference and improves system stability by designing the signal pre-conditioning module, the power divider, the mixer, the low-pass filter, the intermediate frequency amplifier and the FPGA module on one board card; designing a high-speed pseudo-random sequence generator by utilizing a GTX module in an FPGA (field programmable gate array), and meeting the requirement of a modulation broadband converter system on processing broadband sparse signals; a four-channel modulation broadband converter hardware system capable of processing 50MHz-500MHz sparse multi-band signals is designed, and the frequency spectrum of an original signal can be effectively reconstructed.
It should be noted that the above list is only one specific embodiment of the present invention. It is obvious that the invention is not limited to the above embodiments, but that many variations are possible. In general, variations thereof that can be derived or suggested directly from the disclosure herein by those of ordinary skill in the art are considered to be within the scope of the present invention.
Claims (6)
1. The broadband frequency spectrum monitoring system is characterized by comprising a signal pre-conditioning module (1), a power divider (4), a frequency mixer (5), a low-pass filter (6), an intermediate frequency amplifier (7), an FPGA module (2) and a reconstruction algorithm device (3), wherein the output end of the signal pre-conditioning module (1) is connected with the input end of the power divider (4), the FPGA module (2) generates a high-speed pseudo-random sequence signal and signals output by four output ends of the power divider (4) are input to the input end of the frequency mixer (5), the four output ends of the frequency mixer (5) are connected with the input end of the intermediate frequency amplifier (7) through the low-pass filter (6), the four output ends of the intermediate frequency amplifier (7) are connected with the FPGA module (2), and the FPGA module (2) is connected with the reconstruction algorithm device (3);
the FPGA module (2) comprises an ADC module (22) and a GTX module (21), wherein the GTX module (21) in the FPGA module generates high-speed pseudo-random sequence signals and signals output by four output ends of the power divider (4) are input to the input end of the mixer (5), four input ends of the intermediate frequency amplifier (7) are connected with the ADC module (22) in the FPGA module, and the GTX module (21) comprises a data transmission bus and a parallel-serial output module at the transmitting end of the GTX module;
the signal pre-conditioning module (1) comprises a low noise amplifier (11), an adjustable attenuator (12) and an amplifier module (13), wherein the low noise amplifier (11) is connected with the amplifier module (13) through the adjustable attenuator (12), and the output end of the amplifier module (13) in the signal pre-conditioning module is connected with the input end of the power divider (4).
2. The wideband spectrum monitoring system of claim 1, wherein the high-speed pseudorandom sequence signal is generated using a rockio high-speed serial data transmission technique.
3. Broadband spectral monitoring system according to claim 1, characterized in that the mixer (5) is designed with an ADL5801 chip.
4. Broadband spectrum monitoring system according to claim 1, characterized in that the intermediate frequency amplifier (7) is designed with OPA847 chip.
5. The broadband spectrum monitoring system according to claim 1, wherein the low noise amplifier (11) is designed with a BGB707L7ESD chip.
6. A method of generating a high-speed pseudo-random sequence signal, based on the wideband spectrum monitoring system of claim 1, the method comprising the steps of:
(1) randomly generating a matrix with 4 rows and 127 columns by using MATLAB software, and corresponding each row of random numbers of the matrix to a pseudorandom sequence in a period;
(2) changing-1 in the matrix into 0 to form a pseudo-random code, and storing the pseudo-random code in an RAM block of the FPGA;
(3) and the GTX module is started, every 16 pseudo random codes in the RAM block are taken as a group and are parallelly sent to a data transmission bus of the GTX module to obtain parallel data, and then the parallel data are sent out in a serial mode through a parallel-parallel serial-out module of a sending end of the GTX module to obtain a high-speed pseudo random sequence signal.
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