CN1025405C - Digital interpolation circuitry - Google Patents
Digital interpolation circuitry Download PDFInfo
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- CN1025405C CN1025405C CN91101483A CN91101483A CN1025405C CN 1025405 C CN1025405 C CN 1025405C CN 91101483 A CN91101483 A CN 91101483A CN 91101483 A CN91101483 A CN 91101483A CN 1025405 C CN1025405 C CN 1025405C
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Abstract
A sampled data interpolator includes a linear interpolator (20,24) coupled in parallel with a nonlinear compensation signal path (22,34). The nonlinearly processed signals and the linearly interpolated signals are summed (36) to produce interpolated samples. The nonlinear compensation signal path includes a finite impulse response filter (22) having tap weights conforming to a sinc function, and a weighting circuit for scaling filtered samples by a normalized sinc function.
Description
The present invention relates to be used for producing between for example circuit of the signal value between the given value of expansion or compressed video image.
In the expansion and compressibility of vision signal, need carry out time conversion for discrete-time signal.Yet, for for Y(m)=X(α m) this conversion realizes the general conversion of discrete time axle, a subject matter has occurred: i.e. input signal X(α m) for the not definition of non integer value of concordance list (α m).Interpolation is exactly a kind of method that addresses this problem.When output need be at the input sample on having the time index table of undefined input value, must provide interpolate value.About the interpolation problem a large amount of documents is arranged, what time merits attention: a) use with function S in(x but have)/interpolation of a large amount of input samples of X weighting provides accurate result, but in order to realize user's set, cost is too high; B) sampling and maintenance interpolation are easy to realize most, but performance is generally relatively poor; C) linear interpolation more easily realizes and provides the performance that is better than sampling and keeps method, but along with the raising decay of signal frequency is also increasing; D) the higher-order interpolation provides the performance that is better than linear interpolation, but presents non-linear.
T.J.Christopher is in U.S. Patent No. 4,694, described a kind of non-relatively multiple interpolater in 414, and this interpolater presents more accurate characteristic, and by with 2 linear interpolaters with phase compensation filter is in parallel is achieved.The transfer function H(z of compensating filter) as follows:
H(z)=-1+z
-1+z
-2-z
-3(1)
Wherein: " z " is traditional converted variable, and its index is corresponding to the number in sampling interval.Should be noted that weight coefficient is positive 1 or negative 1.The amplitude characteristic A(φ of filter) as follows:
A(φ)=2cos(φ/2)-2cos(3φ/2) (2)
Wherein: φ represents frequency, is unit with the radian per second.
Compensating filter is connected with the gain unit cascade, and this gain unit is being designed corresponding to system to produce on those possible positions of interpolate value, programmes with the yield value of estimating.These gain benefit values obtain by the response error that calculates under the signal specific frequency.Because these yield values are not the functions of frequency, so the Christopher system contains residual error.
The present invention is devoted to simple relatively generally interpolating circuit, and this circuit has basic accurate response characteristic for the signal of all frequencies (up to the nyquist sampling limit of system).
The present invention is a signal interpolation device, and it comprises linear interpolation and the compensating filter that is connected in parallel.Compensating filter be comprise sectionally weighting, one by one according to correction function Sin(x)/ limited exciter response filter that X revises.
Fig. 1 is the oscillogram that sinusoidal sampling function is shown;
Fig. 2 can be used for the diagrammatic representation embodiment of the invention, the normalization SIN function;
Fig. 3 is the block diagram of enforcement interpolater of the present invention system;
Fig. 4 can be used to realize block diagram Fig. 3 median filter 22, compensating filter.
As everyone knows, desirable interpolation can be by obtaining the function S convolution of input signal with the exciter response of expression ideal low-pass filter.For continuous signal, function S is defined as:
S(t)=Sin(2πβt)/2πβt (3)
Wherein: β equals nyquist frequency, and, be the function definition of equation (3) SIN function.Function S (t) is shown in Fig. 1.Corresponding to the discrete time interpolate value of special time, can utilize S(t according to discrete time or sampled signal) and sampled signal g(Tn) convolution calculate.That is to say, for the interpolating sampling value g(to of sampling time to), can be according to g(Tn) * calculate in Sn(to) the sum of products, wherein, Sn(to) to anti-in the discrete time form of function S, and following providing:
Sn(t)=Sin(2πβ(t-nT))/(2πβ(t-nT)) (4)
In more detail, following providing interpolate value g(to):
g(to)=
{g(Tn)×Sn(to)}(5)
Yet should be noted that it is unpractiaca calculating for all designated values.
In order in attainable hardware, to realize this function, used following constraints.
1) the numerical limitations of the interpolate value between two sampled points for example: N=64) to N(;
2) in calculating, only utilize to calculate interpolate value that before M sampling and afterwards M sampling.In the embodiment shown, M equals 4, adds up to 8 sampling like this and is used among each calculating.
Sampling function Sn(t) be divided into linear segment and non-linear partial.In more detail, these are:
S
0(t)=F
0(t)+(1-t/T) (6)
S
1(t)=F
1(t)+t/T (7)
And, Sn(t)=Fn(t), for except 0 and 1 n value
Function F n(t) be further defined as:
F
0(t)=F
1(t)=K
0F(t) (8)
F
-1(t)=F
2(t)=K
1F(t) (9)
F
-2(t)=F
3(t)=K
2F(t) (10)
F
-3(t)=F
4(t)=K
3F(t) (11)
And K
0=S
0(T/2)-0.5 (12)
K
1=S
1(T/2)-0.5 (13)
Kn is defined as:
Kn=Sn(T/2) (14)
(t) is defined as function F:
F(t)={S
-1(t)+S
2(t)}/{2S
2(T/2)} (15)
Independent variable t in equation 15 is corresponding to the time location between the input sample point, and on this time location, interpolate value is calculated, and the item S in the equation 15
-1And S
2Consistent with equation 4 defined SIN function.For example, suppose the point that will calculate interpolate value between continuous sampling Sa and Sb, and with the sampling Sa that at first occurs at a distance of (R/N) T.With the independent variable t in (1-R/N) T substitution equation 15, (R/N) fractional part of T definition sampling period T.Equaling 64 F(t for N) value is shown in Figure 2.
With equation 6-14 substitution equation 5, obtain:
g(t
0)=(1-R/N)g(0)+R/Ng(T)+F(t
0)·{K
3·g(-3T)+k
2·g(-2T)+k
1·g(-T)+k
0·g(0)+k
1·g(T)+k2·g(2T)+k
3·g(3T)+k
4·g(4T)} (16)
Preceding two corresponding to linear interpolation.The back those corresponding to multiply by variable gain function F(t) limited exciter response filter function.The representative of the value of Kn is added to each sampling g(nT) on weight coefficient.The table I illustrates each Kn value for the filter of eight segmentations.
The table I
k
-3=-2/(7π)=-0.0909
k
-2=2/(5π)=0.1273
k
-1=-2/(3π)=-0.2122
k
0=2/π-0.5=0.1366
k
1=2/π-0.5=0.1366
k
2=-2/(3π)=-0.2122
k
3=2/(5π)=0.1273
k
4=-2/(7π)=-0.0909
Interpolation system is shown in Fig. 3.In this embodiment, it is in the environment of vision signal grating converter, in this converter, the wide-screen image information of for example having compressed is reformulated, so that reproduce wide-screen image.Suppose that each row video information comprises the left side bar information of having compressed, the central information of slightly expansion and the right bar information of having compressed.In this example, interpolater has been expanded left and right edge strip information and has been compressed central information, provides the horizontal information of non-compression/extension capable for being used for the wide screen display unit.
In Fig. 3, the video information of compression/extension is added on the data input pin that is coupled on the data buffer 10.Data buffer 10 comprises Signal Separation switch 12, two horizontal line buffer storages 14 and 16 and multicircuit switch 18.Data buffer is controlled by control-signals generator 38 so that in input data-storing to a buffer storage, meanwhile, from second buffer storage data (information row of storage before the expression) is offered interpolation circuit.Two buffer storages alternately receive and dateout.The clock frequency that receives memory is the frequency of occurrences of input sample, and the clock frequency of output memory is determined by interpolating function.In fact, the output clock frequency can be consistent with input clock frequency, but be operated in/stopped under the mode.
Similar data buffer 44 is coupled on the output of interpolater,, and on output " OUT ", provides the interpolating sampling of constant frequency so that be received in an interpolating sampling on the frequency.
Provide control by counter 40 and read-only memory 42 to whole system, counter and read-only memory provide control signal for clock control generator 38, non-linear partial for interpolater provides F(t) value, and provide R/N value for the linear segment of interpolater.On the starting point of every between-line spacing, horizontal-drive signal HORIZ resets to predetermined value (for example, zero) to counter 40.After this, the cycle of counter 40 beginning counting clock signals (4fsc), this clock signal and input data signal synchronously and its frequency resemble at least import the data frequency high.Each count value that counter provided is corresponding to the known location on the video information row.The count value that counter 40 is provided is coupled on the read-only memory (ROM) 42 as address value.Each address location for this read-only memory carries out pre-programmed, so that appropriate control signals is provided and provides corresponding to F(t for generator 38) and the appropriate value of R/N.
Actual interpolater comprises: the nonlinear properties path that contains compensating filter 22 and multiplier 34; The linear signal path that contains compensating delay unit 20 and linear interpolation 24; And be used for the add circuit 36 of the signal plus that will handle in two signal paths.Signal from data buffer 10 is coupled on linear and the nonlinear properties path.In the nonlinear properties path, signal filtering in compensating filter 22, this filter is the limited exciter response filter that has corresponding to the symmetrical segmentation coefficient of Kn value.Output signal from filter 22 is coupled on the multiplier 34, in multiplier 34, this output signal is multiply by F(t) value.Consistent with the non-linear partial of equation 16, be coupled on the input of add circuit 36 from the scaled value of multiplier 34, the output of adder 36 is coupled on the data buffer 44.
In linear signal path, input signal is coupled on the delay cell 20, this delay cell affords redress for different processing delay between linear signal and nonlinear properties path.The output of delay cell 20 is coupled on the minuend input of a sampling delay unit 26 and subtracter 28.Delay sampling from delay cell 26 is coupled on the subtrahend input of subtracter 28.Being coupled on the multiplier 30, in multiplier 30, this difference be multiply by the R/N value from subtracter output difference.The sampling of output separately from multiplier 30 and delay cell 26 is coupled on first and second inputs of adder 32.If be sampled as g(1 the now that delay cell 20 is provided), then g(0 is provided now of being provided delay cell 26).The output signal that subtracter 28, multiplier 30 and adder 32 are provided is respectively: (g(1)-g(0)); R/N(g(1)-g(0)); R/N(g(1)-g(0))+g(0).Can become R/Ng(1 to every rearrangement from adder 32 output signals)+g(0) (1-R/N), it is consistent with the linear response part of equation 16.These and be coupled on second input of add circuit 36.
Fig. 4 illustrates the demonstrative circuit that is used to realize compensating filter 22.Because paired sampling comes weighting with identical coefficient, so, earlier these to the weighting again that combines, with minimizing hardware.Illustrating specific filter is eight segmentation filters, yet can utilize the filter greater or less than eight segmentations.
In Fig. 4, input signal is added on seven single sampling delay unit 52-54 of cascade connection.Input signal and inhibit signal from delay cell 64 are coupled on the adder 76 corresponding inputs.From the output of adder 76 be coupled on the multiplier 86, in multiplier 86, this output with multiply by COEFFICIENT K
4To produce sum of products K
4G(4T)+K
4G(-3T), it equals K
4G(4T)+K
-3G(-3T).The sum of products that multiplier 86 is provided is coupled on the adder 90, and adder 90 provides corresponding to that filter output signal in equation 16 brackets.
Inhibit signal from delay cell 52 and 62 is coupled on the adder 74 corresponding inputs, the output of adder 74 is added on the multiplier 84.The signal that adder 74 is provided and in multiplier 84, multiply by COEFFICIENT K
3, to produce sum of products K
3G(3T)+K
3G(-2T), it equals K
3G(3T)+K
-2G(-2T).Output signal from multiplier 84 is coupled on the adder 90.
Inhibit signal from delay cell 54 and 60 similarly is coupled in the combination of adder 72 and multiplier 82, this makes up sum of products K
2G(2T)+K
-1G(T) offer adder 90.Similarly, the inhibit signal from delay cell 56 and 58 is added in the combination of adder 70 and multiplier 80, this makes up sum of products K
1G(T)+K
0G(O) offer adder 90.Adder 90 is added up the output signal that multiplier 80-86 is provided, to produce filter output signal.
Should be known in compensating delay unit 20 among Fig. 3 can obtain be added to signal on the linear interpolation signal of delay cell 56 (for example, from) by suitable delay cell and be removed from filter shown in Figure 4.
In addition, can revise the listed COEFFICIENT K n of table I a little, adopt extremely approximate binary rate to make coefficient, the hardware of short-cut multiplication device is realized.For example, K
1, K
2, K
3And K
4May be respectively 9/64,14/64,8/64 and 6/64, perhaps be respectively 17/128,27/128,17/128 and 12/128.Similarly, can be F(t) value be adjusted to the ratio that equals faint.Like this, multiplier can utilize displacement, add circuit to realize.
Although the present invention describes in the environment that vision signal is handled,, should be known in that it is applicable to any data-signal of having sampled of processing.
Claims (3)
1, a kind of sampled data interpolater is characterized in that:
Be used to receive the input of sampled data input signal;
Be coupled on the described input, be used on its output, providing the linear interpolation (24) of linear interpolation sampling;
Be coupled on the described input, be used to provide limited exciter response filter (22) corresponding to the filtering sampling of compensating signal;
Be coupled on the described filter, be used for utilizing normalized SIN function to convert described compensating signal on its output so that the weighting device (80-86) of the sampling that has converted is provided;
Be coupled on the output of described weighting device and described interpolater, be used for device (36) that the sampling and the described sampling additive combination that has converted of described linear interpolation are got up.
2, according to a kind of sampled data interpolater of claim 1, it is characterized in that: described normalized SIN function corresponding to:
Wherein: d is corresponding to the form of the part of sampling period T, the position of interpolating sampling between two input samples, d
nCorresponding to the normalization position, be typically T/2.
3, according to a kind of sampled data interpolater of claim 1, it is characterized in that: described finite impulse response filter has transfer function H:
H=
kng(nT)
Wherein n is the variable index; T represents the sampling period; G(nT) corresponding to the input sample value; M equals filter to be used for forming a number partly of the input sample number of filtering sampling, and Kn is as follows:
N is the value except that 0 and 1, when n equals 0 and 1:
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/462,367 US5136410A (en) | 1990-01-09 | 1990-01-09 | Optical fiber link control safety system |
US07/493,020 US5018090A (en) | 1990-03-13 | 1990-03-13 | Digital interpolation circuitry |
US493,020 | 1990-03-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1054872A CN1054872A (en) | 1991-09-25 |
CN1025405C true CN1025405C (en) | 1994-07-06 |
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ID=27040311
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CN91101483A Expired - Fee Related CN1025405C (en) | 1990-01-09 | 1991-03-12 | Digital interpolation circuitry |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR950003031B1 (en) * | 1992-03-30 | 1995-03-29 | 주식회사 금성사 | Tv image signal compensating circuit |
CN1067830C (en) * | 1994-09-26 | 2001-06-27 | 华邦电子股份有限公司 | Digital image format converter |
KR100548362B1 (en) * | 2003-06-30 | 2006-02-02 | 엘지전자 주식회사 | High order sampling wave shaping filter |
CN107133014B (en) * | 2017-04-01 | 2021-02-12 | 中国人民解放军国防科技大学 | Broadband spectrum monitoring system and method for generating high-speed pseudo-random sequence signal |
-
1991
- 1991-03-12 CN CN91101483A patent/CN1025405C/en not_active Expired - Fee Related
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