CN107123690A - Solid plasma PIN diode - Google Patents
Solid plasma PIN diode Download PDFInfo
- Publication number
- CN107123690A CN107123690A CN201710313883.5A CN201710313883A CN107123690A CN 107123690 A CN107123690 A CN 107123690A CN 201710313883 A CN201710313883 A CN 201710313883A CN 107123690 A CN107123690 A CN 107123690A
- Authority
- CN
- China
- Prior art keywords
- areas
- areas step
- pin diode
- solid plasma
- soi substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000007787 solid Substances 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 239000000969 carrier Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 30
- 239000000377 silicon dioxide Substances 0.000 description 15
- 238000000034 method Methods 0.000 description 13
- 235000012239 silicon dioxide Nutrition 0.000 description 12
- 238000001259 photo etching Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000005465 channeling Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005281 excited state Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- WABPQHHGFIMREM-AKLPVKDBSA-N lead-210 Chemical compound [210Pb] WABPQHHGFIMREM-AKLPVKDBSA-N 0.000 description 1
- 229910052752 metalloid Inorganic materials 0.000 description 1
- 150000002738 metalloids Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The present invention relates to a kind of solid plasma PIN diode.The device includes SOI substrate (101)；First P areas step (102), the first N areas step (103), the 2nd P areas step (104), the 2nd N areas step (105), the 3rd P areas step (106) and the 3rd N areas step (107), are respectively arranged in SOI substrate (101) and positioned at the both sides of SOI substrate (101)；Wherein, the 2nd P areas step (104) and the 2nd N areas step (105) are located at the downside of the first P areas step (102) and the first N areas step (103) respectively；3rd P areas step (106) and the 3rd N areas step (107) are located at the downside of the 2nd P areas step (104) and the 2nd N areas step (105) respectively.The present invention by preparing multiple step formation multilayer raceway grooves on soi substrates, superposition using high concentration carrier in two raceway grooves causes whole intrinsic region carriers concentration to reach uniformly, so as to improve the power density of horizontal PIN diode, the solid plasma bulk properties of PIN diode is enhanced.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of solid plasma PIN diode.
Background technology
Currently, the electronics and information industry using integrated circuit as core has surmounted traditional work that automobile, oil, steel are representative
Industry turns into the largest industrial sector, the powerful engine and rich foundation stone of digital Age of being marched toward as transformation and pulling conventional industries.Partly lead
Body device as integrated circuit elemental device, in the field such as consumer electronics, computer and peripheral hardware, network service, in intelligence
Mobile phone, tablet personal computer, track traffic, new energy, hybrid vehicle, solid-state illumination, portable medical electronics, intelligence wearing etc. are new
Emerging market, is widely applied.
Horizontal PIN diode is the important semiconductor devices for producing solid state plasma.Found through theoretical research, solid-state etc.
Ion PIN diode is when adding Dc bias, and DC current can form free carrier (electronics and hole) composition on its surface
Solid state plasma, the plasma has metalloid characteristic so that the plasma can receive, radiate and reflect electromagnetism
The microwave transmission characteristic of ripple, its radiation characteristic and surface plasma, concentration and it is distributed closely related.The PIN studied at present
Diode only has individual layer raceway groove, and so when adding Dc bias, the Carrier Profile in intrinsic region can be uneven, intrinsic region
The deeper local carrier concentration of interior depth is lower so that heating region performance degradation in transmission and radiated electromagnetic wave,
And the power density of this diode is low so that the application of this single-groove road PiN diodes is limited by very large.
Therefore, a kind of solid plasma PIN diode how is made come so that carriers distribution in intrinsic region becomes uniform
Just become particularly important.
The content of the invention
Therefore, to solve the technological deficiency and deficiency that prior art is present, the present invention proposes a kind of solid plasma PIN bis-
Pole pipe.
Specifically, a kind of solid plasma PIN diode that one embodiment of the invention is proposed, including：
SOI substrate 101；
First P areas step 102, the first N areas step 103, the 2nd P areas step 104, the 2nd N areas step 105, the 3rd P areas platform
The N areas step 107 of rank 106 and the 3rd, is respectively arranged in the SOI substrate 101 and positioned at the both sides of the SOI substrate 101；Its
In,
2nd P areas step 104 and the 2nd N areas step 105 are located at the first P areas step 102 and institute respectively
State the downside of the first N areas step 103；
3rd P areas step 106 and the 3rd N areas step 107 are located at the 2nd P areas step 104 and institute respectively
State the downside of the 2nd N areas step 105.
In one embodiment of the invention, in addition to isolated material 108, the isolated material 108 is filled in making institute
State the first P areas step 102, the first N areas step 103, the 2nd P areas step 104, the 2nd N areas step 105, institute
State in the groove formed when the 3rd P areas step 106 and the 3rd N areas step 107.
In one embodiment of the invention, in addition to the first lead 109 and the second lead 110；Wherein,
First lead 109 connects the first P areas step 102, the 2nd P areas step 104 and the 3rd P areas step
106；
Second lead 110 connects the first N areas step 103, the 2nd N areas step 105 and the 3rd N areas step
107。
In one embodiment of the invention, the doping type of the SOI substrate 101 is p-type, and doping concentration is 1 × 1014
~9 × 1014cm-3。
In one embodiment of the invention, the thickness of top layer silicon 1003 is 100 μm in the SOI substrate 101.
In one embodiment of the invention, the upper surface of the first P areas step 102 and the first N areas step 103
Distance respectively away from the upper surface of top layer silicon 1003 is 30~100nm；2nd P areas step 104 and the 2nd N areas platform
Distance of the upper surface of rank 105 respectively away from the first P areas step 102 and the upper surface of the first N areas step 103 be 100~
300nm；The upper surface of 3rd P areas step 106 and the 3rd N areas step 107 is away from the 2nd P areas step 104 and institute
The distance for stating the upper surface of the 2nd N areas step 105 is 300~500nm.
In one embodiment of the invention, the first P areas step 102, the first N areas step 103, described second
P areas step 104, the 2nd N areas step 105, the 3rd P areas step 106 and the 3rd N areas step 107 thickness it is equal
For 100nm.
In one embodiment of the invention, the first P areas step 102, the first N areas step 103, described second
P areas step 104, the 2nd N areas step 105, the 3rd P areas step 106 and the 3rd N areas step 107 doping it is dense
Degree is 1 × 1018~5 × 1018cm-3。
In one embodiment of the invention, in addition to passivation layer 111, isolated material 108, first lead are arranged at
109 and the upper surface of second lead 110.
In one embodiment of the invention, the material of the passivation layer 111 is silicon nitride.
PIN diode of the present invention by preparing multiple step formation multilayer raceway grooves on soi substrates, when on contact electrode
During additional forward voltage, the superposition using high concentration carrier in two raceway grooves causes whole intrinsic region carriers concentration
Reach uniformly, so as to improve the power density of horizontal PIN diode, enhance the solid plasma bulk properties of PIN diode.
By the detailed description below with reference to accompanying drawing, other side and feature of the invention becomes obvious.But should know
Road, the accompanying drawing is only the purpose design explained, not as the restriction of the scope of the present invention, because it should refer to
Appended claims.It should also be noted that unless otherwise noted, it is not necessary to scale accompanying drawing, they only try hard to concept
Ground illustrates structure described herein and flow.
Brief description of the drawings
Below in conjunction with accompanying drawing, the embodiment to the present invention is described in detail.
Fig. 1 is a kind of structural representation of solid plasma PIN diode provided in an embodiment of the present invention；
Fig. 2 a- Fig. 2 r are a kind of preparation method schematic diagram of solid plasma PIN diode of the embodiment of the present invention.
Fig. 3 is the structural representation of another solid plasma PIN diode provided in an embodiment of the present invention.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of structural representation of solid plasma PIN diode provided in an embodiment of the present invention.
Solid plasma PIN diode 10 of the present invention includes：
SOI substrate 101；
First P areas step 102, the first N areas step 103, the 2nd P areas step 104, the 2nd N areas step 105, the 3rd P areas platform
The N areas step 107 of rank 106 and the 3rd, is respectively arranged in the SOI substrate 101 and positioned at the both sides of the SOI substrate 101；Its
In,
2nd P areas step 104 and the 2nd N areas step 105 are located at the first P areas step 102 and institute respectively
State the downside of the first N areas step 103；
3rd P areas step 106 and the 3rd N areas step 107 are located at the 2nd P areas step 104 and institute respectively
State the downside of the 2nd N areas step 105.
Alternatively, in addition to isolated material 108, the isolated material 108 be filled in making the first P areas step 102,
First N areas step 103, the 2nd P areas step 104, the 2nd N areas step 105, the 3rd P areas step 106 and
In the groove formed during the 3rd N areas step 107.
Alternatively, in addition to the first lead 109 and the second lead 110；Wherein,
First lead 109 connects the first P areas step 102, the 2nd P areas step 104 and the 3rd P areas step
106；
Second lead 110 connects the first N areas step 103, the 2nd N areas step 105 and the 3rd N areas step
107。
Alternatively, the doping type of the SOI substrate 101 is p-type, and doping concentration is 1 × 1014~9 × 1014cm-3。
Alternatively, the thickness of top layer silicon 1003 is 100 μm in the SOI substrate 101.
Alternatively, the upper surface of the first P areas step 102 and the first N areas step 103 is respectively away from the top layer silicon
The distance of 1003 upper surfaces is 30~100nm；The upper surface of 2nd P areas step 104 and the 2nd N areas step 105 point
The other distance away from the first P areas step 102 and the upper surface of the first N areas step 103 is 100~300nm；3rd P
The upper surface of area's step 106 and the 3rd N areas step 107 is away from the 2nd P areas step (104) and the 2nd N areas step
The distance of 105 upper surfaces is 300~500nm.
Alternatively, the first P areas step 102, the first N areas step 103, the 2nd P areas step 104, described
The thickness of 2nd N areas step 105, the 3rd P areas step 106 and the 3rd N areas step 107 is 100nm.
Alternatively, the first P areas step 102, the first N areas step 103, the 2nd P areas step 104, described
The doping concentration of 2nd N areas step 105, the 3rd P areas step 106 and the 3rd N areas step 107 is 1 × 1018~5
×1018cm-3。
Alternatively, in addition to passivation layer 111, isolated material 108, first lead 109 are arranged at and described second is drawn
The upper surface of line 110.
Alternatively, the material of the passivation layer 111 is silicon nitride.
The conventional solid plasma PIN diode made is current-carrying in individual layer raceway groove, the intrinsic region in excited state
Sub- concentration distribution is uneven with causing radiation characteristic to be deteriorated.Many channeling diodes of the present invention solve intrinsic region carriers point
This problem of cloth inequality, improves the performance of diode.
Embodiment two
Refer to a kind of system for solid plasma PIN diode that Fig. 2 a- Fig. 2 r, Fig. 2 a- Fig. 2 r are the embodiment of the present invention
Preparation Method schematic diagram, the preparation method of other kinds of many raceway groove PIN diodes is similar with this example, comprises the following steps that：
S10, selection SOI substrate.
Fig. 2 a are referred to, the crystal orientation being somebody's turn to do is (100), and the doping type of the SOI substrate 201 is p-type, and doping concentration is
1014cm-3；The thickness of the top layer silicon of SOI substrate 201 is 100 μm.
S20, in described one layer of silicon nitride of SOI substrate surface deposition.
Fig. 2 b are referred to, using chemical vapor deposition (Chemical Vapor Deposition, abbreviation CVD) method,
The deposit silicon nitride layer 202 in SOI substrate 201.
S30, etching SOI substrate formation active area groove.
Fig. 2 c are referred to, active area figure is formed on silicon nitride layer 202 using photoetching process, dry etch process is utilized
In specified location etch-protecting layer silicon nitride layer 202 and top layer silicon so as to form active area groove 203.
S40, active area surrounding planarization process.
Fig. 2 d are referred to, four the week side of boss walls of active area are aoxidized so that the four the week side of boss walls formation oxide layer 204 of active area.
Fig. 2 e are referred to, etch the surrounding sidewall oxide of active area to complete the four of active area using wet-etching technology
The week side of boss wall is planarized,
S50, deposit layer of silicon dioxide.
Fig. 2 f are referred to, layer of silicon dioxide layer 205 is deposited in whole material surface using CVD method.
S60, photoetching silicon dioxide layer.
Fig. 2 g are referred to, P areas figure is formed in silicon dioxide layer 205 using photoetching process, wet-etching technology is utilized
Remove the silicon dioxide layer 205 on P areas figure.
S70, the P areas for forming first layer raceway groove, second layer raceway groove and third layer raceway groove.
Fig. 2 h are referred to, specific practice can be：Using the method for original position doping, in the P areas figure of whole substrate surface
Upper deposit P-type silicon forms the P areas 2063 in the P areas 2061, the P areas 2062 of second layer raceway groove and third layer raceway groove of first layer raceway groove,
The doping concentration in P areas is controlled by controlling gas flow.
S80, planarizing substrate surface.
Fig. 2 i are referred to, specific practice can be：Make P areas surface flattening first with dry etch process, recycle wet
Method etching technics removes the silicon dioxide layer 205 of substrate surface.
S90, the substrate surface deposit layer of silicon dioxide.
Fig. 2 j are referred to, specific practice can be：Using CVD method silicon dioxide layer 207 is deposited in whole material surface.
S100, photoetching silicon dioxide layer.
Fig. 2 k are referred to, N areas figure is formed in silicon dioxide layer 207 using photoetching process；Utilize wet-etching technology
Remove the silicon dioxide layer 207 in N areas.
S110, the N areas for forming first layer raceway groove, second layer raceway groove and third layer raceway groove.
Fig. 2 l are referred to, using the method for original position doping, N-type silicon shape is deposited on the N areas figure on the surface of SOI substrate 201
Into the N areas 2083 in the N areas 2081 of first layer raceway groove, the N areas 2082 of second layer raceway groove and third layer raceway groove, by controlling gas stream
Measure to control the doping concentration in N areas.
S120, planarizing substrate surface.
Fig. 2 m are referred to, make N areas surface flattening first with dry etch process, recycle wet-etching technology to remove whole
The silicon dioxide layer 207 of individual material surface.
S130, substrate surface planarization.
Refer to Fig. 2 n, it is possible to use CMP method, the silicon nitride layer 202 of the substrate surface is removed, so that entirely
Material surface is planarized.
S140, deposit silica.
Fig. 2 o are referred to, one layer of isolated material silica 209 is deposited in whole material surface using CVD method.
S150, impurity activation.
In 950-1150, DEG C annealing 0.5~2 minute makes the impurity activation of ion implanting and promoted miscellaneous in active area
Matter.
S160, in P, N contact zone lithography fair lead.
Fig. 2 p are refer to, the lithography fair lead 210 on silica 209.
S170, formation lead.
Fig. 2 q are refer to, can be in the splash-proofing sputtering metal of fairlead 210, alloying formation metal silicide, and etch away surface
Metal；Again in whole material surface splash-proofing sputtering metal 211, photoetching lead, and lead is connected.
S180, Passivation Treatment, photoetching PAD.
Fig. 2 r are refer to, deposit silicon nitride (SiN) formation passivation layer 212, photoetching PAD can be passed through.Ultimately form solid-state
Plasma PIN diode.
The conventional solid plasma PIN diode made is current-carrying in individual layer raceway groove, the intrinsic region in excited state
Sub- concentration distribution is uneven with causing radiation characteristic to be deteriorated.Many channeling diodes of the present invention solve intrinsic region carriers point
This problem of cloth inequality, improves the performance of diode.
Embodiment three
Fig. 3 is refer to, Fig. 3 is the structural representation of another solid plasma PIN diode provided in an embodiment of the present invention
Figure.The solid plasma PIN diode is made of the preparation method shown in above-described embodiment.Specifically, the solid plasma
PIN diode prepares formation in SOI substrate 301, and the P areas 301 of the raceway groove of PIN diode first, N areas 302, the second raceway groove
P areas 303, the P areas 305 in N areas 304 and triple channel, N areas 306 and the I areas that are laterally positioned between P areas and N areas are respectively positioned on this
In the top layer silicon 3011 of SOI substrate.
In summary, a kind of solid plasma that specific case used herein is provided invention embodiment
The embodiment of PIN diode is set forth, the explanation of above example be only intended to help to understand the present invention method and
Its core concept；Simultaneously for those of ordinary skill in the art, according to the thought of the present invention, in embodiment and should
With will change in scope, in summary, this specification content should not be construed as limiting the invention, of the invention
Protection domain should be defined by appended claim.
Claims (10)
1. a kind of solid plasma PIN diode, it is characterised in that including：
SOI substrate (101)；
First P areas step (102), the first N areas step (103), the 2nd P areas step (104), the 2nd N areas step (105), the 3rd P
Area's step (106) and the 3rd N areas step (107), are respectively arranged in the SOI substrate (101) and positioned at the SOI substrate
(101) both sides；Wherein,
The 2nd P areas step (104) and the 2nd N areas step (105) respectively be located at the first P areas step (102) and
The downside of the first N areas step (103)；
The 3rd P areas step (106) and the 3rd N areas step (107) respectively be located at the 2nd P areas step (104) and
The downside of the 2nd N areas step (105).
2. solid plasma PIN diode according to claim 1, it is characterised in that also including isolated material (108),
The isolated material (108) is filled in making the first P areas step (102), the first N areas step (103), described second
P areas step (104), the 2nd N areas step (105), the 3rd P areas step (106) and the 3rd N areas step (107)
When the groove that is formed in.
3. solid plasma PIN diode according to claim 1, it is characterised in that also including the first lead (109) and
Second lead (110)；Wherein,
First lead (109) connects the first P areas step (102), the 2nd P areas step (104) and the 3rd P areas platform
Rank (106)；
Second lead (110) connects the first N areas step (103), the 2nd N areas step (105) and the 3rd N areas platform
Rank (107).
4. solid plasma PIN diode according to claim 1, it is characterised in that SOI substrate (101) mix
Miscellany type is p-type, and doping concentration is 1 × 1014~9 × 1014cm-3。
5. solid plasma PIN diode according to claim 3, it is characterised in that pushed up in the SOI substrate (101)
The thickness of layer silicon (1003) is 100 μm.
6. solid plasma PIN diode according to claim 3, it is characterised in that the first P areas step (102)
Distance with the upper surface of the first N areas step (103) respectively away from the top layer silicon (1003) upper surface is 30~100nm；
The upper surface of the 2nd P areas step (104) and the 2nd N areas step (105) is respectively away from the first P areas step (102)
Distance with the first N areas step (103) upper surface is 100~300nm；The 3rd P areas step (106) and the described 3rd
Distance of the upper surface of N areas step (107) away from the 2nd P areas step (104) and the 2nd N areas step (105) upper surface
For 300~500nm.
7. solid plasma PIN diode according to claim 1, it is characterised in that the first P areas step (102),
The first N areas step (103), the 2nd P areas step (104), the 2nd N areas step (105), the 3rd P areas platform
The thickness of rank (106) and the 3rd N areas step (107) is 100nm.
8. solid plasma PIN diode according to claim 1, it is characterised in that the first P areas step (102),
The first N areas step (103), the 2nd P areas step (104), the 2nd N areas step (105), the 3rd P areas platform
The doping concentration of rank (106) and the 3rd N areas step (107) is 1 × 1018~5 × 1018cm-3。
9. solid plasma PIN diode according to claim 1, it is characterised in that also including passivation layer (111), if
It is placed in the upper surface of isolated material (108), first lead (109) and second lead (110).
10. solid plasma PIN diode according to claim 9, it is characterised in that the material of the passivation layer (111)
Expect for silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710313883.5A CN107123690B (en) | 2017-05-05 | 2017-05-05 | Solid-state plasma PIN diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710313883.5A CN107123690B (en) | 2017-05-05 | 2017-05-05 | Solid-state plasma PIN diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107123690A true CN107123690A (en) | 2017-09-01 |
| CN107123690B CN107123690B (en) | 2020-01-10 |
Family
ID=59727387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710313883.5A Active CN107123690B (en) | 2017-05-05 | 2017-05-05 | Solid-state plasma PIN diode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107123690B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005093584A (en) * | 2003-09-16 | 2005-04-07 | Matsushita Electric Ind Co Ltd | Manufacturing method of mesa type semiconductor device |
| CN103915511A (en) * | 2012-12-28 | 2014-07-09 | 现代自动车株式会社 | Schottky barrier diode and method of manufacturing the same |
| CN206961836U (en) * | 2017-05-05 | 2018-02-02 | 西安科锐盛创新科技有限公司 | Horizontal PIN diode |
-
2017
- 2017-05-05 CN CN201710313883.5A patent/CN107123690B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005093584A (en) * | 2003-09-16 | 2005-04-07 | Matsushita Electric Ind Co Ltd | Manufacturing method of mesa type semiconductor device |
| CN103915511A (en) * | 2012-12-28 | 2014-07-09 | 现代自动车株式会社 | Schottky barrier diode and method of manufacturing the same |
| CN206961836U (en) * | 2017-05-05 | 2018-02-02 | 西安科锐盛创新科技有限公司 | Horizontal PIN diode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107123690B (en) | 2020-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7670908B2 (en) | Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling | |
| US8502312B2 (en) | Configurations and methods for manufacturing charge balanced devices | |
| US9368614B2 (en) | Flexibly scalable charge balanced vertical semiconductor power devices with a super-junction structure | |
| CN102412140B (en) | Non-uniformity reduction in semiconductor planarization | |
| US8178409B2 (en) | Semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same | |
| US20100015768A1 (en) | Method of fabricating semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer | |
| US10186575B2 (en) | Silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device | |
| CN115020211B (en) | Semiconductor device and manufacturing method thereof | |
| US20120228699A1 (en) | Methods for fabricating transistors including one or more circular trenches | |
| CN106449771B (en) | With SiO2Solid state plasma PiN diode of protective effect and preparation method thereof | |
| US20160149012A1 (en) | Very high aspect ratio contact | |
| CN106785335A (en) | The preparation technology of the Ge base plasma pin diodes of frequency reconfigurable dipole antenna | |
| CN206961836U (en) | Horizontal PIN diode | |
| CN107046163A (en) | Mesa-shaped active area solid plasma diode fabricating method for preparing holographic antenna | |
| CN106784019A (en) | A kind of Ge bases solid state plasma PiN diodes and preparation method thereof | |
| CN107123690A (en) | Solid plasma PIN diode | |
| CN104752334A (en) | Forming method of contact plug | |
| TW201316452A (en) | U-MOS trench profile optimization and etch damage removal using microwaves | |
| CN106876269A (en) | Possesses SiO in dipole antenna2The preparation method of the SPiN diodes of protective layer | |
| CN106653867B (en) | Solid-state plasma PiN diode based on mesa-shaped active region and preparation method thereof | |
| WO2018113454A1 (en) | Preparation method for heterogeneous sige-based plasma pin diode string used for sleeve antenna | |
| US10177141B2 (en) | Preparation method for heterogeneous SiGe based plasma P-I-N diode string for sleeve antenna | |
| CN107068560B (en) | Preparation method based on mesa-shaped active area PIN diode string in restructural loop aerial | |
| TWI642116B (en) | A method of manufacturing a semiconductor device | |
| CN109841515B (en) | Method for manufacturing semiconductor element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |