CN107112301A - 半导体芯片的背侧上的电子元件集成 - Google Patents

半导体芯片的背侧上的电子元件集成 Download PDF

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Publication number
CN107112301A
CN107112301A CN201580051134.9A CN201580051134A CN107112301A CN 107112301 A CN107112301 A CN 107112301A CN 201580051134 A CN201580051134 A CN 201580051134A CN 107112301 A CN107112301 A CN 107112301A
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semiconductor element
electronic component
semiconductor
integrated
semiconductor devices
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V·拉马钱德兰
U·雷
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Qualcomm Inc
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Qualcomm Inc
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Abstract

系统和方法包括带有基板的第一半导体管芯，该基板具有第一侧和与第一侧相对的第二侧。第一电子元件集被集成到第一侧上。第二电子元件集被集成到第二侧上。一个或多个通过基板的穿板通孔被用于将第一电子元件集中的一者或多者与第二电子元件集中的一者或多者耦合。该多个穿板通孔可以是穿硅通孔(TSV)或穿玻通孔(TGV)。第一半导体管芯可用第二半导体管芯来堆叠，其中第一半导体管芯的第一侧或第二侧与第二半导体管芯的有源侧对接。

Description

半导体芯片的背侧上的电子元件集成
公开领域
所公开的实施例涉及管芯的背侧或第二侧上的电子元件集成，该背侧或第二侧与该管芯的有源侧或第一侧相对。示例性方面包括诸如第二侧上的薄膜晶体管、输入/输出晶体管、二极管、无源器件等的电子元件，以及诸如将第一侧连接至第二侧的穿硅通孔(TSV)之类的贯穿通孔。
背景
半导体器件的设计和制造的进步已经导致半导体封装、晶片和管芯/芯片的缩小尺寸。随着对现代计算机系统(尤其在移动处理系统领域中)的处理需要增加，对于在每个半导体芯片上集成大量电子元件有不断增长的需求。因为半导体芯片的有源表面上的有限表面积，电子元件和组件在半导体芯片上的集成、放置和布线提出了公认问题。
例如，常规集成电路设计可使用线焊来将直立安装的芯片或管芯连接至外部电路系统或半导体封装。芯片的电子器件/元件/集成电路组件集成在芯片的有源侧上。线焊要求输入/输出(I/O)连接、焊盘等，它们也形成在芯片的有源侧上，因为例如芯片朝上安装在印刷电路板(PCB)上。这些I/O连接消耗了有源侧上相对大部分的已经有限的表面积。
另一常规集成电路设计选项涉及倒装芯片封装。在倒装芯片中，焊球形成在与有源侧相对的芯片背侧上。金属连接焊盘形成在有源侧上并通过线焊或贯穿通孔作出通过芯片的半导体基板至焊球的连接。作出通过可附连至球栅阵列(BGA)的焊球至外部电路系统的电连接。然而，常规芯片倒装技术还要求在管芯的有源侧上放置I/O连接、至焊球的金属连接焊盘等。除了形成焊球之外，在常规倒装芯片技术中，芯片背侧不被用于集成任何附加组件。
一些常规办法还包括在副管芯或芯片上放置集成电路或片上系统(SoC)的所选组件。例如，第一芯片上的集成电路的I/O端口和/或其他电子元件可被放置在第二芯片上以力图克服对第一芯片上的表面积的限制。然而，此类解决方案引入了涉及芯片间放置和布线的附加挑战，并且这两个芯片之间的互连可引入高性能处理需要可能不能容忍的不期望延迟和低效。
另外，高级芯片设计还可涉及集成在不同电压域和/或其他工作条件中工作的电子元件，并且以上讨论的办法不提供处置具有缩小器件技术的此种设计考虑的有效解决方案。相应地，现有技术中存在对能克服现有解决方案中的至少前述缺点的改善型半导体器件集成技术的需要。
概述
本发明的诸实施例针对用于在半导体管芯背侧上集成电子元件的系统和方法。例如，示例性系统和方法包括带有基板的第一半导体管芯，该基板具有第一侧和与第一侧相对的第二侧。第一集合的电子元件被集成到第一侧上。第二集合的电子元件被集成到第二侧上。一个或多个穿透基板的穿板通孔被用于将第一集合的电子元件中的一者或多者与第二集合的电子元件中的一者或多者耦合。该多个穿板通孔可以是穿硅通孔(TSV)或穿玻通孔(TGV)。第一半导体管芯可与第二半导体管芯相堆叠，其中第一半导体管芯的第一侧或第二侧与第二半导体管芯的有源侧形成界面。
相应地，示例性方面包括半导体器件，其包括带有基板的第一半导体管芯，该基板包括第一侧和与第一侧相对的第二侧。第一集合的电子元件被集成到第一侧上，而第二集合的电子元件被集成到第二侧上。一个或多个穿透基板的穿板通孔将第一集合的电子元件中的一者或多者与第二集合的电子元件中的一者或多者耦合。
另一示例性方面包括一种形成半导体器件的方法，该方法包括：形成具有第一侧和与第一侧相对的第二侧的第一半导体管芯的基板，在第一侧上集成第一集合的电子元件，在第二侧上集成第二集合的电子元件，以及形成一个或多个穿透基板的穿板通孔以供将第一集合的电子元件中的一者或多者与第二集合的电子元件中的一者或多者耦合。
又一示例性方面包括一种系统，包括：具有第一侧和与第一侧相对的第二侧的第一半导体管芯、集成到第一侧上的第一集合的电子元件和集成到第二侧上的第二集合的电子元件。该系统进一步包括用于将第一集合的电子元件中的一者或多者与第二集合的电子元件中的一者或多者耦合的装置。
附图简要说明
给出附图以帮助对本发明实施例进行描述，且提供附图仅用于解说实施例而非对其进行限定。
图1解说了根据示例性方面的半导体管芯。
图2解说了涉及堆叠示例性半导体管芯的方面。
图3解说了涉及堆叠示例性半导体管芯的另一方面。
图4是根据本公开的各方面的用于形成半导体管芯的示例性过程的流程图解说。
图5是根据示例性方面的形成半导体管芯的方法的流程图解说。
图6解说了示出其中可有利地采用示例性方面的示例性无线通信系统的框图。
详细描述
本发明的各方面在以下针对本发明具体实施例的描述和有关附图中被公开。可以设计替换实施例而不会脱离本发明的范围。另外，本发明中众所周知的元素将不被详细描述或将被省去以免湮没本发明的相关细节。
术语“本发明的实施例”并不要求本发明的所有实施例都包括所讨论的特征、优点、或工作模式。
本文中所使用的术语仅出于描述特定实施例的目的，而并不旨在限定本发明的实施例。如本文所使用的，单数形式的“一”、“某”和“该”旨在也包括复数形式，除非上下文另有明确指示。还将理解，术语“包括”、“具有”、“包含”和/或“含有”在本文中使用时指明所陈述的特征、整数、步骤、操作、元素、和/或组件的存在，但并不排除一个或多个其他特征、整数、步骤、操作、元素、组件和/或其群组的存在或添加。
此外，许多实施例是根据将由例如计算设备的元件执行的动作序列来描述的。将认识到，专门电路(例如，专用集成电路(ASIC))、执行程序指令的一个或多个处理器、或这两者的组合可以执行本文中所描述的各种动作。另外，本文描述的动作序列可被认为是完全体现在任何形式的计算机可读存储介质内，其内存储有一经执行就将使相关联的处理器执行本文所描述的功能性的相应计算机指令集。因此，本发明的各种方面可以用数种不同形式来体现，所有这些形式都已被构想落在所要求保护的主题内容的范围内。另外，对于本文描述的每个实施例，任何此类实施例的对应形式可在本文中被描述为例如被配置成执行所描述的动作的“逻辑”。
本公开的诸方面涉及在半导体管芯的至少两侧(或者换而言之，半导体管芯的两面)上集成电子元件和集成电路组件。各侧和各面可相关于半导体管芯的基板。如此，示例性半导体管芯包括第一侧和第二侧。不作为限制，第一侧可包括管芯的常规有源侧而第二侧可包括管芯的常规背侧。第二侧或背侧在作为第一侧或有源侧的基板的相对侧上。然而，脱离常规设计，本公开中管芯的第二侧包括比半导体管芯的常规背侧多得多。例如，在本公开的诸方面中，与被限于前述电路连接、焊球等的半导体器件的常规背侧相反，第二侧还包括电子元件或集成电路组件。
相应地，在本公开中，使用术语“有源侧”和“背侧”仅被用于解释起见，以提供示例性方面与常规设计的区别。将理解，参照第一侧使用术语“有源”并不意指传达第二侧排除了有源组件。因此，在示例性方面中，第一和第二侧两者都可包括电子元件和集成电路组件。换而言之，本公开的示例性方面涉及对常规设计的改进，其中此类常规设计限制将电子元件集成到常规有源侧并且最好也不过将管芯的常规背侧用于互连、焊球等等。
更详细地，示例性半导体管芯的第一侧包括一个或多个电子元件的第一集合且第二侧包括一个或多个电子元件的第二集合。如本文所使用的，术语“电子元件”意指包括半导体器件，诸如晶体管、门、和集成电路的其他此类组件。术语“电子元件”包括诸如晶体管之类的有源器件，以及诸如电感器、电容器等之类的无源器件。更重要地，本公开中的术语“电子元件”排除诸如金属化层、导线、网、互连、焊球等之类的电路组件，这些组件的主要功能是用于提供电连接。因此，对例如集成到第一/第二侧上的电子元件的引用意指排除前述常规倒装芯片设计中的焊球，尽管在示例性方面中，除了在第一/第二侧上的电子元件外，也可集成焊球。
并且，示例性半导体管芯还包括贯穿通孔，用于耦合第一侧和第二侧，并且更具体地，用于将第一集合的电子元件中的至少一者与第二集合的器件中的至少一者耦合。在一个非限定示例中，半导体管芯可由如本领域已知的硅基板形成，在该情形中，贯穿通孔可以是穿硅通孔(TSV)。在另一非限定示例中，半导体管芯可由玻璃基板形成，在该情形中，贯穿通孔可以是穿玻通孔(TGV)。本领域技术人员将能够将本公开的各方面扩展至用于形成半导体管芯以及贯穿通孔的其他已知技术，而不脱离本公开的范围。并且，贯穿通孔可仅包括第一集合的电子元件与第二集合的电子元件之间的电连接的一部分，因为第一和/或第二侧上可存在完成该电子连接的金属导线。换而言之，贯穿通孔不需要仅提供第一集合的电子元件与第二集合的电子元件之间的互连路径，并且由此，可用于协同如本领域已知的金属导线、网、互连来电耦合第一和第二侧。
相应地，通过在半导体管芯的第二侧上集成电子元件，示例性方面利用先前未在半导体管芯的常规背侧上利用的半导体管芯上的附加表面积。在一些非限定示例中，第二侧可尤其适合诸如薄膜晶体管(TFT)、I/O晶体管或门(可包括I/O TFT)、二极管(包括薄膜二极管)之类的电子元件、诸如平行板电容器之类的无源器件等。第二侧还可包括与半导体管芯的静电放电(ESD)保护有关的电子元件。相应地，集成到半导体管芯的第二侧上的第二集合的电子元件可包括但不限于由薄膜技术、无源器件、和/或ESD元件制造的电子元件。因此，这些第二集合的电子元件可移出半导体管芯的第一侧以缓解第一侧上的拥塞。集成到第一侧上的第一集合的电子元件可包括作为集成电路或片上系统的一部分的常规电子元件(例如，常规晶体管，诸如互补金属氧化物半导体(CMOS)晶体管)。然而，第一集合的电子元件并不限于该方式，并且在一些方面中还可包括薄膜器件和无源器件。集成到或第一侧或第二侧上的电子元件的本质和类型可以是因特定设计需要而异的，并且不限于以上示例。例如，设计者可考虑特定半导体管芯的放置和布线要求以及第一侧与第二侧之间可通过一个或多个贯穿通孔耦合的分配电子元件。
在附加方面中，如以上的具有第一和第二侧的以上半导体管芯还可与一个或多个其他半导体管芯相堆叠。如本领域已知的穿硅堆叠(TSS)可用于堆叠。一个或多个其他半导体管芯可以是具有常规有源侧和常规背侧的常规半导体管芯，或者它们可以是(但不限于)如上所讨论的具有电子组件的第一和第二侧的示例性半导体管芯。并且，因为示例性半导体管芯在第一和第二侧两者上都有电子元件，因而或第一侧或第二侧可被配置成与另一半导体管芯形成界面以供堆叠。现在将参照附图进一步说明以上和附加方面。
参照图1，解说了半导体管芯100。半导体管芯100可根据以上讨论的示例性方面来设计，并且包括在基板104的任一侧上形成的第一侧102和第二侧106。如所解说的，第一侧102代表性地示为包括常规有源侧，且第二侧106代表性地示为包括半导体管芯100的常规背侧。更具体地，第一侧102可包括一个或多个电子元件(诸如晶体管110a(例如，CMOS晶体管))的第一集。并且，第一侧102还可包括一个或多个金属层或互连110b，一个或多个金属层或互连110b可在第一侧102上在第一集的电子元件之间形成互连，尽管这些金属层或互连110b并非一个或多个电子元件的第一集的一部分。类似地，第二侧106包括一个或多个电子元件(诸如，I/O晶体管108a(可以是TFT)、平行板电容器108b和二极管108c(可以是薄膜二极管))的第二集。二极管108c可被用于半导体管芯100的静电放电(ESD)保护。第二侧106还可包括用于ESD保护的其他电子元件。并且，第二侧106可包括一个或多个金属层或互连108d，一个或多个金属层或互连108d可在第二集的电子元件之间形成互连，但这些金属层或互连108d并非一个或多个电子元件的第二集的一部分。
在所解说的示例中，半导体管芯100可以是硅管芯，并且如此，基板104可由硅形成。相应地，基板104包括代表性地解说为穿硅通孔(TSV)112的一个或多个贯穿通孔。TSV112被配置成将第一侧102的组件电耦合至第二侧106的组件。更具体地，TSV 112可将第一侧102上的一个或多个金属层或互连110b与第二侧106上的一个或多个金属层或互连108d耦合。并且，在一些方面中，基板104不需要专用于仅贯穿通孔，而是还可用于形成附加集成电路组件，诸如沟槽电容器114。
现在参照图2，解说了涉及半导体管芯100的封装和堆叠的第一方面。更具体地，如所解说的，半导体封装200包括可以是第一层或“层1”管芯的半导体管芯100。半导体管芯100可用可以是第二层或“层2”管芯的第二管芯(管芯202)来堆叠。不作为限制，管芯202可根据具有集成到管芯202的两个相对侧上的电子元件的示例性方面或者根据具有常规有源侧和常规背侧的常规方面来配置。分层结构被解说为代表垂直堆叠或三维(3D)封装。该堆叠可至少部分地基于示例性半导体器件的贯穿通孔来完成，并且如此被称为穿硅堆叠(TSS)。
如所示，不限定地，管芯202是常规芯片，并且如此可按倒装芯片方式用半导体管芯100来堆叠。相应地，管芯202的正面或有源侧可与包括半导体管芯100的常规背侧的第二侧106对接。因此，将所解说的结构与传统或常规术语相关，该堆叠也称为“面对背堆叠”，其中层2管芯的面用层1管芯的背侧来堆叠。更具体地，示例性半导体封装包括藉由包括焊球204的第一球栅阵列堆叠至半导体管芯100的管芯202。焊球204连接至互连108d，互连108d可耦合至TSV 112。如先前所讨论的，TSV 112提供半导体管芯100的第二侧106至第一侧102的耦合。因此，TSV 112提供用于以TSS方式将半导体管芯100的第一侧102耦合至管芯202的装置。此外，在一些方面中，半导体管芯100可进一步堆叠至与第一侧102对接的第三管芯(未示出)，或者如在所解说的方面中，通过包括焊球206的第二球栅阵列附连至封装基板208。焊球206可将封装基板208耦合至半导体管芯100的第一侧102上的互连110b。另外，半导体封装200可包括模具210以封装两个管芯－半导体管芯100和管芯202。参照图3，解说了涉及半导体管芯100的封装和堆叠的第二方面。图3的半导体封装300在许多方面类似于以上讨论的图2的半导体封装200。因此，为了简明起见，图3的解释将省略这些附图之间的某些共同方面。如所解说的，半导体封装300还包括作为“层1”管芯的半导体管芯100，半导体管芯可用可以是“层2”管芯的第二管芯(管芯302)来堆叠。再一次，管芯302可根据具有集成到管芯302的两个相对侧上的电子元件的示例性方面或者根据具有常规有源侧和常规背侧的常规方面来配置。管芯302可按倒装芯片方式用半导体管芯100来堆叠。
与图2的半导体封装200相反，图3的半导体封装300示出了“面对面堆叠”。更具体地，管芯302的正面或有源侧在此与包括半导体管芯100的常规有源侧的第一侧102对接。管芯302藉由包括焊球304的第一球栅阵列堆叠至半导体管芯100。焊球304连接至互连110b，互连110b可耦合至TSV 112。TSV 112提供半导体管芯100的第一侧102至第二侧106的耦合。因此，在此情形中，TSV 112提供用于以面对面TSS方式将半导体管芯100的第二侧106耦合至管芯302的装置。半导体管芯100可进一步堆叠至与第二侧106对接的第三管芯(未示出)，或者如在所解说的方面中，通过包括焊球306的第二球栅阵列附连至封装基板308。焊球306可将封装基板308耦合至半导体管芯100的第二侧106上的互连108d。另外，半导体封装300还可包括模具310以封装两个管芯－半导体管芯100和管芯302。
因此，如图2-3的TSS堆叠示例中所示，用于耦合示例性半导体管芯的第一和第二侧的TSV还可用于以垂直分层方式或以3D封装结构用一个或多个附加管芯来堆叠示例性半导体管芯。
现在参照图4，解说了用于根据示例性方面形成半导体管芯的示例性过程流。例如，过程流400始于处理包括感兴趣的半导体管芯或芯片(例如，半导体管芯100)的半导体晶片的第一侧(或常规前/有源侧，例如第一侧202)(所处理的晶片可以或可以不包括TSV(在此步骤中，诸如TSV 112))－框402。
接着，芯片可被配置为倒装芯片和载体安装；如果已经存在TSV，则薄TSV部分可被揭示/暴露－框404。在此之后，薄膜晶体管(TFT)基础涂层可被应用于芯片的第二侧(例如，第二侧106)或背侧，其具有用于形成TFT器件的毯覆隔离－框406。可在第二侧上针对沟槽电容器(例如，沟槽电容器114)来图案化沟槽－框408。可在第二侧上针对电子元件执行沉积和图案化，诸如针对晶体管(例如，108a)的审计、平行板电容器(108b)的顶部电极等－框410。如果针对平行板电容器的氧化物不同于针对晶体管栅极的氧化物，则可针对这些氧化物执行分开的图案化和薄膜沉积－框412。接着，TFT晶体管、平行板电容器的二极管(例如，108c)本体和底部电极可被图案化－框414。可针对晶体管、二极管、沟槽电容器和平行板电容器的底部电极执行薄膜沉积－框416。在一些方面中，在框416，非晶透明导电氧化物(ATCO)薄膜可被用于底部电极。
层间电介质(ILD)可被沉积在第二侧或背侧上以形成接触(例如，对于图2中解说并参照半导体封装200描述的面对背配置)－框418。可执行用于形成(例如，至包括焊球204的BGA的)接触的导电材料的图案化和填充－框420。可在第二侧或背侧上执行针对TSV的图案化并可填充导电材料－框422。可在第二侧或背侧上执行Cu镀敷以形成重分布层(RDL)－框424。
在第二侧或背侧上执行钝化并添加包括焊球204的凸块/微凸块或BGA－框426。如上处理的半导体管芯现在可被组装以供堆叠(例如，在图2中面对背堆叠的TSS堆叠示例中)－框428。半导体管芯现在可用第二管芯(例如，管芯202)来堆叠，如在以上所讨论的章节中。
将领会，各实施例包括用于执行本文中所公开的过程、功能和/或算法的各种方法。例如，如图5中所解说的，一实施例可包括一种形成半导体器件的方法(500)，该方法包括：形成具有第一侧(例如102)和与第一侧相对的第二侧(例如106)的第一半导体管芯(例如100)的基板(例如104)－框502；在第一侧上集成第一电子元件集(例如110a)－框504；在第二侧上集成第二电子元件集(例如，108a、108b、108c)－框506；以及形成通过该基板用于将第一电子元件集中的一者或多者与第二电子元件集中的一者或多者耦合的一个或多个穿板通孔(例如112)－框508。
在图6中，解说了其中可有利地采用本公开的一方面的示例性无线通信系统600的框图。出于解说目的，图6示出了三个远程单元620、630和650以及两个基站640。将认识到，无线通信系统可具有远多于此的远程单元和基站。例如，远程单元620、630和650包括包含所公开的半导体管芯100的集成电路(IC)器件625A、625C和625B。将认识到，其他设备也可包括所公开的半导体管芯100，诸如基站、交换设备、和网络装备。图6示出了从基站640到远程单元620、630、和650的前向链路信号680，以及从远程单元620、630、和650到基站640的反向链路信号690。
在图6中，远程单元620被示为移动电话，远程单元630被示为便携式计算机，而远程单元650被示为无线本地环路系统中的位置固定的远程单元。例如，远程单元可以是移动电话、手持式个人通信系统(PCS)单元、便携式数据单元(诸如个人数据助理)、启用GPS的设备、导航设备、机顶盒、音乐播放器、视频播放器、娱乐单元、位置固定的数据单元(诸如仪表读数装置)、或者存储或取回数据或计算机指令的其他设备、或者其组合。尽管图6解说了根据本公开的教义的远程单元，但本公开并不限于这些所解说的示例性单元。本公开的诸方面也可被集成到机顶盒、音乐播放器、饰品播放器、娱乐单元、导航设备、个人数字助理(PDA)、位置固定的数据单元、移动电话、智能电话、或计算机中。
本领域技术人员将领会，信息和信号可使用各种不同技术和技艺中的任何一种来表示。例如，贯穿上面说明始终可能被述及的数据、指令、命令、信息、信号、比特、码元、和码片可由电压、电流、电磁波、磁场或磁粒子、光场或光粒子、或其任何组合来表示。
此外，本领域技术人员将领会，结合此处所公开的各实施例描述的各种说明性逻辑框、模块、电路和算法步骤可被实现为电子硬件、计算机软件、或两者的组合。为清楚地解说硬件与软件的这一可互换性，各种解说性组件、框、模块、电路、和步骤在上面是以其功能性的形式作一般化描述的。此类功能性是被实现为硬件还是软件取决于具体应用和施加于整体系统的设计约束。技术人员对于每种特定应用可用不同的方式来实现所描述的功能性，但这样的实现决策不应被解读成导致脱离了本发明的范围。
结合本文公开的各实施例描述的方法、序列和/或算法可直接在硬件中、在由处理器执行的软件模块中、或在这两者的组合中体现。软件模块可驻留在RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动盘、CD-ROM或者本领域中所知的任何其他形式的存储介质中。示例性存储介质耦合到处理器以使得该处理器能从/向该存储介质读写信息。替换地，存储介质可以被整合到处理器。
相应地，本发明的一实施例可包括实施用于形成具有集成到半导体管芯的背侧上的电子元件的半导体管芯的方法的计算机可读介质。相应地，本发明并不限于所解说的示例且任何用于执行本文中所描述的功能性的手段均被包括在本发明的实施例中。
尽管上述公开示出了本发明的解说性实施例，但是应当注意到，在其中可作出各种更换和改动而不会脱离如所附权利要求定义的本发明的范围。根据本文中所描述的本发明实施例的方法权利要求的功能、步骤和/或动作不必按任何特定次序来执行。此外，尽管本发明的要素可能是以单数来描述或主张权利的，但是复数也是已料想了的，除非显式地声明了限定于单数。

Claims (23)

1.一种半导体器件，包括：
带有基板的第一半导体管芯，所述基板包括第一侧和与所述第一侧相对的第二侧；
集成到所述第一侧上的第一电子元件集；
集成到所述第二侧上的第二电子元件集；以及
一个或多个通过所述基板的穿板通孔以将所述第一电子元件集中的一者或多者与所述第二电子元件集中的一者或多者耦合。
2.如权利要求1所述的半导体器件，其特征在于，所述第一电子元件集包括晶体管或有源电路元件中的一者或多者。
3.如权利要求1所述的半导体器件，其特征在于，所述第二电子元件集包括输入/输出设备、薄膜晶体管(TFT)、无源电路元件、或用于所述半导体器件的静电放电(ESD)保护的电子元件中的一者或多者。
4.如权利要求3所述的半导体器件，其特征在于，所述无源电路元件或用于静电放电(ESD)保护的电子元件中的至少一者包括薄膜二极管。
5.如权利要求1所述的半导体器件，其特征在于，进一步包括集成到所述第一侧或所述第二侧中的至少一者上的一个或多个互连、金属导线、或焊球。
6.如权利要求1所述的半导体器件，其特征在于，进一步包括与所述第一半导体管芯相堆叠的第二半导体管芯，其中所述第一半导体管芯的所述第二侧与所述第二半导体管芯的有源侧形成界面。
7.如权利要求6所述的半导体器件，其特征在于，所述第一半导体管芯和所述第二半导体管芯通过穿硅堆叠(TSS)来堆叠。
8.如权利要求1所述的半导体器件，其特征在于，进一步包括与所述第一半导体管芯相堆叠的第二半导体管芯，其中所述第一半导体管芯的所述第二侧与所述第二半导体管芯的有源侧形成界面。
9.如权利要求8所述的半导体器件，其特征在于，所述第一半导体管芯和所述第二半导体管芯通过穿硅堆叠(TSS)来堆叠。
10.如权利要求1所述的半导体器件，其特征在于，所述基板由硅制成并且所述一个或多个穿板通孔中的至少一者是穿硅通孔(TSV)或穿玻通孔(TGV)。
11.如权利要求1所述的半导体器件，其特征在于，所述半导体器件集成到选自包括以下各项的组的设备中：机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、个人数字助理(PDA)、位置固定的数据单元、移动电话、以及计算机。
12.一种形成半导体器件的方法，所述方法包括：
形成具有第一侧和与所述第一侧相对的第二侧的第一半导体管芯的基板；
在所述第一侧上集成第一集合的电子元件；
在所述第二侧上集成第二集合的电子元件；以及
形成一个或多个穿透所述基板的穿板通孔以供将所述第一集合的电子元件中的一者或多者与所述第二集合的电子元件中的一者或多者耦合。
13.如权利要求12所述的方法，其特征在于，所述第一集合的电子元件包括晶体管或有源电路元件中的一者或多者。
14.如权利要求12所述的方法，其特征在于，所述第二集合的电子元件包括输入/输出设备、薄膜晶体管(TFT)、无源电路元件、或用于所述半导体器件的静电放电(ESD)保护的电子元件中的一者或多者。
15.如权利要求14所述的方法，其特征在于，所述无源电路元件或用于静电放电(ESD)保护的电子元件中的至少一者是薄膜二极管。
16.如权利要求12所述的方法，其特征在于，进一步包括在所述第一侧或所述第二侧中的至少一者上集成一个或多个互连、金属导线、或焊球。
17.如权利要求12所述的方法，其特征在于，进一步包括使第二半导体管芯与所述第一半导体管芯相堆叠，其中所述第一半导体管芯的所述第一侧与所述第二半导体管芯的有源侧形成界面。
18.如权利要求17所述的方法，其特征在于，所述堆叠包括穿硅堆叠(TSS)。
19.如权利要求12所述的方法，其特征在于，进一步包括使第二半导体管芯与所述第一半导体管芯相堆叠，其中所述第一半导体管芯的所述第二侧与所述第二半导体管芯的有源侧形成界面。
20.如权利要求19所述的方法，其特征在于，所述堆叠包括穿硅堆叠(TSS)。
21.如权利要求12所述的方法，其特征在于，包括由硅制成所述基板，其中所述一个或多个穿板通孔中的至少一者是穿硅通孔(TSV)或穿玻通孔(TGV)。
22.一种系统，包括：
具有第一侧和与所述第一侧相对的第二侧的第一半导体管芯；
集成到所述第一侧上的第一集合的电子元件；
集成到所述第二侧上的第二集合的电子元件；以及
用于将所述第一集合的电子元件中的一者或多者与所述第二集合的电子元件中的一者或多者耦合的装置。
23.如权利要求22所述的系统，其特征在于，进一步包括第二半导体管芯以及用于使所述第二半导体管芯与所述第一半导体管芯相堆叠的装置，其中所述第一半导体管芯的所述第一侧或所述第二侧与所述第二半导体管芯的有源侧形成界面。
CN201580051134.9A 2014-09-27 2015-09-16 半导体芯片的背侧上的电子元件集成 Pending CN107112301A (zh)

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