CN107103888A - Time sequence driving circuit, drive circuit and the liquid crystal display panel of liquid crystal display panel - Google Patents
Time sequence driving circuit, drive circuit and the liquid crystal display panel of liquid crystal display panel Download PDFInfo
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- CN107103888A CN107103888A CN201710358681.2A CN201710358681A CN107103888A CN 107103888 A CN107103888 A CN 107103888A CN 201710358681 A CN201710358681 A CN 201710358681A CN 107103888 A CN107103888 A CN 107103888A
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- liquid crystal
- display panel
- crystal display
- pin
- time sequence
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
Abstract
The invention discloses a kind of time sequence driving circuit of liquid crystal display panel, including：System board, it provides supply voltage；Control panel, it electrically connects to receive the supply voltage with the system board；First level translator and second electrical level converter, it includes the first pin, second pin, the 3rd pin and the 4th pin, and two first pins are used to detect the supply voltage, and two the 4th pins are electrically connected with the gate drivers respectively；With gate cell, it includes two inputs, and two inputs are electrically connected with two second pins respectively, described to be electrically connected respectively with two the 3rd pins with the output end of gate cell.The invention also discloses a kind of drive circuit of liquid crystal display panel and liquid crystal display panel.Using the present invention, the problem of level translator of false triggering first and second electrical level converter overcurrent protection can be prevented.
Description
Technical field
The invention belongs to display technology field, specifically, it is related to a kind of time sequence driving circuit of liquid crystal display panel, drive
Dynamic circuit and liquid crystal display panel.
Background technology
Existing liquid crystal display panel, it is desirable to resolution ratio more and more higher, current HD (High Definition, high definition) point
The liquid crystal display panel of resolution is that, using 4 control signals, this 4 control signals are that (level turns by a leverl shifter
Parallel operation) produce, in order to accelerate the velocity of discharge, improve power-off ghost shadow, picture is disappeared faster, leverl shifter, which can be detected, is
Unite voltage of the plate to control panel, the voltage is generally 12V during working condition, and in shutdown, the voltage can be reduced gradually, when less than
During some threshold value, leverl shifter can continue output high level, and the high level can be transferred to the thin film transistor (TFT) of viewing area
To open the thin film transistor (TFT), so as to realize that all liquid crystal capacitances discharge (discharge) as early as possible.
The liquid crystal display panel of existing UD (Ultra High Definition, ultra high-definition) resolution ratio needs to use 8 controls
Signal processed is general to produce 4 control signals using two while consider versatility in order to produce 8 control signals
Leverl shifter (level translator), collocation produces 8 control signals, so as to cause circuit more, in order to prevent liquid crystal
Display panel causes to damage due to line short, and leverl shifter generally do excessively stream (OCP) protection.
However, when the liquid crystal display panel of existing UD resolution ratio needs to use two leverl shifter, leverl
Shifter is due to factors such as the errors on processing procedure, and the voltage that two leverl shifter triggerings persistently export high level has
Institute's difference, the voltage that such as one leverl shifter triggering persistently exports high level is 10.1V, and another leverl
The voltage that shifter triggerings persistently export high level is 9.8V, in this case, it may appear that sometimes one leverl shifter
Triggering persistently exports high level, and another leverl shifter normally exports (square wave), so as to cause super-large current, causes
Leverl shifter false triggering overcurrent protections.
The content of the invention
The technical problems to be solved by the invention are that there is provided a kind of time sequence driving circuit of liquid crystal display panel, driving
Circuit and liquid crystal display panel.The problem of level translator of false triggering first and second electrical level converter overcurrent protection can be prevented.
In order to solve the above-mentioned technical problem, first aspect present invention embodiment provides a kind of sequential of liquid crystal display panel
Drive circuit, the liquid crystal display panel includes provided with thin film transistor (TFT) and brilliant with the film in viewing area, the viewing area
The liquid crystal capacitance of body pipe electrical connection, the liquid crystal display panel also includes gate drivers, and the gate drivers output is opened
Voltage closes voltage to the thin film transistor (TFT), including：
System board, it provides supply voltage；
Control panel, it electrically connects to receive the supply voltage with the system board；
First level translator and second electrical level converter, it includes the first pin, second pin, the 3rd pin and the
Four pins, two first pins are used to detect the supply voltage, and two the 4th pins drive with the grid respectively
Dynamic device electrical connection；
With gate cell, it includes two inputs, and two inputs are electrically connected with two second pins respectively,
It is described to be electrically connected respectively with two the 3rd pins with the output end of gate cell；Wherein,
When the supply voltage is less than the first threshold voltage of first level translator and second electrical level conversion
During the second threshold voltage of device, the second pin of first level translator and the second electrical level converter it is described
Second pin exports high level to the input with gate cell, and the output end with gate cell is exported respectively
High level gives two the 3rd pins, and first level translator and the second electrical level converter pass through the 4th pin point
High level is not exported persistently to gate drivers, the gate drivers export the film of the cut-in voltage to the viewing area
Transistor, realizes the liquid crystal capacitance electric discharge.
In the embodiment of first aspect present invention one, when the supply voltage is higher than the first threshold voltage and described the
Two threshold voltages at least one when, first level translator and the second electrical level converter are normally exported.
In the embodiment of first aspect present invention one, the time sequence driving circuit also includes detecting branch road, the detecting branch
Road includes first resistor and second resistance, and the first end connection control panel of the first resistor is described for receiving supply voltage
Second end of first resistor connects the first pin of first level translator, the first of the second electrical level converter respectively
The first end of pin, the second resistance；The second end ground connection of the second resistance.
In the embodiment of first aspect present invention one, the resistance of the first resistor is less than the resistance of the second resistance.
It is described to pass through CMOS logic, NMOS logics, PMOS logics with gate cell in the embodiment of first aspect present invention one
Or diode is realized.
In the embodiment of first aspect present invention one, the scope of the first threshold voltage is 9V-11V；Second threshold
The scope of threshold voltage is 9V-11V.
Second aspect of the present invention provides a kind of drive circuit of liquid crystal display panel, and the liquid crystal display panel includes display
Provided with thin film transistor (TFT) and the liquid crystal capacitance electrically connected with the thin film transistor (TFT) in area, the viewing area, including：
Time sequence driving circuit, it is the time sequence driving circuit of above-mentioned liquid crystal display panel；
Gate drivers, its respectively with the 4th pin of first level translator and second electrical level converter electricity
Connection, the gate drivers are also electrically connected with scan line, and the scan line electrically connects the grid of the thin film transistor (TFT).
In the embodiment of second aspect of the present invention one, the gate drivers are produced on the array of the liquid crystal display panel
On substrate.
In the embodiment of second aspect of the present invention one, the drive circuit also includes source electrode driver, the Timing driver
Circuit is electrically connected with the source electrode driver, and the source electrode driver is also electrically connected with data wire, the data wire with it is described thin
The source electrode electrical connection of film transistor, the liquid crystal capacitance is electrically connected with the drain electrode of the thin film transistor (TFT).
Third aspect present invention embodiment provides a kind of liquid crystal display panel, includes the drive of above-mentioned liquid crystal display panel
Dynamic circuit.
Implement the present invention, have the advantages that：
Because the time sequence driving circuit of liquid crystal display panel includes and gate cell, with two inputs of gate cell respectively with
Two second pin electrical connections, it is described to be electrically connected respectively with two the 3rd pins with the output end of gate cell, so that,
Even if the first threshold voltage of the first level translator is different with the second threshold voltage of second electrical level converter, the first level turns
Parallel operation and second electrical level converter persistently export high level by the 4th pin by being controlled with the output end of gate cell respectively, so that
The problem of level translator of super-large current false triggering first and second electrical level converter overcurrent protection is not resulted in.
Brief description of the drawings
, below will be to embodiment or prior art in order to illustrate more clearly of technical scheme of the invention or of the prior art
The accompanying drawing used required in description is briefly described, it should be apparent that, drawings in the following description are only the present invention's
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also be according to this
A little accompanying drawings obtain other accompanying drawings.
Fig. 1 is the schematic diagram of the time sequence driving circuit of one embodiment of the invention liquid crystal display panel；
Shown by reference numeral explanation：
110- system boards；120- control panels；The level translators of 130- first；The pins of 131- first；132- second pins；
The pins of 133- the 3rd；140- second electrical level converters；The pins of 141- first；142- second pins；The pins of 143- the 3rd；150- with
Gate cell；160- detects branch road；R1- first resistors；R2- second resistances.
Embodiment
Below in conjunction with the accompanying drawing in the present invention, the technical scheme in the present invention is clearly and completely described, shown
So, described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Based on the reality in the present invention
Example is applied, the every other embodiment that those of ordinary skill in the art are obtained under the premise of creative work is not made all belongs to
In the scope of protection of the invention.
The term " comprising " and " having " occurred in present specification, claims and accompanying drawing and their any changes
Shape, it is intended that covering is non-exclusive to be included.For example contain the process of series of steps or unit, method, system, product or
The step of equipment is not limited to list or unit, but alternatively also include the step of do not list or unit, or it is optional
Ground is also included for the intrinsic other steps of these processes, method, product or equipment or unit.In addition, term " first ", " the
Two " and " the 3rd " etc. be, for distinguishing different objects, and to be not intended to describe specific order.
The present invention provides a kind of time sequence driving circuit of liquid crystal display panel, the liquid crystal display panel include viewing area and
External zones, the viewing area refers generally to show to be provided with thin film transistor (TFT) and and film crystal in the region of figure, the viewing area
The liquid crystal capacitance of pipe electrical connection, the external zones is set around the viewing area, and the external zones is provided with some electrical components
And circuit, such as provided with source electrode driver, gate drivers, namely the liquid crystal display panel also includes gate drivers, institute
Gate drivers are stated to export cut-in voltage or close voltage to the thin film transistor (TFT).Refer to Fig. 1, the time sequence driving circuit
Including：
System board 110, it provides supply voltage, and the supply voltage of the offer is generally 12V, when display panel shuts down,
The supply voltage is slowly reduced.System board 110 is machine core board, and it is used for the conversion video and audio signal or similar signal
For the displayable signal of liquid crystal display panel.
Control panel 120, it electrically connects to receive supply voltage, the power supply with the system board 110 by circuit
Voltage is as the input power of control panel 120, and the control panel 120 is provided with level shifter IC (level translator controls
Device processed) and TCON IC (time schedule controller).
First level translator 130 and second electrical level converter 140, it includes the first pin 131,141, second pin
132nd, the 142, the 3rd pin 133,143 and the 4th pin (not illustrating the 4th pin in diagram), the first level translator 130 and
First pin 131,141 of two level translators 140 is used for detecting real-time supply voltage, so that the He of the first level translator 130
Second electrical level converter 140 can obtain the information of supply voltage in real time.Two the 4th pins drive with the grid respectively
Dynamic device electrical connection.
With gate cell 150, it includes two inputs, two inputs respectively with two second pins 132,
142 electrical connections, namely one of them described input are electrically connected with the second pin 132 of the first level translator 130, another
The input is electrically connected with the second pin 142 of second electrical level converter 140；The output end with gate cell 150 is distinguished
Electrically connected with two the 3rd pins 133,143, namely the output end and the first level translator with gate cell 150
130 the 3rd pin 133 is electrically connected, the 3rd pin of the output end with gate cell 150 also with second electrical level converter 140
143 electrical connections, in the present embodiment, the 3rd pin 133,143 are control end.
In the present embodiment, time sequence driving circuit includes the first level translator 130 and second electrical level converter 140, by
In factors such as the errors on processing procedure, the first level translator 130 may be different with the threshold voltage of second electrical level converter 140,
Namely first the second threshold voltage of first threshold voltage and second electrical level converter 140 of level translator 130 may be different,
In the present embodiment, the scope of first threshold voltage is 9V-11V, for example, 9V, 9.5V, 10V, 10.2V, 10.5V, 11V etc.,
The scope of second threshold voltage is 9V-11V, for example, 9V, 9.5V, 9.8V, 10V, 10.5V, 11V etc., here with the first threshold
Threshold voltage is that 10.2V, second threshold voltage are to illustrate, certainly, first threshold voltage and second threshold voltage exemplified by 9.8V
Can also be identical, for the overcurrent protection for preventing first threshold voltage different with second threshold voltage and causing, in the present embodiment
In, when supply voltage is less than the first threshold voltage of the first level translator 130 and the Second Threshold of second electrical level converter 140
During voltage, such as when supply voltage is 9.5V, this interval scale liquid crystal display panel is performing power-off operation, the first level translator
130 second pin 132 and the output high level of second pin 142 of second electrical level converter 140 give the input of gate cell 150
End, now, two inputs with gate cell 150 are high level, by the logical operation with gate cell 150, with gate cell
150 output end output high level, with gate cell 150 export high level export respectively to two the 3rd pins 133,
143, now, the first level translator 130 and second electrical level converter 140 by the 4th pin persistently export respectively high level to
Gate drivers, namely the first level translator 130 persistently export high level, and persistently output is high electric for second electrical level converter 140
Flat, the gate drivers export thin film transistor (TFT) of the cut-in voltage to viewing area, so that the thin film transistor (TFT) of viewing area is beaten
Open, liquid crystal capacitance is discharged, so as to improve power-off ghost shadow, picture is disappeared faster.
When liquid crystal display panel causes supply voltage to reduce suddenly extremely, such as when supply voltage bust is to 10.1V, this
When supply voltage be less than first threshold voltage, but higher than second threshold voltage, now, the first of the first level translator 130 draws
Pin 131 exports high level, but the first pin 141 output low level of second electrical level converter 140, two with gate cell 150
Input receives high level and low level respectively, and by logical operation, low level is exported with the output end of gate cell 150, so that
3rd pin 133,143 of the first level translator 130 and second electrical level converter 140 receives low level, now the first electricity
Flat turn parallel operation 130 and second electrical level converter 140 are normally exported, and this is normally output as square wave, namely the voltage of output has height
Level also has low level, and gate drivers are normally driven, namely gate drivers output cut-in voltage or closing electricity
Pressure, so that the liquid crystal capacitance of liquid crystal display panel viewing area performs normal discharge and recharge or holding, namely gate drivers are carried out
Normal output, so as to not result in the level translator of super-large current false triggering first and second electrical level converter overcurrent protection.
When liquid crystal display panel causes supply voltage to reduce suddenly extremely, such as when supply voltage bust is to 10.5V, this
When supply voltage higher than first threshold voltage and higher than second threshold voltage, now, the first pin of the first level translator 130
131 and the first pin 141 of second electrical level converter 140 export low level, connect respectively with two inputs of gate cell 150
Low level is received, by logical operation, low level is exported with the output end of gate cell 150, so that the first level translator 130 and the
3rd pin 133,143 of two level translators 140 receives low level, now the first level translator 130 and second electrical level
Converter 140 is normally exported by the 4th pin, so that the pixel of liquid crystal display panel viewing area performs normal discharge and recharge,
Normally exported, so as to not result in super-large current false triggering overcurrent protection.
In the present embodiment, due to liquid crystal display panel time sequence driving circuit include with gate cell 150, with gate cell
150 two inputs are electrically connected with two second pins 132,142 respectively, the output end point with gate cell 150
Do not electrically connected with two the 3rd pins 133,143 so that, even if the first threshold voltage of the first level translator 130 and
The second threshold voltage of second electrical level converter 140 is different, and the first level translator 130 and second electrical level converter 140 are distinguished
High level is persistently exported by being controlled with the output end of gate cell 150 by the 4th pin, so as to not result in super-large current false touch
The problem of sending out overcurrent protection.
Continuing with referring to Fig. 1, in the present embodiment, the time sequence driving circuit also includes detecting branch road 160, the detecting
Branch road 160 includes first resistor R1 and second resistance R2, the first resistor R1 first end connection control panel, for receiving electricity
Source voltage, the second end of the first resistor R1 connects the first pin 131, second of first level translator 130 respectively
First pin 141 of level translator 140, the first end of the second resistance R2, the second end ground connection of the second resistance R2.
So as to realize the detecting real-time of supply voltage.In the present embodiment, the resistance of the first resistor R1 is less than second resistance R2's
Resistance, such as R2=10R1, R2=20R1, etc..
In the present embodiment, CMOS is passed through with gate cell 150, described and gate cell 150 to realize
(Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) logic, NMOS (N-
Metal-Oxide-Semiconductor, N-type Metal-oxide-semicondutor) logic, PMOS (positive channel
Metal Oxide Semiconductor, P-channel metal-oxide-semiconductor) logic or diode realize, CMOS, NMOS,
The common knowledge that PMOS, diode are implemented with the circuit of gate cell 150 is this area, is just repeated no more herein.
The present invention also provides a kind of drive circuit of liquid crystal display panel, and the liquid crystal display panel includes viewing area, institute
State provided with thin film transistor (TFT) and the liquid crystal capacitance electrically connected with the thin film transistor (TFT) in viewing area, the drive circuit includes upper
The time sequence driving circuit and gate drivers stated, the gate drivers respectively with first level translator 130 and described
The 4th pin electrical connection of second electrical level converter 140, the gate drivers are also electrically connected with scan line, the scan line electricity
Connect the thin film transistor (TFT) of the viewing area.So as to, when the output end with gate cell 150 export respectively high level to
Two the 3rd pins 133,143, first level translator 130 and the second electrical level converter 140 pass through the 4th
Pin persistently exports high level to gate drivers respectively, and the gate drivers export cut-in voltage via scan line to described
The thin film transistor (TFT) of viewing area, realizes the liquid crystal capacitance electric discharge.When first level translator 130 and second electrical level
When 140 tins of pins of mistake the 4th of converter export low level to gate drivers, the gate drivers normal output signal, namely
Normal output cut-in voltage closes voltage, and the thin film transistor (TFT) is turned on and off, so that the normal charge and discharge of the liquid crystal capacitance
Electricity is kept.
In the present embodiment, the liquid crystal display panel includes array base palte and colored filter substrate, in order to reduce into
This, the gate drivers are produced on array base palte (GOA), so that the first level translator 130, second electrical level converter
140 and with gate cell 150 be located at array base palte on.
In the present embodiment, the drive circuit also includes source electrode driver, the time sequence driving circuit and the source electrode
Driver is electrically connected, and the source electrode driver is also electrically connected with data wire, the source electrode of the data wire and the thin film transistor (TFT)
Electrical connection, the liquid crystal capacitance is electrically connected with the drain electrode of the thin film transistor (TFT).
The present invention also provides a kind of liquid crystal display panel, and the liquid crystal display panel includes above-mentioned liquid crystal display panel
Drive circuit.
It should be noted that each embodiment in this specification is described by the way of progressive, each embodiment weight
Point explanation be all between difference with other embodiments, each embodiment identical similar part mutually referring to.
For device embodiment, because it is substantially similar to embodiment of the method, so description is fairly simple, related part referring to
The part explanation of embodiment of the method.
By the description of above-described embodiment, the present invention has advantages below：
Because the time sequence driving circuit of liquid crystal display panel includes and gate cell, with two inputs of gate cell respectively with
Two second pin electrical connections, it is described to be electrically connected respectively with two the 3rd pins with the output end of gate cell, so that,
Even if the first threshold voltage of the first level translator is different with the second threshold voltage of second electrical level converter, the first level turns
Parallel operation and second electrical level converter persistently export high level by the 4th pin by being controlled with the output end of gate cell respectively, so that
The problem of level translator of super-large current false triggering first and second electrical level converter overcurrent protection is not resulted in.
Above disclosure is only preferred embodiment of present invention, can not limit the right model of the present invention with this certainly
Enclose, therefore the equivalent variations made according to the claims in the present invention, still belong to the scope that the present invention is covered.
Claims (10)
1. a kind of time sequence driving circuit of liquid crystal display panel, the liquid crystal display panel is included in viewing area, the viewing area
The liquid crystal capacitance electrically connected provided with thin film transistor (TFT) and with the thin film transistor (TFT), the liquid crystal display panel also includes grid and driven
Dynamic device, the gate drivers export cut-in voltage or close voltage to the thin film transistor (TFT), it is characterised in that including：
System board, it provides supply voltage；
Control panel, it electrically connects to receive the supply voltage with the system board；
First level translator and second electrical level converter, it includes the first pin, second pin, the 3rd pin and the 4th and drawn
Pin, two first pins are used to detecting the supply voltage, two the 4th pins respectively with the gate drivers
Electrical connection；
With gate cell, it includes two inputs, and two inputs are electrically connected with two second pins respectively, described
Electrically connected respectively with two the 3rd pins with the output end of gate cell；Wherein,
When first threshold voltage and the second electrical level converter of the supply voltage less than first level translator
During second threshold voltage, described the second of the second pin of first level translator and the second electrical level converter
Pin exports high level to the input with gate cell, described to export high electricity respectively with the gate cell output end
Put down to two the 3rd pins, first level translator and the second electrical level converter are held respectively by the 4th pin
Continuous to export high level to gate drivers, the gate drivers export the film crystal of the cut-in voltage to the viewing area
Pipe, realizes the liquid crystal capacitance electric discharge.
2. the time sequence driving circuit of liquid crystal display panel as claimed in claim 1, it is characterised in that when the supply voltage is high
In the first threshold voltage and the second threshold voltage at least one when, first level translator and second electricity
Flat turn parallel operation is normally exported.
3. the time sequence driving circuit of liquid crystal display panel as claimed in claim 1 or 2, it is characterised in that the Timing driver
Circuit also includes detecting branch road, and the detecting branch road includes first resistor and second resistance, and the first end of the first resistor connects
Control panel is connect, for receiving supply voltage, the second end of the first resistor connects the of first level translator respectively
One pin, the first pin of the second electrical level converter, the first end of the second resistance；Second end of the second resistance
Ground connection.
4. the time sequence driving circuit of liquid crystal display panel as claimed in claim 3, it is characterised in that the resistance of the first resistor
Resistance of the value less than the second resistance.
5. the time sequence driving circuit of liquid crystal display panel as claimed in claim 1 or 2, it is characterised in that described and gate cell
Realized by CMOS logic, NMOS logics, PMOS logics or diode.
6. the time sequence driving circuit of liquid crystal display panel as claimed in claim 1 or 2, it is characterised in that the first threshold
The scope of voltage is 9V-11V；The scope of the second threshold voltage is 9V-11V.
7. a kind of drive circuit of liquid crystal display panel, the liquid crystal display panel includes being provided with viewing area, the viewing area
Thin film transistor (TFT) and the liquid crystal capacitance electrically connected with the thin film transistor (TFT), it is characterised in that including：
Time sequence driving circuit, it is the time sequence driving circuit of the liquid crystal display panel described in claim 1-6 any one；
Gate drivers, its 4th pin respectively with first level translator and the second electrical level converter is electrically connected
Connect, the gate drivers are also electrically connected with scan line, the scan line electrically connects the grid of the thin film transistor (TFT).
8. the drive circuit of liquid crystal display panel as claimed in claim 7, it is characterised in that the gate drivers are produced on
On the array base palte of the liquid crystal display panel.
9. the drive circuit of liquid crystal display panel as claimed in claim 7 or 8, it is characterised in that the drive circuit is also wrapped
Include source electrode driver, the time sequence driving circuit is electrically connected with the source electrode driver, the source electrode driver also with data wire
Electrical connection, the data wire is electrically connected with the source electrode of the thin film transistor (TFT), the liquid crystal capacitance and the thin film transistor (TFT)
Drain electrode electrical connection.
10. a kind of liquid crystal display panel, it is characterised in that including the LCD as described in claim 7-9 any one
The drive circuit of plate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710358681.2A CN107103888B (en) | 2017-05-19 | 2017-05-19 | Time sequence driving circuit, driving circuit and the liquid crystal display panel of liquid crystal display panel |
| PCT/CN2017/087822 WO2018209742A1 (en) | 2017-05-19 | 2017-06-09 | Time sequence driving circuit for liquid crystal display panel, driving circuit and liquid crystal display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710358681.2A CN107103888B (en) | 2017-05-19 | 2017-05-19 | Time sequence driving circuit, driving circuit and the liquid crystal display panel of liquid crystal display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107103888A true CN107103888A (en) | 2017-08-29 |
| CN107103888B CN107103888B (en) | 2018-09-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710358681.2A Active CN107103888B (en) | 2017-05-19 | 2017-05-19 | Time sequence driving circuit, driving circuit and the liquid crystal display panel of liquid crystal display panel |
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| Country | Link |
|---|---|
| CN (1) | CN107103888B (en) |
| WO (1) | WO2018209742A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107749285A (en) * | 2017-11-14 | 2018-03-02 | 深圳市华星光电技术有限公司 | One kind electric leakage flow control circuit and control method |
| CN108154859A (en) * | 2018-01-16 | 2018-06-12 | 深圳市华星光电技术有限公司 | A kind of array substrate and display device |
| CN109346019A (en) * | 2018-11-22 | 2019-02-15 | 深圳市华星光电技术有限公司 | Overcurrent protection control circuit for level shift circuit |
| CN110060644A (en) * | 2019-04-10 | 2019-07-26 | 深圳市华星光电技术有限公司 | Liquid crystal display device and its over-current protection method |
| WO2020001594A1 (en) * | 2018-06-29 | 2020-01-02 | 深圳市华星光电半导体显示技术有限公司 | Method and circuit for reducing current for gate driver on array circuit and liquid crystal display |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1514424A (en) * | 2002-12-31 | 2004-07-21 | Lg.菲利浦Lcd株式会社 | Panel display for small scale mode application |
| CN101093649A (en) * | 2006-06-22 | 2007-12-26 | 三星电子株式会社 | Liquid crystal display device and driving method thereof |
| US20080225034A1 (en) * | 2007-02-14 | 2008-09-18 | Advanced Analog Technology, Inc. | Image sticking erasing circuit and method for using the same |
| CN101546536A (en) * | 2008-03-26 | 2009-09-30 | 联咏科技股份有限公司 | Liquid crystal display having function of eliminating power-off ghost shadow |
| CN202503490U (en) * | 2011-02-22 | 2012-10-24 | 罗姆股份有限公司 | Voltage reduction protection circuit and switch driving device using same |
| CN102982780A (en) * | 2012-12-12 | 2013-03-20 | 中颖电子股份有限公司 | Built-in high level generating circuit of liquid crystal display panel |
-
2017
- 2017-05-19 CN CN201710358681.2A patent/CN107103888B/en active Active
- 2017-06-09 WO PCT/CN2017/087822 patent/WO2018209742A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1514424A (en) * | 2002-12-31 | 2004-07-21 | Lg.菲利浦Lcd株式会社 | Panel display for small scale mode application |
| CN101093649A (en) * | 2006-06-22 | 2007-12-26 | 三星电子株式会社 | Liquid crystal display device and driving method thereof |
| US20080225034A1 (en) * | 2007-02-14 | 2008-09-18 | Advanced Analog Technology, Inc. | Image sticking erasing circuit and method for using the same |
| CN101546536A (en) * | 2008-03-26 | 2009-09-30 | 联咏科技股份有限公司 | Liquid crystal display having function of eliminating power-off ghost shadow |
| CN202503490U (en) * | 2011-02-22 | 2012-10-24 | 罗姆股份有限公司 | Voltage reduction protection circuit and switch driving device using same |
| CN102982780A (en) * | 2012-12-12 | 2013-03-20 | 中颖电子股份有限公司 | Built-in high level generating circuit of liquid crystal display panel |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107749285A (en) * | 2017-11-14 | 2018-03-02 | 深圳市华星光电技术有限公司 | One kind electric leakage flow control circuit and control method |
| CN108154859A (en) * | 2018-01-16 | 2018-06-12 | 深圳市华星光电技术有限公司 | A kind of array substrate and display device |
| WO2020001594A1 (en) * | 2018-06-29 | 2020-01-02 | 深圳市华星光电半导体显示技术有限公司 | Method and circuit for reducing current for gate driver on array circuit and liquid crystal display |
| CN109346019A (en) * | 2018-11-22 | 2019-02-15 | 深圳市华星光电技术有限公司 | Overcurrent protection control circuit for level shift circuit |
| CN110060644A (en) * | 2019-04-10 | 2019-07-26 | 深圳市华星光电技术有限公司 | Liquid crystal display device and its over-current protection method |
| CN110060644B (en) * | 2019-04-10 | 2021-01-01 | 深圳市华星光电技术有限公司 | Liquid crystal display device and overcurrent protection method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018209742A1 (en) | 2018-11-22 |
| CN107103888B (en) | 2018-09-14 |
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