CN107103358A - Processing with Neural Network method and system based on spin transfer torque magnetic memory - Google Patents

Processing with Neural Network method and system based on spin transfer torque magnetic memory Download PDF

Info

Publication number
CN107103358A
CN107103358A CN201710182534.4A CN201710182534A CN107103358A CN 107103358 A CN107103358 A CN 107103358A CN 201710182534 A CN201710182534 A CN 201710182534A CN 107103358 A CN107103358 A CN 107103358A
Authority
CN
China
Prior art keywords
data
memory cell
memory
neural network
transfer torque
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710182534.4A
Other languages
Chinese (zh)
Inventor
韩银和
宋莉莉
许浩博
王颖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Computing Technology of CAS
Original Assignee
Institute of Computing Technology of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Computing Technology of CAS filed Critical Institute of Computing Technology of CAS
Priority to CN201710182534.4A priority Critical patent/CN107103358A/en
Publication of CN107103358A publication Critical patent/CN107103358A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Artificial Intelligence (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Neurology (AREA)
  • Memory System (AREA)

Abstract

The present invention relates to a kind of Processing with Neural Network method and system based on spin transfer torque magnetic memory, including following steps:Step S1, the operational order for needing to perform is read from memory cell, and input data to be calculated is write into the memory cell according to the operational order, and generates control signal;Step S2, obtains the input data from the memory cell, and the calculating operation in neural computing is performed with reference to the control signal, produces intermediate calculation data and finally calculates data, and is stored in the memory cell;Wherein the memory cell storage medium is multilayer spin transfer torque magnetic memory.Pin of the present invention can ensure neural computing precision simultaneously, reduction Resources on Chip expense and energy loss.

Description

Processing with Neural Network method and system based on spin transfer torque magnetic memory
Technical field
Acceleration field is calculated the present invention relates to hardware neural network model, it is more particularly to a kind of to be based on spin transfer torque magnetic The Processing with Neural Network method and system of memory.
Background technology
Deep neural network is one of sensor model that artificial intelligence field has highest development level, and such network passes through The neural attachment structure of modeling human brain is set up, data characteristics is described by the layering of multiple conversion stages, is The application of the big datas such as image, video and audio processing task brings breakthrough.Because neural network model is to environment Noise and problems of Signal Integrity have enough robustness, therefore the partial loss of calculating data will not be produced to result of calculation Devastating impact, realizing the neural network processor of neural network computing can be seen as a kind of approximate calculation processor.
With the rapid progress of depth learning technology, general neural network processor be deep into image classification, speech recognition, The different application field of the artificial intelligence fields such as intelligent robot, the common trait of these applications is to belong to approximate calculation field. Such application carries out the effectively function such as training completion prediction, classification by gathering mass data collection, and relies on numerical value meter not too much The accuracy of calculation obtains final result, but in embedded device and small-scale data center, because its system architecture is special Point and application field demand, processor are difficult to rely on mass data to realize the purpose of high accuracy calculating in real work, Therefore by approximate calculation method, using in neural network model precision tolerance realize that high precision computation turns into relieving tablet The effective mode of contradiction between upper resource, energy consumption, precision.
Need to handle the data set of enough scales in neural network model application process, this capacity and visit to storage system Ask that speed equally proposes high requirement.Memory based on CMOS technology is the mainstream technology of current on-chip memory design, Such as SRAM (SRAM) and dynamic RAM (DRAM).However as process and power problemses Limitation, CMOS memory is faced with serious design challenge at present, designs depositing for a adaptation neutral net approximate calculation feature Reservoir and built based on this memory the neural network processor storage system with fault tolerance features as one have choose The task of war property.
The content of the invention
The present invention is directed to big operational data scale present in Processing with Neural Network, Resources on Chip demand height and circuit energy The problems such as consuming big is there is provided a kind of Processing with Neural Network method and system based on spin transfer torque magnetic memory, using many Layer spin transfer torque magnetic memory (STT-RAM, full name Spin Toque Transfer RAM) is used as main storage and basis The characteristics of multilayer STT-RAM multi-modes are stored, propose a kind of data mapping structure towards neutral net approximate calculation method and Data path turn-off technique, on the premise of neural computing precision is ensured, reduces storage overhead on piece, reduces circuit Operating power consumption.
Specifically, a kind of Processing with Neural Network method based on spin transfer torque magnetic memory of the invention of settling sth. according to policy or law, its In comprise the following steps:
Step S1, the operational order for needing to perform is read from memory cell, and will be to be calculated defeated according to the operational order Enter data and write the memory cell, and generate control signal;
Step S2, obtains the input data from the memory cell, is performed with reference to the control signal in neural computing Calculating operation, produce intermediate calculation data and it is final calculate data, and be stored in the memory cell;
Wherein the memory cell storage medium is multilayer spin transfer torque magnetic memory.
The Processing with Neural Network method based on spin transfer torque magnetic memory, wherein memory cell possesses multilayer list First memory module, single-bit memory module and state limit multiple-unit memory module, and according to Processing with Neural Network scale and meter Required precision is calculated between above-mentioned three kinds of memory modules to switch, wherein,
Whole MJT both participates in data storage in multilevel-cell memory module, each memory cell, and data bit width is 2N;
Half MJT participates in data storage in single-bit memory module, each memory cell, and data bit width is N;
3/4ths MJT participate in data storage, data bit in state limit multiple-unit memory module, each two memory cell A width of 3/2nds N.
The Processing with Neural Network method based on spin transfer torque magnetic memory, wherein storing the operation using Q forms Instruct, this finally calculates data and the intermediate calculation data, the form of the Q forms is Qn.m, and wherein n is binary number decimal Integer part, m is the fractional part of binary number decimal, and n+m=2N, 2N are data bit width.
The Processing with Neural Network method based on spin transfer torque magnetic memory, wherein step S1 is additionally included in the input When data write the memory cell, if the bit wide of the input data is more than the data bit width of memory cell, the input number is abandoned Low data in, and cancel the calculating for the low data in step s 2.
The operation of the Processing with Neural Network method based on spin transfer torque magnetic memory, the wherein calculating includes vector and multiplied Add operation, pondization operation and local corresponding normalization operation.
The invention also discloses a kind of Processing with Neural Network system based on spin transfer torque magnetic memory, including With lower unit:
Control unit, the operational order for needing to perform is read from memory cell, and will be to be calculated according to the operational order Input data writes the memory cell, and generates control signal;
Computing unit array, including multiple computing units, for obtaining the input data from the memory cell, with reference to this The calculating that control signal is performed in neural computing is operated, and is produced intermediate calculation data and is finally calculated data, and deposit should Memory cell;
Wherein the memory cell storage medium is multilayer spin transfer torque magnetic memory.
The Processing with Neural Network system based on spin transfer torque magnetic memory, wherein memory cell possesses multilayer list First memory module, single-bit memory module and state limit multiple-unit memory module, and according to Processing with Neural Network scale and meter Required precision is calculated between above-mentioned three kinds of memory modules to switch, wherein,
Whole MJT both participates in data storage in multilevel-cell memory module, memory cell, and data bit width is 2N;
Half MJT participates in data storage in single-bit memory module, memory cell, and data bit width is N;
3/4ths MJT participate in data storage, data bit in state limit multiple-unit memory module, each two memory cell A width of 3/2nds N.
The Processing with Neural Network system based on spin transfer torque magnetic memory, wherein storing the operation using Q forms Instruct, this finally calculates data and the intermediate calculation data, the form of the Q forms is Qn.m, and wherein n is binary number decimal Integer part, m is the fractional part of binary number decimal, and n+m=2N, 2N are data bit width.
The Processing with Neural Network system based on spin transfer torque magnetic memory, wherein control unit is additionally included in this When input data writes the memory cell, if the bit wide of the input data is more than the data bit width of memory cell, this is abandoned defeated Enter the low data in data, and turn off in computing unit array computation the computing unit for calculating the low data.
The Processing with Neural Network system based on spin transfer torque magnetic memory, wherein arithmetic operation multiplies including vector Add operation, pondization operation and local corresponding normalization operation.
The present invention is directed to big operational data scale present in neural network processor, Resources on Chip demand height and circuit energy The problems such as amount consumption is big, proposes a kind of neural network processor based on spin transfer torque magnetic memory, is ensureing nerve net Network computational accuracy simultaneously, reduces Resources on Chip expense and energy loss.
Brief description of the drawings
The Processing with Neural Network system architecture diagram that Fig. 1 provides for the present invention;
The multilayer STT-RAM memory cell schematic diagrames that Fig. 2 uses for the present invention;
Fig. 3 is a kind of number based on spin transfer torque magnetic memory towards neural network processor proposed by the present invention According to mapping structure figure;
Fig. 4 is a kind of neural network processor data path turn-off technique schematic diagram proposed by the present invention.
Embodiment
The present invention settles sth. according to policy or law a kind of Processing with Neural Network method based on spin transfer torque magnetic memory, including following Step:
Step S1, the operational order for needing to perform is read from memory cell, and will be to be calculated defeated according to the operational order Enter data and write the memory cell, and generate control signal;
Step S2, obtains the input data from the memory cell, is performed with reference to the control signal in neural computing Calculating operation, produce intermediate calculation data and it is final calculate data, and be stored in the memory cell;
Wherein the memory cell storage medium is multilayer spin transfer torque magnetic memory.
The Processing with Neural Network method based on spin transfer torque magnetic memory, wherein memory cell possesses multilayer list First memory module, single-bit memory module and state limit multiple-unit memory module, and according to Processing with Neural Network scale and meter Required precision is calculated between above-mentioned three kinds of memory modules switch, wherein, multilevel-cell memory module, whole in each memory cell MJT (MTJ Magnetic Tunneling Junction) both participates in data storage, and data bit width is 2N;
Half MJT participates in data storage in single-bit memory module, each memory cell, and data bit width is N;
3/4ths MJT participate in data storage, data bit in state limit multiple-unit memory module, each two memory cell A width of 3/2nds N.
The Processing with Neural Network method based on spin transfer torque magnetic memory, wherein storing the operation using Q forms Instruct, this finally calculates data and the intermediate calculation data, the form of the Q forms is Qn.m, and wherein n is binary number decimal Integer part, m is the fractional part of binary number decimal, and n+m=2N, 2N are data bit width.
The Processing with Neural Network method based on spin transfer torque magnetic memory, wherein step S1 is additionally included in the input When data write the memory cell, if the bit wide of the input data is more than the data bit width of memory cell, the input number is abandoned Low data in, and cancel the calculating for the low data in step s 2.
The operation of the Processing with Neural Network method based on spin transfer torque magnetic memory, the wherein calculating includes vector and multiplied Add operation, pondization operation and local corresponding normalization operation.
In the prior art, neural network processor is present operational data scale is big, Resources on Chip demand is high and circuit energy The problems such as amount consumption is big.Inventor after the carry out numerous studies to neural computing feature and multi storage by sending out Existing, the emerging non-volatile memory technologies including spin transfer torque magnetic memory (STT-RAM) possess static random storage The read or write speed advantage of device, the high density feature of dynamic RAM, the non-volatile characteristic of flash memory and extremely low leakage power Advantage, be used widely in recent years in approximate calculation field.
The characteristics of present invention has a variety of memory modules according to multilayer STT-RAM, memory is used as using multilayer STT-RAM Part, proposes storage system on a kind of data mapping structure and piece suitable for neural network processor, has adapted to neutral net mould The approximate calculation feature of type.Compared with using neural network processors of the SRAM and DRAM as memory, read or write speed is higher, Storage density bigger, consumed energy is smaller, reduces Resources on Chip while neural computing precision is ensured, reduces work Make energy consumption.
The object of the invention is provides a kind of new neural network processor system, and the neural network processor uses multilayer Spin transfer torque magnetic memory (STT-RAM) is carried as main storage and according to multilayer STT-RAM multi-mode storage characteristics Go out a kind of data mapping structure and data path turn-off technique towards neutral net approximate calculation method.
To achieve the above object, the Processing with Neural Network system that the present invention is provided, including:
At least one memory cell, for storing operational order and operational data, the memory cell storage medium is multilayer Spin transfer torque magnetic memory;
At least one computing unit, for performing neural computing;And control unit, with least one described storage Unit is connected with least one described computing unit, for via at least one described memory cell obtain it is described at least one deposit The instruction of storage unit storage, and parse the instruction to control at least one described computing unit.
A kind of storage system based on spin transfer torque magnetic memory towards neural network processor, the storage system Applied to neural network processor and using spin transfer torque memory as memory cell, with multilevel-cell pattern (MLC Pattern), single-bit pattern (SLC patterns) and state limit multiple-unit (SR-MLC patterns) pattern;
A kind of data mapping structure based on spin transfer torque magnetic memory towards neural network processor, the data Mapping structure is based on above-mentioned storage system, corresponding to above-mentioned STT-RAM, respectively with three kinds of accuracy modes, is respectively high accuracy Pattern, low accuracy modes and medium accuracy pattern, every kind of accuracy modes ensure that data bits on the premise of word address is constant Extension and compression;
A kind of data path turn-off technique suitable for above-mentioned storage system, the technology is by the data path quilt of computing unit Multiple independent passages are divided into, passage portion can be switched on or off according to the bit wide in above-mentioned data mapping structure.
To allow the features described above and more clearly understandable, the special embodiment below that can illustrate of effect of the present invention, and coordinate Bright book accompanying drawing is described in detail below.It should be appreciated that specific embodiment described herein is only to explain the present invention, and without It is of the invention in limiting.
Structure of the Processing with Neural Network that the present invention is provided based on storage-control-calculating;
Storage organization is used to store the data for participating in calculating and coprocessor operation instruction, wherein using spin transfer torque magnetic Memory is used as memory cell;
Control structure includes decoding circuit, and for parsing operational order, generation control signal is with the tune of data in control sheet Degree and storage and neural computing process;
Calculating structure includes ALU, for participating in the operation of the neural computing in the processor, compresses number Operation is calculated according to being realized in structure is calculated.
A kind of neural network processor system 101 that Fig. 1 provides for the present invention, the system architecture is made up of six parts, Including input data memory cell 102, control unit 103, output data memory cell 104, weight memory cell 105, instruction Memory cell 106, computing unit array 107.
Control unit 103 respectively with output data memory cell 104, weight memory cell 105, the location of instruction 106, Computing unit array 107 is connected, and control unit 103 obtains operational order and the parsing being stored in the location of instruction 106 The operational order is to control computing unit array 107, the control signal control meter that control unit 103 can be obtained according to analysis instruction The computing unit calculated in cell array 107 carries out neural computing.
Computing unit array 107, is made up of multiple computing units, for the control signal produced according to control unit 103 To perform corresponding neural computing, generation neuron response is calculated.Computing unit 107 and input data memory cell 102 and output data memory cell 104 it is associated, computing unit 107 can be from input data memory cell associated there Data storage part in 102 obtains data to be calculated, and can be to output data memory cell associated there 104 write-in data.Computing unit 107 is the special module designed exclusively for neutral net, for completing in neural network algorithm Most of computing, i.e. the multiply-add operation of vector, pond and local corresponding normalization etc. operates.
Input data memory cell 102 is connected with computing unit array 107, for storing the calculating data for participating in calculating, The data include primitive character diagram data and participate in the data that intermediate layer is calculated;Output data memory cell 104 includes calculating The neuron response arrived;Weight memory cell 105 is used to store the neutral net weight trained;The location of instruction 106 storages participate in the command information calculated, and instruction is parsed to realize neural computing.Memory cell is adopted in the present invention Spin transfer torque magnetic memory is used, the memory is a kind of new non-volatile material, it has, and density is big, quiescent dissipation Low the characteristics of.
The multilayer STT-RAM memory cell schematic diagrames that Fig. 2 uses for the present invention.Multilayer STT-RAM units are by two stackings MTJ (MJT) device composition, each magnetic funnel node device includes reference layer and free layer two parts and constitutes, two layers Between have oxide be used as separation layer.The logical value of memory cell can be changed by changing the direction of magnetization of free layer, by two The logical value storage of (multilayer) magnetic funnel node device, which is combined, can represent two bits.It is noted that two magnetic Property tunnel junction element is of different sizes, when the circuit of formed objects flows through, the less MTJ free layer of size It is easier to reversion, the larger-size more difficult reversion of MTJ device free layer.The write operation of the memory cell is divided into the progress of two steps, first By changing firmly while two MTJ of switching state, if desired for second step is then carried out, small MTJ is only switched by soft conversion;Equally , the memory cell read operation is also classified into the progress of two steps, and MTJ resistance is compared first, and (MJT itself resistance refers to big MJT and small MJT all-in resistance) with reference resistance RR2 resistance size, Read Controller obtains big MJT state value from comparative result, then Compare the resistance size of MTJ resistance and reference resistance RR1 or RR3, Read Controller obtains small MJT state value.MSB is stored in In big MTJ, therefore the unit first reads out highest significant position (MSB).
The multilayer STT-RAM memory cell that the present invention is provided has three kinds of mode of operations, respectively multilevel-cell pattern (MLC patterns), single-bit pattern (SLC patterns) and state limit multiple-unit pattern (SR-MLC patterns).STT-RAM units are distinguished Using high-impedance state and low resistive state data storage 0 and 1.In multilevel-cell pattern, memory cell passes through vertical stacking two MTJ device represents four states;In single-bit pattern, represent to store logic using only the big MTJ device in mtj stack Value, that is, have two states;In state limit multiple-unit pattern, two MLC cells are used to store three-bit value, that is, have three shapes State.
In the neural network processor that the present invention is provided, three kinds of differences can be provided as the STT-RAM of storage organization Mode of operation, by switching signal P1, P2, P3, P4, MLC can be stored in Serial output in the storage in two MTJ devices Hold.
The storage system based on spin transfer torque magnetic memory that the present invention is provided has the effect of capacity extension. In MLC patterns, two MTJ both participate in data storage, therefore with highest storage density;SR-MLC moulds are mono- using two MLC Member storage three-bit value, therefore memory span is the 3/4 of MLC patterns;In SLC patterns, only big MTJ participates in data storage, Therefore memory capacity is only the 1/2 of MLC patterns, and storage density is minimum.
Neural network processor is a kind of accelerating engine suitable for approximate calculation, and the present invention is according to its operation principle and ties Close STT-RAM multi-operation mode feature, propose it is a kind of towards neural network processor based on spin transfer torque magnetic storage The data mapping structure of device.
Fig. 3 is data mapping structure proposed by the present invention.One digital data has 2N and is stored in N number of MLC cell, The MSB of the digital data is mapped in big MTJ, and LSB (least significant bit) is mapped in small MTJ, wherein in identical storage word The bit wide of data operand is variable.The data mapping structure has three kinds of accuracy modes, respectively high precision mode, low precision Pattern and medium accuracy pattern, when neural network processor is in high precision mode (MLC patterns), two in memory cell MJT both participates in data storage, and data bit width is 2N;When neural network processor is in low accuracy modes (SLC patterns), storage Only big MJT participates in data storage in unit, and data bit width is N;When neural network processor is in medium accuracy pattern, N Individual memory cell storage has 3/2N data.STT-RAM memories can be according to scale of neural network and computational accuracy (bit wide) It is required that switching between multiple mode of operations.
In MLC patterns, the 2N positional operands being stored in memory cell both participate in neural network computing, it is ensured that nerve net The precision of network processing, but sacrifice the memory access time (reading data needs two steps to complete);In SLC patterns or SR-MLC patterns, storage Word have lost half or 1/4 bit wide, data precision reduction respectively, but improve memory access speed.
According to data mapping structure proposed by the present invention, neural network processor has three kinds of accuracy modes, every kind of precision Operand of the pattern in on-chip memory is accessed on the premise of ensureing that word address is constant.
The present invention participates in the data of neural computing using the storage of Q forms.The form of Q forms is Qn.m, and wherein n is two The integer part of system number decimal, m is the fractional part of binary number decimal.In the present invention, n+m=2N, wherein 2N are number According to bit wide.
Based on above-mentioned storage system, the present invention proposes a kind of data path turn-off technique suitable for above-mentioned storage system. The data path of computing unit is divided into multiple autonomous channels, when STT-RAM switches between a variety of accuracy modes, data bit It is wide also corresponding to change, can be with matched data bit wide by way of being turned on and off partial data passage.When STT-RAM is from MLC When pattern switching is SLC or SR-MLC patterns, 1/2 or 1/4 data are abandoned in partial data, therefore can close the participation portion The data path that partite transport is calculated, reaches the purpose for saving power consumption.
Fig. 4 specifically describes data path shut-off proposed by the present invention so that two 12 bits participate in multiplying as an example Technology.Initial data (input data) is two 16 bits, when SR-MLC patterns are stored, has abandoned low 4 Data, retain high 12 data.16 multipliers include 48 multipliers, and each 8 multipliers include 44 multipliers. When carrying out multiplication operation, dash area shut-off is operated with the multiplication for adapting to 12 input datas in 16 multipliers.
Two operand initial data A16-0And B16-0For 16 positional operands, actually active position is 12, is abandoned in storage Low 4 data, according to SR-MLC patterns by low 12 of high 12 data storages to memory cell.
Specific workflow is as follows:
The data A of SR-MLC patterns16-0With data B16-0In least-significant byte A7-0And B7-0In being linked into eight multipliers 1., meter Calculate result P115-8In 8 multipliers being linked into as results of intermediate calculations 3., result of calculation P17-0It is used as final calculation result P31-0Least-significant byte P7-0
A15-8And B7-0In being linked into 8 multipliers 2., wherein A11-8It is linked into 4 multipliers 2-1 and 2-3, A15-12Connect Enter into 4 multipliers 2-2 and 2-4, B3-0It is linked into 4 multipliers 2-1 and 2-2, B7-4Be linked into 4 multiplier 2-3 and In 2-4, due to A15-12Without Effective Numerical, therefore 4 multipliers 2-2 and 2-4 are off state, result of calculation P27-0As During 3. results of intermediate calculations accesses to 8 multipliers, result of calculation P215-88 multipliers are accessed to as results of intermediate calculations 4. in;
A7-0And A15-8In being linked into 8 multipliers 3., wherein A3-0It is linked into 4 multipliers 3-1 and 3-3, A7-4Access Into 4 multipliers 3-2 and 3-4, B11-8It is linked into 4 multipliers 3-1 and 3-2, B15-12Be linked into 4 multiplier 3-3 and In 3-4, due to B15-12Without Effective Numerical, therefore 4 multipliers 3-3 and 3-4 are off state, result of calculation P315-8Make In 8 multipliers being accessed to for results of intermediate calculations 4., result of calculation P37-0It is used as final calculation result P31-0P15-8
A15-8And B15-8In being linked into 8 multipliers 4., wherein A11-8It is linked into 4 multipliers 4-1 and 4-3, A15-12Connect Enter into 4 multipliers 4-2 and 4-4, B11-8It is linked into 4 multipliers 4-1 and 4-2, B15-12It is linked into 4 multiplier 4-3 In 4-4, due to B15-12Without Effective Numerical, therefore 4 multipliers 4-2,4-3 and 4-4 are off state, result of calculation P415-8It is used as final calculation result P31-0P31-24, result of calculation P47-0It is used as final calculation result P31-0P23-16
It is below system embodiment corresponding with above method embodiment, present embodiment can be mutual with above-mentioned embodiment Coordinate and implement.The above-mentioned relevant technical details mentioned in mode of applying are still effective in the present embodiment, in order to reduce repetition, this In repeat no more.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in above-mentioned embodiment.
The invention also discloses a kind of Processing with Neural Network system based on spin transfer torque magnetic memory, including With lower unit:
Control unit, the operational order for needing to perform is read from memory cell, and will be to be calculated according to the operational order Input data writes the memory cell, and generates control signal;
Computing unit array, including multiple computing units, for obtaining the input data from the memory cell, with reference to this The calculating that control signal is performed in neural computing is operated, and is produced intermediate calculation data and is finally calculated data, and deposit should Memory cell;
Wherein the memory cell storage medium is multilayer spin transfer torque magnetic memory.
The Processing with Neural Network system based on spin transfer torque magnetic memory, wherein memory cell possesses multilayer list First memory module, single-bit memory module and state limit multiple-unit memory module, and according to Processing with Neural Network scale and meter Required precision is calculated between above-mentioned three kinds of memory modules to switch, wherein,
Whole MJT both participates in data storage in multilevel-cell memory module, memory cell, and data bit width is 2N;
Half MJT participates in data storage in single-bit memory module, memory cell, and data bit width is N;
3/4ths MJT participate in data storage, data bit in state limit multiple-unit memory module, each two memory cell A width of 3/2nds N.
The Processing with Neural Network system based on spin transfer torque magnetic memory, wherein storing the operation using Q forms Instruct, this finally calculates data and the intermediate calculation data, the form of the Q forms is Qn.m, and wherein n is binary number decimal Integer part, m is the fractional part of binary number decimal, and n+m=2N, 2N are data bit width.
The Processing with Neural Network system based on spin transfer torque magnetic memory, wherein control unit is additionally included in this When input data writes the memory cell, if the bit wide of the input data is more than the data bit width of memory cell, this is abandoned defeated Enter the low data in data, and turn off in computing unit array computation the computing unit for calculating the low data.
The Processing with Neural Network system based on spin transfer torque magnetic memory, wherein arithmetic operation multiplies including vector Add operation, pondization operation and local corresponding normalization operation.
In summary, the present invention is for operational data scale present in neural network processor is big, Resources on Chip demand The problems such as consumption of high and circuit energy is big, proposes a kind of neural network processor based on spin transfer torque magnetic memory, Ensure neural computing precision simultaneously, reduction Resources on Chip expense and energy loss.
Although the present invention is disclosed with above-described embodiment, specific embodiment only to explain the present invention, is not used to limit The present invention, any those skilled in the art of the present technique without departing from the spirit and scope of the invention, can make the change and complete of some It is kind, therefore the scope of the present invention is defined by claims.

Claims (10)

1. a kind of Processing with Neural Network method based on spin transfer torque magnetic memory, it is characterised in that comprise the following steps:
Step S1, the operational order for needing to perform is read from memory cell, and according to the operational order by input number to be calculated According to the write-in memory cell, and generate control signal;
Step S2, obtains the input data from the memory cell, and the meter in neural computing is performed with reference to the control signal Operation is calculated, intermediate calculation data is produced and finally calculates data, and be stored in the memory cell;
Wherein the memory cell storage medium is multilayer spin transfer torque magnetic memory.
2. the Processing with Neural Network method as claimed in claim 1 based on spin transfer torque magnetic memory, it is characterised in that The memory cell possesses multilevel-cell memory module, single-bit memory module and state limit multiple-unit memory module, and according to Processing with Neural Network scale and computational accuracy requirement switch between above-mentioned three kinds of memory modules, wherein,
Whole MJT both participates in data storage in multilevel-cell memory module, each memory cell, and data bit width is 2N;
Half MJT participates in data storage in single-bit memory module, each memory cell, and data bit width is N;
3/4ths MJT participate in data storage in state limit multiple-unit memory module, each two memory cell, and data bit width is 3/2nds N.
3. the Processing with Neural Network method as claimed in claim 1 based on spin transfer torque magnetic memory, it is characterised in that Using Q forms store the operational order, this finally calculate data and the intermediate calculation data, the forms of the Q forms is Qn.m, its Middle n is the integer part of binary number decimal, and m is the fractional part of binary number decimal, and n+m=2N, 2N are data bit width.
4. the Processing with Neural Network method as claimed in claim 1 based on spin transfer torque magnetic memory, it is characterised in that When step S1 is additionally included in the input data and writes the memory cell, if the bit wide of the input data is more than the data of memory cell Bit wide, then abandon the low data in the input data, and cancels the calculating for the low data in step s 2.
5. the Processing with Neural Network method as claimed in claim 1 based on spin transfer torque magnetic memory, it is characterised in that Calculating operation includes the multiply-add operation of vector, pondization operation and local corresponding normalization operation.
6. a kind of Processing with Neural Network system based on spin transfer torque magnetic memory, it is characterised in that including with lower unit:
Control unit, the operational order for needing to perform is read from memory cell, and according to the operational order by input to be calculated Data write the memory cell, and generate control signal;
Computing unit array, including multiple computing units, for obtaining the input data from the memory cell, with reference to the control Signal performs the calculating operation in neural computing, produces intermediate calculation data and finally calculates data, and is stored in the storage Unit;
Wherein the memory cell storage medium is multilayer spin transfer torque magnetic memory.
7. the Processing with Neural Network system as claimed in claim 1 based on spin transfer torque magnetic memory, it is characterised in that The memory cell possesses multilevel-cell memory module, single-bit memory module and state limit multiple-unit memory module, and according to Processing with Neural Network scale and computational accuracy requirement switch between above-mentioned three kinds of memory modules, wherein,
Whole MJT both participates in data storage in multilevel-cell memory module, memory cell, and data bit width is 2N;
Half MJT participates in data storage in single-bit memory module, memory cell, and data bit width is N;
3/4ths MJT participate in data storage in state limit multiple-unit memory module, each two memory cell, and data bit width is 3/2nds N.
8. the Processing with Neural Network system as claimed in claim 1 based on spin transfer torque magnetic memory, it is characterised in that Using Q forms store the operational order, this finally calculate data and the intermediate calculation data, the forms of the Q forms is Qn.m, its Middle n is the integer part of binary number decimal, and m is the fractional part of binary number decimal, and n+m=2N, 2N are data bit width.
9. the Processing with Neural Network system as claimed in claim 7 based on spin transfer torque magnetic memory, it is characterised in that When the control unit is additionally included in the input data and writes the memory cell, if the bit wide of the input data is more than memory cell Data bit width, then abandon the low data in the input data, and turns off in computing unit array computation low for calculating this The computing unit of position data.
10. the Processing with Neural Network system as claimed in claim 6 based on spin transfer torque magnetic memory, its feature exists In the arithmetic operation includes the multiply-add operation of vector, pondization operation and local corresponding normalization operation.
CN201710182534.4A 2017-03-24 2017-03-24 Processing with Neural Network method and system based on spin transfer torque magnetic memory Pending CN107103358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710182534.4A CN107103358A (en) 2017-03-24 2017-03-24 Processing with Neural Network method and system based on spin transfer torque magnetic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710182534.4A CN107103358A (en) 2017-03-24 2017-03-24 Processing with Neural Network method and system based on spin transfer torque magnetic memory

Publications (1)

Publication Number Publication Date
CN107103358A true CN107103358A (en) 2017-08-29

Family

ID=59675676

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710182534.4A Pending CN107103358A (en) 2017-03-24 2017-03-24 Processing with Neural Network method and system based on spin transfer torque magnetic memory

Country Status (1)

Country Link
CN (1) CN107103358A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108256645A (en) * 2018-01-19 2018-07-06 上海兆芯集成电路有限公司 The adaptable processor of data bit width
CN108288091A (en) * 2018-01-19 2018-07-17 上海兆芯集成电路有限公司 Adopt the microprocessor of booth multiplication
CN109147839A (en) * 2018-08-17 2019-01-04 湖南毂梁微电子有限公司 A kind of apparatus and system for having both Yi Xin and calculating with random storage access function

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101657859A (en) * 2007-04-05 2010-02-24 高通股份有限公司 Spin transfer torque magnetoresistive random access memory and design methods
CN101878506A (en) * 2007-10-17 2010-11-03 高通股份有限公司 Ground level precharge bit line scheme for read operation in spin transfer torque magnetoresistive random access memory
CN103917992A (en) * 2011-11-09 2014-07-09 高通股份有限公司 Method and apparatus for using memory in probabilistic manner to store synaptic weights of neural network
CN106529670A (en) * 2016-10-27 2017-03-22 中国科学院计算技术研究所 Neural network processor based on weight compression, design method, and chip

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101657859A (en) * 2007-04-05 2010-02-24 高通股份有限公司 Spin transfer torque magnetoresistive random access memory and design methods
CN101878506A (en) * 2007-10-17 2010-11-03 高通股份有限公司 Ground level precharge bit line scheme for read operation in spin transfer torque magnetoresistive random access memory
CN103917992A (en) * 2011-11-09 2014-07-09 高通股份有限公司 Method and apparatus for using memory in probabilistic manner to store synaptic weights of neural network
CN106529670A (en) * 2016-10-27 2017-03-22 中国科学院计算技术研究所 Neural network processor based on weight compression, design method, and chip

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LILI SONG等: "STT-RAM Buffer Design for Precision-Tunable", 《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108256645A (en) * 2018-01-19 2018-07-06 上海兆芯集成电路有限公司 The adaptable processor of data bit width
CN108288091A (en) * 2018-01-19 2018-07-17 上海兆芯集成电路有限公司 Adopt the microprocessor of booth multiplication
CN108256645B (en) * 2018-01-19 2021-02-26 上海兆芯集成电路有限公司 Processor with adjustable data bit width
CN109147839A (en) * 2018-08-17 2019-01-04 湖南毂梁微电子有限公司 A kind of apparatus and system for having both Yi Xin and calculating with random storage access function
CN109147839B (en) * 2018-08-17 2020-07-07 湖南毂梁微电子有限公司 Device and system with Yixin calculation and random access functions

Similar Documents

Publication Publication Date Title
Zabihi et al. In-memory processing on the spintronic CRAM: From hardware design to application mapping
CN105892989B (en) Neural network accelerator and operational method thereof
JP6773568B2 (en) Arithmetic system and neural network arithmetic method
US20180095930A1 (en) Field-Programmable Crossbar Array For Reconfigurable Computing
Bavikadi et al. A review of in-memory computing architectures for machine learning applications
Angizi et al. IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network
CN109766309B (en) Spin-save integrated chip
CN107423816A (en) A kind of more computational accuracy Processing with Neural Network method and systems
Chang et al. PXNOR-BNN: In/with spin-orbit torque MRAM preset-XNOR operation-based binary neural networks
CN108665063B (en) Bidirectional parallel processing convolution acceleration system for BNN hardware accelerator
CN110390388A (en) Neuromorphic circuit with 3D stacked structure and the semiconductor device including it
CN108446764B (en) Novel neuromorphic chip architecture
Miyashita et al. Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology
Mao et al. MAX 2: An ReRAM-based neural network accelerator that maximizes data reuse and area utilization
Ryu et al. Bitblade: Energy-efficient variable bit-precision hardware accelerator for quantized neural networks
CN107103358A (en) Processing with Neural Network method and system based on spin transfer torque magnetic memory
Ma et al. An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computing
Yan et al. iCELIA: A full-stack framework for STT-MRAM-based deep learning acceleration
Samiee et al. Low-energy acceleration of binarized convolutional neural networks using a spin hall effect based logic-in-memory architecture
Angizi et al. Pisa: A binary-weight processing-in-sensor accelerator for edge image processing
Song et al. STT-RAM buffer design for precision-tunable general-purpose neural network accelerator
Ollivier et al. CORUSCANT: Fast efficient processing-in-racetrack memories
Zhao et al. NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration
Roy et al. PIM-DRAM: Accelerating machine learning workloads using processing in commodity DRAM
Ali et al. Compute-in-memory technologies and architectures for deep learning workloads

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20170829

WD01 Invention patent application deemed withdrawn after publication