CN106529670A - Neural network processor based on weight compression, design method, and chip - Google Patents
Neural network processor based on weight compression, design method, and chip Download PDFInfo
- Publication number
- CN106529670A CN106529670A CN201610958305.2A CN201610958305A CN106529670A CN 106529670 A CN106529670 A CN 106529670A CN 201610958305 A CN201610958305 A CN 201610958305A CN 106529670 A CN106529670 A CN 106529670A
- Authority
- CN
- China
- Prior art keywords
- weight
- data
- memory element
- neural network
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Data Mining & Analysis (AREA)
- Artificial Intelligence (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- Computational Linguistics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Neurology (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
Abstract
The invention brings forward a neural network processor based on weight compression, a design method, and a chip. The processor comprises at least one storage unit used for storing operation instructions and data participating in calculation; at least one storage unit controller used for controlling the storage unit; at least one calculation unit used for executing calculation operation of a neural network; a control unit connected with the storage unit controller and the calculation unit for obtaining the instructions stored by the storage unit via the storage unit controller and analyzing the instructions so as to control the calculation unit; and at least one weight retrieval unit used for retrieving weights, wherein each weight retrieval unit is connected with the calculation unit so as to ensure correct operation on the compressed weights and the corresponding data. According to the invention, less weight resources in a neural network processor are occupied, the operation speed is improved, and the energy efficiency is improved.
Description
Technical field
The present invention relates to the hardware-accelerated field that neural network model is calculated, more particularly to a kind of god compressed based on weight
Jing network processing units, method for designing, chip.
Background technology
Deep learning is the important branch in machine learning field, and important breakthrough is achieved in the last few years.Using depth
The neural network model of Algorithm for Training is practised since the proposition in the applications such as image recognition, speech processes, intelligent robot
Achieve the achievement for attracting people's attention.
Deep neural network by setting up the neural attachment structure of modeling human brain, process image, sound and
During the signals such as text, data characteristicses are described by the layering of multiple conversion stages.With the continuous of neutral net complexity
Improve, nerual network technique has that in actual application occupancy resource is more, arithmetic speed is slow, energy expenditure,
Therefore there is serious efficiency and computing speed in the technology when the field such as embedded device or low overhead data center is applied
Degree bottleneck.Using it is hardware-accelerated substitute traditional software calculate method become improve neural computing efficiency a kind of row it
Effective means.The hardware-accelerated mode of main flow includes graphics processing unit, application specific processor chip and field programmable logic
Array (FPGA) etc..
In existing nerual network technique, neural network model carries out many wheel training according to sample order according to training set
Obtain neutral net weighted value.Neutral net weight has certain openness, there is the weight that big numerical quantity is 0, these power
Weight does not produce impact numerically after the computing such as multiplication and addition with data to operation result.Weight in these neutral nets
Weighted value for 0 is relevant with the inherent character of deep neural network, is obtained by repeatedly training, and is difficult from algorithm angle to eliminate.
These numerical value be 0 weight in storage, be loaded into and when the process such as computing can take a large amount of Resources on Chip, consume unnecessary work
Between, it is difficult to meet the performance requirement of neural network processor.
Therefore no matter in academia or industrial quarters, it is 0 element for numerical value in above-mentioned neutral net, has carried out and ground in a large number
Study carefully.Document " Albericio J, Judd P, Hetherington T, et al.Cnvlutin:ineffectual-neuron-
free deep neural network computing[C]//Computer Architecture(ISCA),2016ACM/
IEEE 43rd Annual International Symposium on.IEEE,2016:1-13. " is big by providing on piece
The memory element of scale is realized Large-scale parallel computing and realizes the compression to data element based on this, but relies on piece
Upper large-scale memory element, meets the demand in parallel computation, is not suitable for embedded device；Document " Chen Y H,
Emer J,Sze V.Eyeriss:A Spatial Architecture for Energy-Efficient Dataflow for
Convolutional Neural Networks [J] .2016. " realize data reusing and using electricity by shared data and weight
The method of source gate closes the calculating of element 0, can effectively improve energy efficiency, but the method can only reduce computing power consumption without
Method is skipped data 0 and then accelerates calculating speed.
Invention " a kind of neutral net accelerator and its operation method ", the invention are applied to neural network algorithm field, carry
A kind of neutral net accelerator and its operation method are supplied, the neutral net accelerator includes address in piece internal memory storage media, piece
Index module, core calculation module and many ALU devices, piece internal memory storage media, for storing the outside data for transmitting or being used for
The data produced in storage computation process；Data directory module in piece, mapped to according to the index of input during computing for performing
Correct storage address；Core calculation module is used to perform neural network computing；Many ALU devices for from core calculation module or
Piece internal memory storage media obtains input data and performs the nonlinear operation that core calculation module cannot be completed.The invention is in neutral net
Many ALU designs are introduced in accelerator, so as to lift the arithmetic speed of nonlinear operation so that neutral net accelerator is more increased
Effect.The present invention is that weight compression storage organization is introduced in neutral net accelerator with the maximum difference of the invention, is improve
Neural network computing speed simultaneously reduces energy loss.
Invention " accelerates the arithmetic unit and method of the speed-up chip of deep neural network algorithm ", and the invention provides a kind of adding
The arithmetic unit and method of the speed-up chip of fast deep neural network algorithm, described device include：Vector addition processor module,
The computing of the vectorization of the pooling layer algorithms entered in the addition or subtraction, and/or deep neural network algorithm of row vector；To
Flow function value arithmetic device module, the vector quantities operation of the non-linear evaluation in deep neural network algorithm；Vectorial adder and multiplier module,
Enter the multiply-add operation of row vector；Three modules perform programmable instructions, interact with each other to calculate the neuron of neutral net
Value and network output result and, represent synapse weight variable quantity of the input layer to output layer neuron operation intensity；
Intermediate value memory area is provided with three modules, and main storage is read out and write operation.Thereby, it is possible to
Reduce the intermediate value to main storage and read and write number of times, reduce the energy expenditure of accelerator chip, it is to avoid data processing
Shortage of data and replacement problem in journey.The present invention is that power is introduced in neutral net accelerator with the maximum difference of the invention
Weight contracting storage organization, improves neural network computing speed and reduces energy loss.
The content of the invention
For the drawbacks described above of existing neural network processor, the present invention proposes a kind of neutral net compressed based on weight
Processor, method for designing, chip, the system introduce weight index structure, Jin Erti in existing neural network processor system
The arithmetic speed and energy loss of neutral net acceleration are risen.
The present invention proposes a kind of neural network processor compressed based on weight, including：
At least one memory element, for storing operational order and participating in the data for calculating；
At least one memory element controller, for being controlled to the memory element；
At least one computing unit, the calculating for performing neutral net are operated；
Control unit, is connected with the computing unit with the memory element controller, for via the memory element
Controller obtains the instruction of the memory element storage, and parses the instruction to control the computing unit；
At least one weight retrieval unit, for entering line retrieval to weight, wherein each described weight retrieval unit and institute
State computing unit to be connected, it is ensured that the weight compressed and the correct computing of corresponding data.
The memory element includes that input data memory element, output data memory element, weight memory element, instruction are deposited
Storage unit.
The input data memory element is used to store the data for participating in and calculating, and the data that the participation is calculated include
Primitive character diagram data and the data for participating in intermediate layer calculating；The output data memory element includes calculating the neuron for obtaining
Response value；The weight memory element is used for the neutral net weight that storage has been trained；The location of instruction is used for
Storage participates in the command information for calculating.
The data for calculating that participate in are recoded by the method for offline compression under piece, by weight compressed format
Realize that weight is compressed.
The weight compressed format includes<Weight, side-play amount>.
Weight in the weight compressed format is original value of the neutral net weight before being compressed, and the side-play amount is
The relative position of current non-zero weight in one group of weighted value.
In weight compression process, the weight value sequence through recompiling acquisition is not retained the element that numerical value is zero,
Only retain nonzero element.
The computing unit obtains data to be calculated from the input data memory element associated there, and
And data are write to the output data memory element associated there.
The present invention also proposes a kind of method for designing of the neural network processor compressed based on weight described in design, including：
Step 1, described control unit are addressed that to the memory element reading and parse next step needs the finger of execution
Order；
Step 2, obtains storage address according to the instruction for parsing, and the participation calculating is obtained from the memory element
Data and weight；
Step 3, the data for participating in calculating are stored from the input memory element with the weight respectively with weight
Unit is loaded into the computing unit；
Step 4, the computing unit perform the arithmetic operation in neural network computing, wherein single by weight retrieval
Unit ensure that the data compressed can be computed correctly with weighted data；
Step 5, neural computing result is stored in the output memory element.
The present invention also proposes a kind of chip including the neural network processor compressed based on weight.
From above scheme, it is an advantage of the current invention that：
The present invention for arithmetic speed present in neural network processor is poor, low this problem of energy efficiency, by from
The mode of wire compression, it is outer by neutral net weight boil down to weight compressed format in piece, weigh in reducing neural network processor
The occupancy of weight resource, improves arithmetic speed, improves energy efficiency.
Description of the drawings
The neural network processor structured flowchart that Fig. 1 is provided for the present invention；
Fig. 2 compresses storage format figure for a kind of weight proposed by the present invention；
Fig. 3 is weight compression unit schematic diagram in present invention list computing unit embodiment；
Fig. 4 is weight compression unit schematic diagram in multioperation unit embodiment of the present invention；
Fig. 5 is the structural representation of computing unit of the present invention；
Fig. 6 is the flow chart that neural network processor proposed by the present invention carries out neural network computing.
Specific embodiment
When studying to neural network processor, it is found that neutral net weight has certain openness, there are a large amount of numbers
It is worth the weight for 0, these weights do not produce impact numerically after the computing such as multiplication and addition with data to operation result,
These numerical value be 0 weight in storage, be loaded into and when the process such as computing can take a large amount of Resources on Chip, consume unnecessary work
Between, it is difficult to meet the performance requirement of neural network processor.
Discovery is analyzed through the computation structure to existing neural network processor, neutral net weighted value can be entered
Row compression, realizes accelerating arithmetic speed, reduces the purpose of energy loss, and prior art provides the basic frame of neutral net accelerator
Structure, the present invention propose a kind of weight compression storage format in prior art basis, and weighted data is being deposited after recodification
Storage format is compressed using weight in storage, transmission and calculating process, and increases weight index structure in neural computing unit,
Ensure that the weight after being compressed can be with the correct computing of data element.
For achieving the above object, the present invention proposes a kind of neural network processor compressed based on weight, including：
At least one memory element, for storing operational order and participating in the data for calculating；
At least one computing unit, for performing neural computing；And control unit, with least one memory element
Controller is connected with least one computing unit, for via at least one memory element controller obtain described in extremely
The instruction of few memory element storage, and parse the instruction to control at least one computing unit；
At least one weight retrieval unit, wherein each weight retrieval unit are connected with least one computing unit,
The weight compressed by guarantee and the correct computing of corresponding data；
Neural network processor system of the invention, the weight are the neutral net weight for having trained.
Neural network processor of the invention, when the neural network processor carries out neural computing,
The neutral net weight for training can be compressed to weight compressed format outside piece, and store in the memory unit.
The present invention using by the way of offline compression under piece by neutral net weight boil down to weight compressed format, and pass through
Input interface transmits the memory element to piece.
In order that the purpose of the present invention, technical scheme, method for designing and advantage are of greater clarity, it is logical below in conjunction with accompanying drawing
The present invention is described in more detail to cross specific embodiment, it will be appreciated that specific embodiment described herein is only to explain
The present invention, is not intended to limit the present invention.
The present invention is intended to provide a kind of neural network processor compressed based on weight, which is in Processing with Neural Network system
Introduce weight retrieval unit and using weight compression storage format storage neutral net weight, so as to reduce storage overhead on piece,
Reduce computing circuit scale and improve operation efficiency so that Processing with Neural Network systematic function is higher efficiently.
Structure of the Processing with Neural Network that the present invention is provided based on storage-control-calculating；
Storage organization is used to store data and the coprocessor operation instruction for participating in calculating；
Control structure includes decoding circuit, for parsing operational order, generates control signal with the tune of data in control sheet
Degree and storage and neural computing process；
Computation structure includes ALU, for participating in the operation of the neural computing in the processor, compresses number
Operate according to realizing calculating in computation structure.
The present invention also proposes a kind of chip comprising the neural network processor compressed based on weight
A kind of neural network processor 101 that Fig. 1 is provided for the present invention, the system architecture are made up of six parts, including
Input data memory element 102, control unit 103, output data memory element 104, weight memory element 105, instruction storage
Unit 106, computing unit 107.
Input data memory element 102 be used for store participate in calculate data, the data include primitive character diagram data and
Participate in the data that intermediate layer calculates；Output data memory element 104 includes calculated neuron response value；Weight storage is single
Unit 105 is used for the neutral net weight that storage has been trained；The location of instruction 106 stores the command information for participating in calculating,
Instruction is parsed to realize neural computing.
Control unit 103 respectively with output data memory element 104, weight memory element 105, the location of instruction 106,
Computing unit 107 is connected, and control unit 103 obtains the instruction that is stored in the location of instruction 106 and parses the instruction, controls
Unit processed 103 can carry out neural computing according to the control signal control computing unit that analysis instruction is obtained.
Computing unit 107 performs corresponding neural computing for the control signal that produces according to control unit 103.
Computing unit 107 is associated with one or more memory element, and computing unit 107 can be deposited from input data associated there
Data storage part in storage unit 102 obtains data to be calculated, and can be to the associated output data storage
Unit 104 writes data.Computing unit 107 completes the most of computing in neural network algorithm, i.e., vectorial multiply-add operation etc., this
Outward, due to being loaded in computing unit 107 the weight form for participating in calculating for weight compressed format, therefore in computing unit 107
In should also include that weight retrieves subelement, the subelement is used to ensure that the weight compressed can be computed correctly with weight.
Fig. 2 is a kind of weight compressed format proposed by the present invention, initial data is entered by the method for offline compression under piece
Row is recoded, and then realizes that weight is compressed.The weight compressed format includes<Weight, side-play amount>Two parts are constituted, and weight is god
Original value of the Jing network weights before being compressed, side-play amount are the relative position of current non-zero weight in one group of weighted value.In pressure
In compression process, obtain weight value sequence and do not retained the element that numerical value is zero through recompiling, only retain nonzero element, the party
Method ensure that only non-zero weight value participates in neural computing, is compressed by weight, effectively reduces weight quantity in data,
Neural computing amount is reduced, system integral operation speed is improve.
The weight compression process is described in detail by Fig. 3.Weight is grouped, per the first prime number in group by computing unit
Scale determine.Now weight compression process is described in detail so that every group of weight is comprising four elements as an example, in first group of weight, number
It is worth element respectively the 0th and the 1st element for 1.5 and 2.5, therefore after recompiling, this group of weight remains two
Nonzero element, the side-play amount for indicating element position are respectively 0 and 1；Three non-zeros are included in second group of original weighted data
Element, is the 0th, the 3rd and the 4th element in this group of data, therefore side-play amount is respectively 0,3 and 4.In the 3rd group of weight
In value, comprising 3 and 4 two nonzero elements, side-play amount is respectively 2 and 3.
When computing unit resource is enough, i.e., when possessing multiple computing units simultaneously, the weighted value of multiple different queues can
It is loaded in different computing units simultaneously, in different queue, the elements in parallel work of same order position, is independent of each other, packet side
Formula is identical with single computing unit, and the element in each queue in identical relative position is divided into a group, is calculating
Cheng Zhong, in each queue, the data parallel of different queue is loaded in computing unit.
For convenience of describing, Fig. 4 illustrates many computing unit situations by taking two computing units as an example, and two weights are included in Fig. 4
Queue, each queue weight are respectively connected to into corresponding computing unit, and each computing unit works independently.According to computing unit
Amount of capacity, weight are divided into four groups, and in every group of weight, the weighted value of each queue is according to identical group interior element length point
Do not compress.
There are 2 points of advantages with weight compressed format storage weight, the nonzero element in weight is only stored first, can significantly
Reduce EMS memory occupation；Secondly, only nonzero element is loaded in computing unit, improves calculating speed and improve computing unit
Utilization rate.
Fig. 5 is computing unit structural representation, describe weight and data carry out it is corresponding when convolutional neural networks are calculated
Relation, in the calculating process, in each computing unit, different weighted values is linked into each computing unit for data sharing
In, each computing unit concurrent working.
Fig. 6 is a kind of flow chart of neural computing process of the invention, and the method includes：
Step S1, control unit are addressed to memory element, read and parse the instruction that next step needs to perform；
Step S2, obtains input data from memory element according to the storage address that analysis instruction is obtained；
Data and weight are loaded into computing unit from input memory element and weight memory element by step S3 respectively；
Step S4, computing unit perform neural network computing in arithmetic operation, wherein data retrieval structure ensure that by
The data of compression can be computed correctly with weighted data；
Step S5, will be stored in output memory element with neural computing result.
In sum, the present invention is for arithmetic speed present in neural network processor is poor, low this of energy efficiency is asked
Topic, it is by way of offline compression, outer by neutral net weight boil down to weight compressed format in piece, reduce at neutral net
In reason device, the occupancy of weight resource, improves arithmetic speed, improves energy efficiency.
It should be understood that, although this specification is described according to each embodiment, but not each embodiment only includes one
Individual independent technical scheme, this narrating mode of description is only that those skilled in the art will should say for clarity
Bright book as an entirety, the technical scheme in each embodiment can also Jing it is appropriately combined, forming those skilled in the art can be with
The other embodiment of understanding.
Schematically specific embodiment of the invention is the foregoing is only, the scope of the present invention is not limited to.It is any
Those skilled in the art, the equivalent variations made on the premise of the design without departing from the present invention and principle, modification and combination,
The scope of protection of the invention all should be belonged to.
Claims (10)
1. it is a kind of based on weight compress neural network processor, it is characterised in that include：
At least one memory element, for storing operational order and participating in the data for calculating；
At least one memory element controller, for being controlled to the memory element；
At least one computing unit, the calculating for performing neutral net are operated；
Control unit, is connected with the computing unit with the memory element controller, for controlling via the memory element
Device obtains the instruction of the memory element storage, and parses the instruction to control the computing unit；
At least one weight retrieval unit, for entering line retrieval to weight, wherein each described weight retrieval unit and the meter
Calculate unit to be connected, it is ensured that the weight compressed and the correct computing of corresponding data.
2. the neural network processor for being compressed based on weight as claimed in claim 1, it is characterised in that the memory element bag
Include input data memory element, output data memory element, weight memory element, the location of instruction.
3. the neural network processor for being compressed based on weight as claimed in claim 2, it is characterised in that the input data is deposited
Storage unit is used to store the data for participating in and calculating, during the data that the participation is calculated include primitive character diagram data and participate in
The data that interbed is calculated；The output data memory element includes calculating the neuron response value for obtaining；The weight storage is single
The neutral net weight that unit has been trained for storage；The location of instruction is used to store the instruction letter for participating in calculating
Breath.
4. the neural network processor for being compressed based on weight as claimed in claim 1, it is characterised in that by being pressed under piece offline
The method of contracting is recoded to the data for calculating that participate in, and realizes that weight is compressed by weight compressed format.
5. the neural network processor for being compressed based on weight as claimed in claim 4, it is characterised in that the weight compresses lattice
Formula includes<Weight, side-play amount>.
6. the neural network processor for being compressed based on weight as claimed in claim 5, it is characterised in that the weight compresses lattice
Weight in formula is original value of the neutral net weight before being compressed, and the side-play amount is current non-zero power in one group of weighted value
The relative position of weight.
7. the neural network processor for being compressed based on weight as claimed in claim 4, it is characterised in that in weight compression process
In, the weight value sequence through recompiling acquisition is not retained the element that numerical value is zero, only retains nonzero element.
8. the as claimed in claim 2 neural network processor compressed based on weight, it is characterised in that the computing unit from
Data are obtained in the input data memory element associated there to be calculated, and to associated there described defeated
Go out data storage cell write data.
9. it is a kind of design as described in claim 1-8 any one based on weight compress neural network processor design side
Method, it is characterised in that include：
Step 1, described control unit are addressed that to the memory element reading and parse next step needs the instruction of execution；
Step 2, obtains storage address according to the instruction for parsing, and the number for participating in and calculating is obtained from the memory element
According to weight；
Step 3, by the data for participating in calculating with weight respectively from the input memory element and the weight memory element
It is loaded into the computing unit；
Step 4, the computing unit perform the arithmetic operation in neural network computing, wherein being protected by the weight retrieval unit
Demonstrate,prove the data compressed to be computed correctly with weighted data；
Step 5, neural computing result is stored in the output memory element.
10. it is a kind of including as described in claim 1-8 any one based on weight compress neural network processor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610958305.2A CN106529670B (en) | 2016-10-27 | 2016-10-27 | It is a kind of based on weight compression neural network processor, design method, chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610958305.2A CN106529670B (en) | 2016-10-27 | 2016-10-27 | It is a kind of based on weight compression neural network processor, design method, chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106529670A true CN106529670A (en) | 2017-03-22 |
| CN106529670B CN106529670B (en) | 2019-01-25 |
Family
ID=58325737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610958305.2A Active CN106529670B (en) | 2016-10-27 | 2016-10-27 | It is a kind of based on weight compression neural network processor, design method, chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106529670B (en) |
Cited By (61)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107016175A (en) * | 2017-03-23 | 2017-08-04 | 中国科学院计算技术研究所 | It is applicable the Automation Design method, device and the optimization method of neural network processor |
| CN107086910A (en) * | 2017-03-24 | 2017-08-22 | 中国科学院计算技术研究所 | A kind of weight encryption and decryption method and system for Processing with Neural Network |
| CN107092961A (en) * | 2017-03-23 | 2017-08-25 | 中国科学院计算技术研究所 | A kind of neural network processor and design method based on mode frequency statistical coding |
| CN107103113A (en) * | 2017-03-23 | 2017-08-29 | 中国科学院计算技术研究所 | Towards the Automation Design method, device and the optimization method of neural network processor |
| CN107103358A (en) * | 2017-03-24 | 2017-08-29 | 中国科学院计算技术研究所 | Processing with Neural Network method and system based on spin transfer torque magnetic memory |
| CN107423816A (en) * | 2017-03-24 | 2017-12-01 | 中国科学院计算技术研究所 | A kind of more computational accuracy Processing with Neural Network method and systems |
| CN107491811A (en) * | 2017-09-01 | 2017-12-19 | 中国科学院计算技术研究所 | Method and system and neural network processor for accelerans network processing unit |
| CN107578098A (en) * | 2017-09-01 | 2018-01-12 | 中国科学院计算技术研究所 | Neural network processor based on systolic arrays |
| CN107622305A (en) * | 2017-08-24 | 2018-01-23 | 中国科学院计算技术研究所 | Processor and processing method for neutral net |
| CN107679621A (en) * | 2017-04-19 | 2018-02-09 | 北京深鉴科技有限公司 | Artificial neural network processing unit |
| CN107729995A (en) * | 2017-10-31 | 2018-02-23 | 中国科学院计算技术研究所 | Method and system and neural network processor for accelerans network processing unit |
| CN107800700A (en) * | 2017-10-27 | 2018-03-13 | 中国科学院计算技术研究所 | A kind of router and network-on-chip Transmission system and method |
| CN107844829A (en) * | 2017-10-31 | 2018-03-27 | 中国科学院计算技术研究所 | Method and system and neural network processor for accelerans network processing unit |
| CN107918794A (en) * | 2017-11-15 | 2018-04-17 | 中国科学院计算技术研究所 | Neural network processor based on computing array |
| CN107944555A (en) * | 2017-12-07 | 2018-04-20 | 广州华多网络科技有限公司 | Method, storage device and the terminal that neutral net is compressed and accelerated |
| CN107977704A (en) * | 2017-11-10 | 2018-05-01 | 中国科学院计算技术研究所 | Weighted data storage method and the neural network processor based on this method |
| CN108171328A (en) * | 2018-03-02 | 2018-06-15 | 中国科学院计算技术研究所 | A kind of convolution algorithm method and the neural network processor based on this method |
| CN108205704A (en) * | 2017-09-27 | 2018-06-26 | 深圳市商汤科技有限公司 | A kind of neural network chip |
| CN108334945A (en) * | 2018-01-30 | 2018-07-27 | 中国科学院自动化研究所 | The acceleration of deep neural network and compression method and device |
| CN108416425A (en) * | 2018-02-02 | 2018-08-17 | 浙江大华技术股份有限公司 | A kind of convolution method and device |
| CN108510058A (en) * | 2018-02-28 | 2018-09-07 | 中国科学院计算技术研究所 | Weight storage method in neural network and the processor based on this method |
| CN108647774A (en) * | 2018-04-23 | 2018-10-12 | 福州瑞芯微电子股份有限公司 | A kind of neural network method and circuit of optimization sparsity matrix operation |
| CN108734288A (en) * | 2017-04-21 | 2018-11-02 | 上海寒武纪信息科技有限公司 | A kind of operation method and device |
| CN108764454A (en) * | 2018-04-28 | 2018-11-06 | 中国科学院计算技术研究所 | The Processing with Neural Network method compressed and/or decompressed based on wavelet transformation |
| CN109146069A (en) * | 2017-06-16 | 2019-01-04 | 上海寒武纪信息科技有限公司 | Arithmetic unit, operation method and chip |
| CN109325590A (en) * | 2018-09-14 | 2019-02-12 | 中国科学院计算技术研究所 | For realizing the device for the neural network processor that computational accuracy can be changed |
| CN109492761A (en) * | 2018-10-30 | 2019-03-19 | 深圳灵图慧视科技有限公司 | Realize FPGA accelerator, the method and system of neural network |
| CN109543140A (en) * | 2018-09-20 | 2019-03-29 | 中国科学院计算技术研究所 | A kind of convolutional neural networks accelerator |
| CN109557996A (en) * | 2017-09-22 | 2019-04-02 | 株式会社东芝 | Arithmetic unit |
| CN109726805A (en) * | 2017-10-30 | 2019-05-07 | 上海寒武纪信息科技有限公司 | The method for carrying out neural network processor design using black box simulator |
| CN109791628A (en) * | 2017-12-29 | 2019-05-21 | 清华大学 | Neural network model splits' positions method, training method, computing device and system |
| CN109886416A (en) * | 2019-02-01 | 2019-06-14 | 京微齐力(北京)科技有限公司 | The System on Chip/SoC and machine learning method of integrated AI's module |
| CN110045960A (en) * | 2018-01-16 | 2019-07-23 | 腾讯科技（深圳）有限公司 | Instruction set processing method, device and storage medium based on chip |
| CN110046702A (en) * | 2018-01-17 | 2019-07-23 | 联发科技股份有限公司 | Neural computing accelerator and its method of execution |
| US10387298B2 (en) | 2017-04-04 | 2019-08-20 | Hailo Technologies Ltd | Artificial neural network incorporating emphasis and focus techniques |
| CN110334716A (en) * | 2019-07-04 | 2019-10-15 | 北京迈格威科技有限公司 | Characteristic pattern processing method, image processing method and device |
| CN110428047A (en) * | 2018-05-01 | 2019-11-08 | 半导体组件工业公司 | Nerve network system and accelerator for implementing neural network |
| CN110546611A (en) * | 2017-04-17 | 2019-12-06 | 微软技术许可有限责任公司 | Reducing power consumption in a neural network processor by skipping processing operations |
| CN110832507A (en) * | 2017-07-07 | 2020-02-21 | 三菱电机株式会社 | Data processing apparatus, data processing method, and compressed data |
| CN111095302A (en) * | 2017-09-21 | 2020-05-01 | 高通股份有限公司 | Compression of sparse deep convolutional network weights |
| CN111105018A (en) * | 2019-10-21 | 2020-05-05 | 深圳云天励飞技术有限公司 | Data processing method and device |
| CN111582464A (en) * | 2017-12-29 | 2020-08-25 | 中科寒武纪科技股份有限公司 | Neural network processing method, computer system, and storage medium |
| CN111656360A (en) * | 2017-07-21 | 2020-09-11 | 森田公司 | System and method for sparsity utilization |
| CN111767996A (en) * | 2018-02-27 | 2020-10-13 | 上海寒武纪信息科技有限公司 | Integrated circuit chip device and related product |
| CN111858196A (en) * | 2020-06-12 | 2020-10-30 | 海光信息技术有限公司 | Computing unit detection method, parallel processor and electronic equipment |
| CN112119593A (en) * | 2019-07-25 | 2020-12-22 | 深圳市大疆创新科技有限公司 | Data processing method and system, encoder and decoder |
| CN112396157A (en) * | 2019-08-12 | 2021-02-23 | 美光科技公司 | System, method and apparatus for communicating with data storage devices in neural network computing |
| WO2021104179A1 (en) * | 2019-11-25 | 2021-06-03 | 北京灵汐科技有限公司 | Method and apparatus for controlling storage format of on-chip storage resources |
| CN113011577A (en) * | 2019-12-20 | 2021-06-22 | 阿里巴巴集团控股有限公司 | Processing unit, processor core, neural network training machine and method |
| CN113688983A (en) * | 2021-08-09 | 2021-11-23 | 上海新氦类脑智能科技有限公司 | Convolution operation implementation method, circuit and terminal for reducing weight storage in impulse neural network |
| US11221929B1 (en) | 2020-09-29 | 2022-01-11 | Hailo Technologies Ltd. | Data stream fault detection mechanism in an artificial neural network processor |
| US11238334B2 (en) | 2017-04-04 | 2022-02-01 | Hailo Technologies Ltd. | System and method of input alignment for efficient vector operations in an artificial neural network |
| US11237894B1 (en) | 2020-09-29 | 2022-02-01 | Hailo Technologies Ltd. | Layer control unit instruction addressing safety mechanism in an artificial neural network processor |
| US11263077B1 (en) | 2020-09-29 | 2022-03-01 | Hailo Technologies Ltd. | Neural network intermediate results safety mechanism in an artificial neural network processor |
| TWI769807B (en) * | 2021-05-04 | 2022-07-01 | 國立清華大學 | Hardware/software co-compressed computing method and system for sram computing-in-memory-based processing unit |
| US11544545B2 (en) | 2017-04-04 | 2023-01-03 | Hailo Technologies Ltd. | Structured activation based sparsity in an artificial neural network |
| US11551028B2 (en) | 2017-04-04 | 2023-01-10 | Hailo Technologies Ltd. | Structured weight based sparsity in an artificial neural network |
| US11588499B2 (en) | 2018-11-05 | 2023-02-21 | Samsung Electronics Co., Ltd. | Lossless compression of neural network weights |
| US11615297B2 (en) | 2017-04-04 | 2023-03-28 | Hailo Technologies Ltd. | Structured weight based sparsity in an artificial neural network compiler |
| US11811421B2 (en) | 2020-09-29 | 2023-11-07 | Hailo Technologies Ltd. | Weights safety mechanism in an artificial neural network processor |
| US11874900B2 (en) | 2020-09-29 | 2024-01-16 | Hailo Technologies Ltd. | Cluster interlayer safety mechanism in an artificial neural network processor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009176110A (en) * | 2008-01-25 | 2009-08-06 | Seiko Epson Corp | Parallel processing device and parallel processing method |
| CN105184366A (en) * | 2015-09-15 | 2015-12-23 | 中国科学院计算技术研究所 | Time-division-multiplexing general neural network processor |
| CN105260776A (en) * | 2015-09-10 | 2016-01-20 | 华为技术有限公司 | Neural network processor and convolutional neural network processor |
| CN105512723A (en) * | 2016-01-20 | 2016-04-20 | 南京艾溪信息科技有限公司 | Artificial neural network calculating device and method for sparse connection |
-
2016
- 2016-10-27 CN CN201610958305.2A patent/CN106529670B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009176110A (en) * | 2008-01-25 | 2009-08-06 | Seiko Epson Corp | Parallel processing device and parallel processing method |
| CN105260776A (en) * | 2015-09-10 | 2016-01-20 | 华为技术有限公司 | Neural network processor and convolutional neural network processor |
| CN105184366A (en) * | 2015-09-15 | 2015-12-23 | 中国科学院计算技术研究所 | Time-division-multiplexing general neural network processor |
| CN105512723A (en) * | 2016-01-20 | 2016-04-20 | 南京艾溪信息科技有限公司 | Artificial neural network calculating device and method for sparse connection |
Cited By (107)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107016175B (en) * | 2017-03-23 | 2018-08-31 | 中国科学院计算技术研究所 | It is applicable in the Automation Design method, apparatus and optimization method of neural network processor |
| CN107092961A (en) * | 2017-03-23 | 2017-08-25 | 中国科学院计算技术研究所 | A kind of neural network processor and design method based on mode frequency statistical coding |
| CN107103113A (en) * | 2017-03-23 | 2017-08-29 | 中国科学院计算技术研究所 | Towards the Automation Design method, device and the optimization method of neural network processor |
| CN107016175A (en) * | 2017-03-23 | 2017-08-04 | 中国科学院计算技术研究所 | It is applicable the Automation Design method, device and the optimization method of neural network processor |
| CN107103113B (en) * | 2017-03-23 | 2019-01-11 | 中国科学院计算技术研究所 | The Automation Design method, apparatus and optimization method towards neural network processor |
| WO2018171717A1 (en) * | 2017-03-23 | 2018-09-27 | 中国科学院计算技术研究所 | Automated design method and system for neural network processor |
| WO2018171715A1 (en) * | 2017-03-23 | 2018-09-27 | 中国科学院计算技术研究所 | Automated design method and system applicable for neural network processor |
| CN107086910A (en) * | 2017-03-24 | 2017-08-22 | 中国科学院计算技术研究所 | A kind of weight encryption and decryption method and system for Processing with Neural Network |
| CN107103358A (en) * | 2017-03-24 | 2017-08-29 | 中国科学院计算技术研究所 | Processing with Neural Network method and system based on spin transfer torque magnetic memory |
| CN107423816A (en) * | 2017-03-24 | 2017-12-01 | 中国科学院计算技术研究所 | A kind of more computational accuracy Processing with Neural Network method and systems |
| US11521048B2 (en) | 2017-03-24 | 2022-12-06 | Institute Of Computing Technology, Chinese Academy Of Sciences | Weight management method and system for neural network processing, and neural network processor |
| WO2018171663A1 (en) * | 2017-03-24 | 2018-09-27 | 中国科学院计算技术研究所 | Weight management method and system for neural network processing, and neural network processor |
| US11216717B2 (en) | 2017-04-04 | 2022-01-04 | Hailo Technologies Ltd. | Neural network processor incorporating multi-level hierarchical aggregated computing and memory elements |
| US11461614B2 (en) | 2017-04-04 | 2022-10-04 | Hailo Technologies Ltd. | Data driven quantization optimization of weights and input data in an artificial neural network |
| US11263512B2 (en) | 2017-04-04 | 2022-03-01 | Hailo Technologies Ltd. | Neural network processor incorporating separate control and data fabric |
| US11551028B2 (en) | 2017-04-04 | 2023-01-10 | Hailo Technologies Ltd. | Structured weight based sparsity in an artificial neural network |
| US10387298B2 (en) | 2017-04-04 | 2019-08-20 | Hailo Technologies Ltd | Artificial neural network incorporating emphasis and focus techniques |
| US11354563B2 (en) | 2017-04-04 | 2022-06-07 | Hallo Technologies Ltd. | Configurable and programmable sliding window based memory access in a neural network processor |
| US11461615B2 (en) | 2017-04-04 | 2022-10-04 | Hailo Technologies Ltd. | System and method of memory access of multi-dimensional data |
| US11544545B2 (en) | 2017-04-04 | 2023-01-03 | Hailo Technologies Ltd. | Structured activation based sparsity in an artificial neural network |
| US11514291B2 (en) | 2017-04-04 | 2022-11-29 | Hailo Technologies Ltd. | Neural network processing element incorporating compute and local memory elements |
| US11615297B2 (en) | 2017-04-04 | 2023-03-28 | Hailo Technologies Ltd. | Structured weight based sparsity in an artificial neural network compiler |
| US11238334B2 (en) | 2017-04-04 | 2022-02-01 | Hailo Technologies Ltd. | System and method of input alignment for efficient vector operations in an artificial neural network |
| US11238331B2 (en) | 2017-04-04 | 2022-02-01 | Hailo Technologies Ltd. | System and method for augmenting an existing artificial neural network |
| US11675693B2 (en) | 2017-04-04 | 2023-06-13 | Hailo Technologies Ltd. | Neural network processor incorporating inter-device connectivity |
| CN110546611A (en) * | 2017-04-17 | 2019-12-06 | 微软技术许可有限责任公司 | Reducing power consumption in a neural network processor by skipping processing operations |
| CN110546611B (en) * | 2017-04-17 | 2023-05-02 | 微软技术许可有限责任公司 | Reducing power consumption in a neural network processor by skipping processing operations |
| CN107679621A (en) * | 2017-04-19 | 2018-02-09 | 北京深鉴科技有限公司 | Artificial neural network processing unit |
| US10902315B2 (en) | 2017-04-19 | 2021-01-26 | Xilinx, Inc. | Device for implementing artificial neural network with separate computation units |
| CN107679621B (en) * | 2017-04-19 | 2020-12-08 | 赛灵思公司 | Artificial neural network processing device |
| CN108734288A (en) * | 2017-04-21 | 2018-11-02 | 上海寒武纪信息科技有限公司 | A kind of operation method and device |
| CN109376852A (en) * | 2017-04-21 | 2019-02-22 | 上海寒武纪信息科技有限公司 | Arithmetic unit and operation method |
| CN109146069B (en) * | 2017-06-16 | 2020-10-13 | 上海寒武纪信息科技有限公司 | Arithmetic device, arithmetic method, and chip |
| CN109146069A (en) * | 2017-06-16 | 2019-01-04 | 上海寒武纪信息科技有限公司 | Arithmetic unit, operation method and chip |
| CN110832507A (en) * | 2017-07-07 | 2020-02-21 | 三菱电机株式会社 | Data processing apparatus, data processing method, and compressed data |
| CN111656360A (en) * | 2017-07-21 | 2020-09-11 | 森田公司 | System and method for sparsity utilization |
| CN111656360B (en) * | 2017-07-21 | 2024-02-20 | 森田公司 | System and method for sparsity utilization |
| CN107622305A (en) * | 2017-08-24 | 2018-01-23 | 中国科学院计算技术研究所 | Processor and processing method for neutral net |
| CN107578098A (en) * | 2017-09-01 | 2018-01-12 | 中国科学院计算技术研究所 | Neural network processor based on systolic arrays |
| CN107491811A (en) * | 2017-09-01 | 2017-12-19 | 中国科学院计算技术研究所 | Method and system and neural network processor for accelerans network processing unit |
| CN111095302A (en) * | 2017-09-21 | 2020-05-01 | 高通股份有限公司 | Compression of sparse deep convolutional network weights |
| CN111095302B (en) * | 2017-09-21 | 2024-05-28 | 高通股份有限公司 | Compression of Sparse Deep Convolutional Network Weights |
| CN109557996A (en) * | 2017-09-22 | 2019-04-02 | 株式会社东芝 | Arithmetic unit |
| CN108205704B (en) * | 2017-09-27 | 2021-10-29 | 深圳市商汤科技有限公司 | Neural network chip |
| CN108205704A (en) * | 2017-09-27 | 2018-06-26 | 深圳市商汤科技有限公司 | A kind of neural network chip |
| CN107800700A (en) * | 2017-10-27 | 2018-03-13 | 中国科学院计算技术研究所 | A kind of router and network-on-chip Transmission system and method |
| CN107800700B (en) * | 2017-10-27 | 2020-10-27 | 中国科学院计算技术研究所 | Router and network-on-chip transmission system and method |
| CN109726805B (en) * | 2017-10-30 | 2021-02-09 | 上海寒武纪信息科技有限公司 | Method for designing neural network processor by using black box simulator |
| CN109726805A (en) * | 2017-10-30 | 2019-05-07 | 上海寒武纪信息科技有限公司 | The method for carrying out neural network processor design using black box simulator |
| CN107729995A (en) * | 2017-10-31 | 2018-02-23 | 中国科学院计算技术研究所 | Method and system and neural network processor for accelerans network processing unit |
| CN107844829A (en) * | 2017-10-31 | 2018-03-27 | 中国科学院计算技术研究所 | Method and system and neural network processor for accelerans network processing unit |
| JP2021503644A (en) * | 2017-11-10 | 2021-02-12 | 中国科学院▲計▼算技▲術▼研究所Ｉｎｓｔｉｔｕｔｅ Ｏｆ Ｃｏｍｐｕｔｉｎｇ Ｔｅｃｈｎｏｌｏｇｙ，Ｃｈｉｎｅｓｅ Ａｃａｄｅｍｙ Ｏｆ Ｓｃｉｅｎｃｅｓ | Weight data storage method and neural network processor based on this method |
| CN107977704A (en) * | 2017-11-10 | 2018-05-01 | 中国科学院计算技术研究所 | Weighted data storage method and the neural network processor based on this method |
| US11531889B2 (en) | 2017-11-10 | 2022-12-20 | Institute Of Computing Technology, Chinese Academy Of Sciences | Weight data storage method and neural network processor based on the method |
| CN107977704B (en) * | 2017-11-10 | 2020-07-31 | 中国科学院计算技术研究所 | Weight data storage method and neural network processor based on same |
| JP7052034B2 (en) | 2017-11-10 | 2022-04-11 | 中国科学院▲計▼算技▲術▼研究所 | How to store weight data and a neural network processor based on this method |
| CN107918794A (en) * | 2017-11-15 | 2018-04-17 | 中国科学院计算技术研究所 | Neural network processor based on computing array |
| CN107944555A (en) * | 2017-12-07 | 2018-04-20 | 广州华多网络科技有限公司 | Method, storage device and the terminal that neutral net is compressed and accelerated |
| CN107944555B (en) * | 2017-12-07 | 2021-09-17 | 广州方硅信息技术有限公司 | Neural network compression and acceleration method, storage device and terminal |
| CN111582464A (en) * | 2017-12-29 | 2020-08-25 | 中科寒武纪科技股份有限公司 | Neural network processing method, computer system, and storage medium |
| CN111582464B (en) * | 2017-12-29 | 2023-09-29 | 中科寒武纪科技股份有限公司 | Neural network processing method, computer system and storage medium |
| CN109791628A (en) * | 2017-12-29 | 2019-05-21 | 清华大学 | Neural network model splits' positions method, training method, computing device and system |
| CN109791628B (en) * | 2017-12-29 | 2022-12-27 | 清华大学 | Neural network model block compression method, training method, computing device and system |
| CN110045960A (en) * | 2018-01-16 | 2019-07-23 | 腾讯科技（深圳）有限公司 | Instruction set processing method, device and storage medium based on chip |
| CN110046702B (en) * | 2018-01-17 | 2023-05-26 | 联发科技股份有限公司 | Neural network computing accelerator and executing method thereof |
| CN110046702A (en) * | 2018-01-17 | 2019-07-23 | 联发科技股份有限公司 | Neural computing accelerator and its method of execution |
| CN108334945B (en) * | 2018-01-30 | 2020-12-25 | 中国科学院自动化研究所 | Acceleration and compression method and device of deep neural network |
| CN108334945A (en) * | 2018-01-30 | 2018-07-27 | 中国科学院自动化研究所 | The acceleration of deep neural network and compression method and device |
| CN108416425B (en) * | 2018-02-02 | 2020-09-29 | 浙江大华技术股份有限公司 | Convolution operation method and device |
| CN108416425A (en) * | 2018-02-02 | 2018-08-17 | 浙江大华技术股份有限公司 | A kind of convolution method and device |
| CN111767996B (en) * | 2018-02-27 | 2024-03-05 | 上海寒武纪信息科技有限公司 | Integrated circuit chip device and related products |
| CN111767996A (en) * | 2018-02-27 | 2020-10-13 | 上海寒武纪信息科技有限公司 | Integrated circuit chip device and related product |
| CN108510058A (en) * | 2018-02-28 | 2018-09-07 | 中国科学院计算技术研究所 | Weight storage method in neural network and the processor based on this method |
| CN108510058B (en) * | 2018-02-28 | 2021-07-20 | 中国科学院计算技术研究所 | Weight storage method in neural network and processor based on method |
| CN108171328B (en) * | 2018-03-02 | 2020-12-29 | 中国科学院计算技术研究所 | Neural network processor and convolution operation method executed by same |
| CN108171328A (en) * | 2018-03-02 | 2018-06-15 | 中国科学院计算技术研究所 | A kind of convolution algorithm method and the neural network processor based on this method |
| CN108647774A (en) * | 2018-04-23 | 2018-10-12 | 福州瑞芯微电子股份有限公司 | A kind of neural network method and circuit of optimization sparsity matrix operation |
| CN108647774B (en) * | 2018-04-23 | 2020-11-20 | 瑞芯微电子股份有限公司 | Neural network method and circuit for optimizing sparsity matrix operation |
| CN108764454A (en) * | 2018-04-28 | 2018-11-06 | 中国科学院计算技术研究所 | The Processing with Neural Network method compressed and/or decompressed based on wavelet transformation |
| US11687759B2 (en) | 2018-05-01 | 2023-06-27 | Semiconductor Components Industries, Llc | Neural network accelerator |
| CN110428047A (en) * | 2018-05-01 | 2019-11-08 | 半导体组件工业公司 | Nerve network system and accelerator for implementing neural network |
| CN109325590B (en) * | 2018-09-14 | 2020-11-03 | 中国科学院计算技术研究所 | Device for realizing neural network processor with variable calculation precision |
| CN109325590A (en) * | 2018-09-14 | 2019-02-12 | 中国科学院计算技术研究所 | For realizing the device for the neural network processor that computational accuracy can be changed |
| CN109543140A (en) * | 2018-09-20 | 2019-03-29 | 中国科学院计算技术研究所 | A kind of convolutional neural networks accelerator |
| CN109543140B (en) * | 2018-09-20 | 2020-07-10 | 中国科学院计算技术研究所 | Convolutional neural network accelerator |
| CN109492761A (en) * | 2018-10-30 | 2019-03-19 | 深圳灵图慧视科技有限公司 | Realize FPGA accelerator, the method and system of neural network |
| US11588499B2 (en) | 2018-11-05 | 2023-02-21 | Samsung Electronics Co., Ltd. | Lossless compression of neural network weights |
| CN109886416A (en) * | 2019-02-01 | 2019-06-14 | 京微齐力(北京)科技有限公司 | The System on Chip/SoC and machine learning method of integrated AI's module |
| CN110334716A (en) * | 2019-07-04 | 2019-10-15 | 北京迈格威科技有限公司 | Characteristic pattern processing method, image processing method and device |
| CN110334716B (en) * | 2019-07-04 | 2022-01-11 | 北京迈格威科技有限公司 | Feature map processing method, image processing method and device |
| WO2021012278A1 (en) * | 2019-07-25 | 2021-01-28 | 深圳市大疆创新科技有限公司 | Data processing method, system, encoder, and decoder |
| CN112119593A (en) * | 2019-07-25 | 2020-12-22 | 深圳市大疆创新科技有限公司 | Data processing method and system, encoder and decoder |
| CN112396157A (en) * | 2019-08-12 | 2021-02-23 | 美光科技公司 | System, method and apparatus for communicating with data storage devices in neural network computing |
| CN111105018B (en) * | 2019-10-21 | 2023-10-13 | 深圳云天励飞技术有限公司 | Data processing method and device |
| CN111105018A (en) * | 2019-10-21 | 2020-05-05 | 深圳云天励飞技术有限公司 | Data processing method and device |
| US11455108B2 (en) | 2019-11-25 | 2022-09-27 | Lynxi Technologies Co., Ltd. | Method and device for controlling storage format of on-chip storage resource |
| WO2021104179A1 (en) * | 2019-11-25 | 2021-06-03 | 北京灵汐科技有限公司 | Method and apparatus for controlling storage format of on-chip storage resources |
| CN113011577A (en) * | 2019-12-20 | 2021-06-22 | 阿里巴巴集团控股有限公司 | Processing unit, processor core, neural network training machine and method |
| CN113011577B (en) * | 2019-12-20 | 2024-01-05 | 阿里巴巴集团控股有限公司 | Processing unit, processor core, neural network training machine and method |
| CN111858196A (en) * | 2020-06-12 | 2020-10-30 | 海光信息技术有限公司 | Computing unit detection method, parallel processor and electronic equipment |
| US11874900B2 (en) | 2020-09-29 | 2024-01-16 | Hailo Technologies Ltd. | Cluster interlayer safety mechanism in an artificial neural network processor |
| US11811421B2 (en) | 2020-09-29 | 2023-11-07 | Hailo Technologies Ltd. | Weights safety mechanism in an artificial neural network processor |
| US11263077B1 (en) | 2020-09-29 | 2022-03-01 | Hailo Technologies Ltd. | Neural network intermediate results safety mechanism in an artificial neural network processor |
| US11221929B1 (en) | 2020-09-29 | 2022-01-11 | Hailo Technologies Ltd. | Data stream fault detection mechanism in an artificial neural network processor |
| US11237894B1 (en) | 2020-09-29 | 2022-02-01 | Hailo Technologies Ltd. | Layer control unit instruction addressing safety mechanism in an artificial neural network processor |
| TWI769807B (en) * | 2021-05-04 | 2022-07-01 | 國立清華大學 | Hardware/software co-compressed computing method and system for sram computing-in-memory-based processing unit |
| CN113688983A (en) * | 2021-08-09 | 2021-11-23 | 上海新氦类脑智能科技有限公司 | Convolution operation implementation method, circuit and terminal for reducing weight storage in impulse neural network |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106529670B (en) | 2019-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106529670A (en) | Neural network processor based on weight compression, design method, and chip | |
| CN106447034B (en) | A kind of neural network processor based on data compression, design method, chip | |
| CN106650924B (en) | A kind of processor based on time dimension and space dimension data stream compression, design method | |
| CN110516801B (en) | High-throughput-rate dynamic reconfigurable convolutional neural network accelerator | |
| Liang et al. | FP-BNN: Binarized neural network on FPGA | |
| CN107169560B (en) | Self-adaptive reconfigurable deep convolutional neural network computing method and device | |
| CN106529668B (en) | Accelerate the arithmetic unit and method of the acceleration chip of deep neural network algorithm | |
| CN107578098A (en) | Neural network processor based on systolic arrays | |
| CN108280514A (en) | Sparse neural network acceleration system based on FPGA and design method | |
| CN106355244A (en) | CNN (convolutional neural network) construction method and system | |
| CN108665059A (en) | Convolutional neural networks acceleration system based on field programmable gate array | |
| CN108932548A (en) | A kind of degree of rarefication neural network acceleration system based on FPGA | |
| CN109325591A (en) | Neural network processor towards Winograd convolution | |
| CN109447241B (en) | Dynamic reconfigurable convolutional neural network accelerator architecture for field of Internet of things | |
| CN110390383A (en) | A kind of deep neural network hardware accelerator based on power exponent quantization | |
| CN107609641A (en) | Sparse neural network framework and its implementation | |
| CN107423816B (en) | Multi-calculation-precision neural network processing method and system | |
| CN109190756A (en) | Arithmetic unit based on Winograd convolution and the neural network processor comprising the device | |
| CN109472356A (en) | A kind of accelerator and method of restructural neural network algorithm | |
| CN109376843A (en) | EEG signals rapid classification method, implementation method and device based on FPGA | |
| CN107491811A (en) | Method and system and neural network processor for accelerans network processing unit | |
| CN101625735A (en) | FPGA implementation method based on LS-SVM classification and recurrence learning recurrence neural network | |
| CN110163359A (en) | A kind of computing device and method | |
| CN114218875A (en) | Acceleration method and device for flow field prediction | |
| CN107085562A (en) | A kind of neural network processor and design method based on efficient multiplexing data flow |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230109 Address after: 518063 14th Floor, West Tower, Baidu International Building, No. 8, Haitian 1st Road, Binhai Community, Yuehai Street, Nanshan District, Shenzhen, Guangdong Patentee after: Zhongke Times (Shenzhen) Computer System Co.,Ltd. Address before: 100080 No. 6 South Road, Zhongguancun Academy of Sciences, Beijing, Haidian District Patentee before: Institute of Computing Technology, Chinese Academy of Sciences |