CN113688983A - Convolution operation implementation method, circuit and terminal for reducing weight storage in impulse neural network - Google Patents
Convolution operation implementation method, circuit and terminal for reducing weight storage in impulse neural network Download PDFInfo
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Abstract
The invention discloses a convolution operation implementation method, a circuit and a terminal for reducing weight storage in a pulse neural network, wherein the convolution operation implementation method comprises the following steps: acquiring a stored one-dimensional weight vector of a first neuron in the neural nucleus; wherein the neural core comprises: n neurons arranged in sequence; shifting the one-dimensional weight vector of the first neuron to obtain a one-dimensional weight vector of the ith neuron corresponding to the neuron; and performing convolution calculation on the one-dimensional weight vector of the ith neuron and the axon vector corresponding to the neuron to obtain a neuron membrane voltage calculation result corresponding to the ith neuron. According to the invention, one neuron core only stores the weight of one neuron, and the weights of other neurons in the neuron core are obtained by conversion according to the stored weights, so that the weight storage space is greatly reduced.
Description
Technical Field
The invention relates to the field of convolutional calculation of a pulse neural network, in particular to a convolutional operation implementation method, circuit and terminal for reducing weight storage in the pulse neural network.
Background
Deep Neural Network (DNN) research has gained rapid development and initial application in recent years. However, implementing such algorithms typically requires a significant amount of computational effort. AlexNet, which is a classical deep convolutional network (CNN) model, requires at least 7.2 hundred million multiplications. The large amount of computation results in large power consumption, typically around 10 to 100 watts.
On the other hand, the impulse neural network (SNN) has attracted attention in academia and industry in recent years with its low power consumption and closer proximity to the human brain. In a spiking neural network, an axon is a unit that receives a pulse, a neuron is a unit that transmits a pulse, one neuron is connected to a plurality of axons through a dendrite, and the connection point of the dendrite and the axon is called a synapse. After the axon receives the pulse, all dendrites synapse with the axon receive the pulse, and then the neuron downstream of the dendrite is affected. The neuron accumulates pulses from multiple axons and sends a pulse downstream if the value exceeds a threshold. 1-bit pulse is transmitted in the pulse neural network, the activation frequency of the pulse is low, and only addition and subtraction operation is needed without multiplication operation. Compared with a neural network based on deep learning, the impulse neural network has lower power consumption.
Based on the research results of neurobiology, the activation frequency of neuron pulses of human brain is found to be about 10Hz, and the interval between two pulses is several milliseconds. Thus each neuron processes an input pulse every 1 millisecond or so in an implementation. In addition, the time required by the addition and subtraction operation is in the nanosecond level. The method of time division multiplexing can be used, and a plurality of neurons multiplex the same arithmetic unit to process different axons. To time-multiplex the arithmetic units, the connection relationship between axons and neurons, which is synaptic connection, must be known. An axon receives a pulse, all neurons synaptically connected to the axon are affected, and neurons not synaptically connected to the axon are not affected. The synaptic connection relationships are stored in the synaptic connection RAM. In a typical implementation, multiple neurons are integrated into a single neuron core. All neurons in the same core share a computing circuit, and the connection relationship between all input axons of the core and all neurons in the core exists in the same synaptic connection RAM.
When the impulse neural network hardware implements convolution operations in artificial intelligence, synaptic connections are weights. The weights are usually 8 bits wide. If N neurons are integrated in a neuron core, each neuron supports M axon inputs, the storage required by the neuron core for storing the weight is N M8 bits N M Byte, and if N M256, the weight storage space is up to 64K bytes, so that the weight storage pressure is greatly increased.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a convolution implementation method, circuit and terminal for reducing weight storage in a spiking neural network, which are used to solve the problem that in the prior art, when the spiking neural network hardware implements convolution in artificial intelligence, weights of all neurons need to be stored, which greatly increases weight storage pressure.
To achieve the above and other related objects, the present invention provides a convolution operation implementation method for reducing weight storage in an impulse neural network, the method comprising: acquiring a stored one-dimensional weight vector of a first neuron in the neural nucleus; wherein the neural core comprises: n neurons arranged in sequence; and wherein N is an integer greater than or equal to 1; shifting the one-dimensional weight vector of the first neuron to obtain a one-dimensional weight vector of the ith neuron corresponding to the neuron; wherein i is an integer greater than 1 and less than or equal to N; and performing convolution calculation on the one-dimensional weight vector of the ith neuron and the axon vector corresponding to the neuron to obtain a neuron membrane voltage calculation result corresponding to the ith neuron.
In an embodiment of the present invention, the manner of shifting the one-dimensional weight vector of the first neuron to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron includes: and right shifting the one-dimensional weight vector of the first neuron by one or more weight bit widths to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron.
In an embodiment of the present invention, the right shift of the one-dimensional weight vector of the first neuron by one or more weight bit widths to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron includes: when the convolution step size stride is judged to be 1, right shifting the one-dimensional weight vector of the first neuron by i-1 weight bit width to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron; and when the convolution step stride is judged not to be 1, right shifting (i-1) × stride weight bit width to the one-dimensional weight vector of the first neuron to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron.
In an embodiment of the present invention, the axon vector is obtained by mapping each unit on the feature map to all axon inputs corresponding to the neuron according to a preset mapping order.
In an embodiment of the present invention, the right shift of the one-dimensional weight vector of the first neuron by one or more weight bit widths to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron includes: and when the number of the channels input by the axon is judged not to be 1, right shifting the one-dimensional weight vector of the first neuron by one or more weight bit widths based on a preset mapping sequence of the axon vector to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron.
In an embodiment of the present invention, the right shifting the one-dimensional weight vector of the first neuron by one or more weight bit widths based on the predetermined mapping order of the axon vector comprises: if the preset mapping sequence of the axon vector is that the mapping of all units of the feature map in one channel is finished sequentially from left to right and from top to bottom, the mapping of all units of the feature map in the next channel is finished sequentially from left to right and from top to bottom until all channels are mapped, the one-dimensional weight vector of the first neuron is shifted to the right by (i-1) stride bit widths to obtain a one-dimensional weight vector corresponding to the ith neuron in the neuron; if the preset mapping sequence of the axon vector is that all channels are mapped by each unit of the feature map from channel 0 in the ascending order of the channel number, then the mapping is sequentially completed from left to right and from top to bottom until all channels are mapped, and the one-dimensional weight vector of the first neuron is shifted to the right by (i-1) stride in channel _ count weight bit widths to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron; wherein the channel _ count is the number of channels of axon input.
In an embodiment of the present invention, the manner of performing convolution calculation on the one-dimensional weight vector of the ith neuron and the axon vector corresponding to the neuron to obtain the neuron membrane voltage calculation result corresponding to the ith neuron includes: and multiplying the one-dimensional weight vector of the ith neuron by the transpose of the axon vector corresponding to the neuron to obtain a neuron membrane voltage calculation result corresponding to the ith neuron.
To achieve the above and other related objects, the present invention provides a convolution operation implementation circuit for reducing weight storage in a spiking neural network, the circuit comprising: a weight store to store a one-dimensional weight vector for a first neuron of the one or more neurons; the weight acquisition module is connected with the weight storage and used for acquiring the stored one-dimensional weight vector of the first neuron in each neuron; wherein each of the nuclei includes: n neurons arranged in sequence; and wherein N is an integer greater than or equal to 1; the weight shifting module is connected with the weight acquisition module and is used for shifting the one-dimensional weight vector of the first neuron of each neural nucleus respectively to acquire the one-dimensional weight vector of the ith neuron corresponding to each neural nucleus; wherein i is an integer greater than 1 and less than or equal to N; one or more calculation modules connected to the weight shift module, configured to perform convolution calculation on the one-dimensional weight vector of the ith neuron of each neuron and the axon vector of the ith neuron corresponding to each neuron, so as to obtain a neuron membrane voltage calculation result of the ith neuron corresponding to each neuron.
To achieve the above and other related objects, the present invention provides a convolution operation implementation terminal for reducing weight storage in an impulse neural network, including: a memory for storing a computer program; and the processor is used for executing the convolution operation implementation method for reducing weight storage in the impulse neural network.
As described above, the convolution operation implementation method, circuit and terminal for reducing weight storage in the impulse neural network of the present invention have the following beneficial effects: according to the invention, one neuron core only stores the weight of one neuron, and the weights of other neurons in the neuron core are obtained by conversion according to the stored weights, so that the weight storage space is greatly reduced.
Drawings
Fig. 1 is a flowchart illustrating a convolution operation implementation method for reducing weight storage in a spiking neural network according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a one-dimensional weight vector of a neuron according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating two-dimensional convolution and axon-neuron mapping according to an embodiment of the invention.
Fig. 4 is a schematic structural diagram of a convolution operation implementation circuit for reducing weight storage in a spiking neural network according to an embodiment of the invention.
Fig. 5 is a schematic structural diagram of a convolution operation implementation terminal for reducing weight storage in a spiking neural network according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It is noted that in the following description, reference is made to the accompanying drawings which illustrate several embodiments of the present invention. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "below," "lower," "over," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures.
Throughout the specification, when a part is referred to as being "connected" to another part, this includes not only a case of being "directly connected" but also a case of being "indirectly connected" with another element interposed therebetween. In addition, when a certain part is referred to as "including" a certain component, unless otherwise stated, other components are not excluded, but it means that other components may be included.
The terms first, second, third, etc. are used herein to describe various elements, components, regions, layers and/or sections, but are not limited thereto. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the present invention.
Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," and/or "comprising," when used in this specification, specify the presence of stated features, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, operations, elements, components, items, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions or operations are inherently mutually exclusive in some way.
The embodiment of the invention provides a convolution operation implementation method for reducing weight storage in a pulse neural network.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in a variety of different forms and is not limited to the embodiments described herein.
Fig. 1 is a schematic flow chart showing a convolution operation implementation method for reducing weight storage in a spiking neural network according to an embodiment of the present invention.
The method comprises the following steps:
step S11: a stored one-dimensional weight vector for a first neuron in the neuron is obtained.
In detail, the neural nucleus includes: n neurons arranged in sequence. And wherein N is an integer greater than or equal to 1;
optionally, each neuron corresponds to a two-dimensional weight matrix, and the weight matrices corresponding to the neurons are sequentially arranged from left to right and from top to bottom to form a one-dimensional weight vector.
Step S12: and shifting the one-dimensional weight vector of the first neuron to obtain the one-dimensional weight vector of the ith neuron corresponding to the neuron.
In detail, i is an integer greater than 1 and less than or equal to N.
Optionally, the one-dimensional weight vector of the first neuron is right-shifted by one or more weight bit widths to obtain a one-dimensional weight vector corresponding to an ith neuron in the neuron.
Optionally, each neuron corresponds to a two-dimensional weight matrix, and each neuron weight matrix is obtained by moving a convolution kernel based on the first neuron.
Optionally, regarding the number of right shift weight bit widths, the number is related to a convolution step size for performing convolution calculation, so step S12 includes: when the convolution step size stride is judged to be 1, right shifting the one-dimensional weight vector of the first neuron by i-1 weight bit width to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron; and when the convolution step stride is judged not to be 1, right shifting (i-1) × stride weight bit width to the one-dimensional weight vector of the first neuron to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron. For example, as shown in fig. 2, when the convolution step size stride is determined to be 1, the one-dimensional weight vector w1D _ vec (i) of each neuron can be obtained by shifting w1D _ vec (0) by i weight bit widths.
Optionally, the axon vector of the neuron is obtained by mapping each unit on the feature map to all axon inputs corresponding to the neuron according to a preset mapping sequence; in one embodiment, each cell on a width and height profile is mapped onto the axon input sequentially according to a preset mapping order to form the axon vector axon _ vec. For example, the preset mapping order is to sequentially map from left to right and from top to bottom.
Optionally, the number of bits of the right shift weight is also related to the number of input channels of the axon input; if the number of the channels is larger than 1, determining the number of the right shift weight bit width by the preset mapping sequence of the axon vector; step S12 thus includes: and when the number of the channels input by the axon is judged not to be 1, right shifting the one-dimensional weight vector of the first neuron by one or more weight bit widths based on a preset mapping sequence of the axon vector to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron.
Optionally, the right-shifting the one-dimensional weight vector of the first neuron by one or more weight bit widths based on the preset mapping order of the axon vector includes:
if the preset mapping sequence of the axon vector is that the mapping of all units of the feature map in one channel is finished sequentially from left to right and from top to bottom, the mapping of all units of the feature map in the next channel is finished sequentially from left to right and from top to bottom until all channels are mapped, the one-dimensional weight vector of the first neuron is shifted to the right by (i-1) stride bit widths to obtain a one-dimensional weight vector corresponding to the ith neuron in the neuron; for example, if stride is 1, the one-dimensional weight vector of the 4 th neuron needs to be right-shifted by (4-1) × 1 ═ 3 weight bits wide.
If the preset mapping sequence of the axon vector is that all channels are mapped by each unit of the feature map from channel 0 in the ascending order of the channel number, then the mapping is sequentially completed from left to right and from top to bottom until all channels are mapped, and the one-dimensional weight vector of the first neuron is shifted to the right by (i-1) stride in channel _ count weight bit widths to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron; wherein the channel _ count is the number of channels of axon input. For example, if stride is 1 and the number of channels is 2, the one-dimensional weight vector of the 4 th neuron needs to be right-shifted by (4-1) × 1 × 2 ═ 6 weight bits wide.
Step S13: and performing convolution calculation on the one-dimensional weight vector of the ith neuron and the axon vector corresponding to the neuron to obtain a neuron membrane voltage calculation result corresponding to the ith neuron.
Optionally, the one-dimensional weight vector of the ith neuron is multiplied by the transpose of the axon vector corresponding to the neuron, so as to obtain a neuron membrane voltage calculation result corresponding to the ith neuron.
Alternatively, the impulse neural network adopts a structure similar to crossbar, and the calculation result of the membrane voltage of each neuron in the neuron core is the multiplication result of the one-dimensional weight vector w1D _ vec corresponding to the neuron and the transpose of the axon vector axon _ vec formed by all axon inputs.
In order to better describe the implementation method of the convolution operation for reducing weight storage in the impulse neural network, a specific embodiment is provided;
example 1: a convolution operation implementation method for reducing weight storage in a pulse neural network.
The method comprises the following steps:
acquiring a one-dimensional weight vector w1D _ vec (0) of a first neuron in the stored neural core; wherein the neural core comprises: n neurons arranged in sequence; and wherein N is an integer greater than or equal to 1;
the one-dimensional weight vector w1D _ vec (i) of each neuron can be obtained by right shifting w1D _ vec (0) by i weight bit widths;
the impulse neural network adopts a structure similar to a crossbar, and the calculation result neuron1D of the membrane voltage of each neuron in a neuron core is the result of multiplying a one-dimensional weight vector w1D _ vec corresponding to the neuron by the transpose of an axon vector axon _ vec consisting of all axon inputs; specifically, as shown in fig. 3, a feature pattern block with width and height is convolved with a weight matrix with width and height both being R to obtain neuron membrane voltage calculation result neuron 1D; and mapping each unit on the feature map to the axon input sequentially from left to right and from top to bottom to form axon _ vec. The upper rectangle in fig. 3 represents the feature tile and the convolution kernel (weight matrix) of size R x R is shown to the right. And (3) performing multiplication and addition operation on each unit on the feature map and the convolution kernel unit which is shifted to the right to obtain a unit neuron (m, n) on the two-dimensional activated block. m represents the row and n represents the column. The two-dimensional neuron matrix is sequentially mapped to the one-dimensional neuron1D vector from left to right and from top to bottom.
Similar to the principle of the above embodiments, the present invention provides a convolution operation implementation circuit for reducing weight storage in a spiking neural network.
Specific embodiments are provided below in conjunction with the attached figures:
fig. 4 is a schematic structural diagram of a convolution operation implementation circuit for reducing weight storage in a spiking neural network according to an embodiment of the present invention.
The circuit comprises:
a weight store 41 for storing a one-dimensional weight vector for a first neuron of the one or more neurons;
the weight obtaining module 42 is connected to the weight storage 41, and is configured to obtain a stored one-dimensional weight vector of a first neuron in each neuron; wherein each of the nuclei includes: n neurons arranged in sequence; and wherein N is an integer greater than or equal to 1;
the weight shifting module 43 is connected to the weight obtaining module 42, and is configured to shift the one-dimensional weight vector of the first neuron of each neural core, respectively, to obtain a one-dimensional weight vector of the ith neuron corresponding to each neural core; wherein i is an integer greater than 1 and less than or equal to N;
one or more calculation modules 44, connected to the weight shift module 43, for performing convolution calculation on the one-dimensional weight vector of the ith neuron of each neuron core and the axon vector of the ith neuron corresponding to each neuron core to obtain a neuron membrane voltage calculation result of the ith neuron corresponding to each neuron core.
Optionally, the weight storage 41 stores only one-dimensional weight vectors of the first neuron of each neuron. For example, if N neurons are integrated into a neuron core, each neuron supporting M axon inputs, the weight storage space only needs 1/N of the storage space of the conventional method. If N-M-256, the weight storage of the neuron nucleus is reduced from 64K to 256 Byte.
Alternatively, the weight shift module 43 may output a plurality of weights simultaneously to support a plurality of parallel calculation modules.
Optionally, the weight shifting module 43 is configured to shift the one-dimensional weight vector of the first neuron of each neural core by one or more weight bit widths to the right, so as to obtain a one-dimensional weight vector corresponding to the ith neuron in each neural core.
Optionally, the weight shift module 43 is configured to, when it is determined that the convolution step stride is 1, right shift the one-dimensional weight vector of the first neuron of each neural core by i-1 weight bit width to obtain a one-dimensional weight vector of the ith neuron corresponding to each neural core; and when the convolution step stride is judged not to be 1, right shifting (i-1) × stride weight bit width to the one-dimensional weight vector of the first neuron of each neural nucleus to obtain the one-dimensional weight vector of the ith neuron corresponding to each neural nucleus.
Optionally, the axon vector is obtained by mapping each unit on the feature map to all axon inputs corresponding to the neuron according to a preset mapping order. The weight shifting module 43 is configured to, when it is determined that the number of channels input by the axon is not 1, right shift the one-dimensional weight vector of the first neuron by one or more weight bit widths based on a preset mapping order of the axon vector, and obtain a one-dimensional weight vector corresponding to an ith neuron in the neuron.
Preferably, if the preset mapping sequence of the axon vector is that the units of the feature map in one channel are sequentially mapped from left to right and from top to bottom, and the units of the feature map in the next channel are sequentially mapped from left to right and from top to bottom, until all channels are mapped, the weight shifting module 43 is configured to shift the one-dimensional weight vector of the first neuron by (i-1) stride weight bit widths to the right, so as to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron; if the preset mapping sequence of the axon vector is that all channels are mapped by each unit of the feature map from channel 0 in the ascending order of the channel number, and then the mapping is sequentially completed from left to right and from top to bottom until all channels are mapped, the weight shifting module 43 is configured to shift the one-dimensional weight vector of the first neuron to the right by (i-1) stride in channel count _ count weight bit widths to obtain a one-dimensional weight vector corresponding to the ith neuron in the neuron; wherein the channel _ count is the number of channels of axon input.
Optionally, a computation module 44 may be respectively disposed corresponding to each neuron, or a plurality of neurons may perform convolution computation by using a computation module.
Optionally, the calculating module 44 is configured to multiply the one-dimensional weight vector of the ith neuron by the transpose of the axon vector corresponding to the neuron, so as to obtain a neuron membrane voltage calculation result corresponding to the ith neuron.
Optionally, the circuit further includes: a neuron counting module 45 connected to the weight shifting module 43 for counting neurons of each shifted neuron core; for example, the neuron count module 45 may be an accumulated count of stride _ in channel _ count.
Fig. 5 is a schematic structural diagram of a convolution operation implementation terminal 50 for reducing weight storage in an impulse neural network according to an embodiment of the present invention.
The convolution operation implementation terminal 50 for reducing weight storage in the impulse neural network includes: a memory 51 and a processor 52, the memory 51 for storing computer programs; the processor 52 runs a computer program to implement the convolution operation implementation method for reducing weight storage in the spiking neural network as described in fig. 1.
Optionally, the number of the memories 51 may be one or more, the number of the processors 52 may be one or more, and fig. 5 is an example.
Optionally, the processor 52 in the terminal 50 for implementing convolution operation for reducing weight storage in the spiking neural network loads one or more instructions corresponding to the process of the application program into the memory 51 according to the steps shown in fig. 1, and the processor 52 runs the application program stored in the first memory 51, so as to implement various functions in the method for implementing convolution operation for reducing weight storage in the spiking neural network shown in fig. 1.
Optionally, the memory 51 may include, but is not limited to, a high speed random access memory, a non-volatile memory. Such as one or more magnetic disk storage devices, flash memory devices, or other non-volatile solid-state storage devices; the Processor 52 may include, but is not limited to, a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.
Optionally, the Processor 52 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.
The present invention also provides a computer-readable storage medium storing a computer program, which when executed implements the convolution operation implementation method for reducing weight storage in the impulse neural network shown in fig. 1. The computer-readable storage medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (compact disc-read only memories), magneto-optical disks, ROMs (read-only memories), RAMs (random access memories), EPROMs (erasable programmable read only memories), EEPROMs (electrically erasable programmable read only memories), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing machine-executable instructions. The computer readable storage medium may be a product that is not accessed by the computer device or may be a component that is used by an accessed computer device.
In summary, in the convolutional operation implementation method, circuit and terminal for reducing weight storage in the pulse neural network, the weight of only one neuron is stored by one neuron core, and the weights of other neurons in the neuron core are obtained by transforming according to the stored weights, so that the weight storage space is greatly reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles of the present invention and its efficacy, and are not to be construed as limiting the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A convolution operation implementation method for reducing weight storage in a pulse neural network is characterized by comprising the following steps:
acquiring a stored one-dimensional weight vector of a first neuron in the neural nucleus; wherein the neural core comprises: n neurons arranged in sequence; and wherein N is an integer greater than or equal to 1;
shifting the one-dimensional weight vector of the first neuron to obtain a one-dimensional weight vector of the ith neuron corresponding to the neuron; wherein i is an integer greater than 1 and less than or equal to N;
and performing convolution calculation on the one-dimensional weight vector of the ith neuron and the axon vector corresponding to the neuron to obtain a neuron membrane voltage calculation result corresponding to the ith neuron.
2. The method of claim 1, wherein the shifting the one-dimensional weight vector of the first neuron to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron comprises:
and right shifting the one-dimensional weight vector of the first neuron by one or more weight bit widths to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron.
3. The method of claim 2, wherein the right shifting the one-dimensional weight vector of the first neuron by one or more weight bit widths to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron comprises:
when the convolution step size stride is judged to be 1, right shifting the one-dimensional weight vector of the first neuron by i-1 weight bit width to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron;
and when the convolution step stride is judged not to be 1, right shifting (i-1) × stride weight bit width to the one-dimensional weight vector of the first neuron to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron.
4. The method of claim 2, wherein the axon vector is obtained by mapping each cell on the feature map to all axon inputs corresponding to the neuron according to a predetermined mapping order.
5. The method of claim 4, wherein the right shifting the one-dimensional weight vector of the first neuron by one or more weight bit widths to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron comprises:
and when the number of the channels input by the axon is judged not to be 1, right shifting the one-dimensional weight vector of the first neuron by one or more weight bit widths based on a preset mapping sequence of the axon vector to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron.
6. The method of claim 5, wherein right shifting the one-dimensional weight vector of the first neuron by one or more weight bit widths based on the predetermined mapping order of the axon vector comprises:
if the preset mapping sequence of the axon vector is that the mapping of all units of the feature map in one channel is finished sequentially from left to right and from top to bottom, the mapping of all units of the feature map in the next channel is finished sequentially from left to right and from top to bottom until all channels are mapped, the one-dimensional weight vector of the first neuron is shifted to the right by (i-1) stride bit widths to obtain a one-dimensional weight vector corresponding to the ith neuron in the neuron;
if the preset mapping sequence of the axon vector is that all channels are mapped by each unit of the feature map from channel 0 in the ascending order of the channel number, then the mapping is sequentially completed from left to right and from top to bottom until all channels are mapped, and the one-dimensional weight vector of the first neuron is shifted to the right by (i-1) stride in channel _ count weight bit widths to obtain the one-dimensional weight vector corresponding to the ith neuron in the neuron; wherein the channel _ count is the number of channels of axon input.
7. The method for implementing convolution operation with reduced weight storage in a spiking neural network according to claim 1, wherein the convolution calculation of the one-dimensional weight vector of the ith neuron and the axon vector corresponding to the neuron to obtain the neuron membrane voltage calculation result corresponding to the ith neuron comprises:
and multiplying the one-dimensional weight vector of the ith neuron by the transpose of the axon vector corresponding to the neuron to obtain a neuron membrane voltage calculation result corresponding to the ith neuron.
8. A convolution operation implementation circuit for reducing weight storage in a spiking neural network, the circuit comprising:
a weight store to store a one-dimensional weight vector for a first neuron of the one or more neurons;
the weight acquisition module is connected with the weight storage and used for acquiring the stored one-dimensional weight vector of the first neuron in each neuron; wherein each of the nuclei includes: n neurons arranged in sequence; and wherein N is an integer greater than or equal to 1;
the weight shifting module is connected with the weight acquisition module and is used for shifting the one-dimensional weight vector of the first neuron of each neural nucleus respectively to acquire the one-dimensional weight vector of the ith neuron corresponding to each neural nucleus; wherein i is an integer greater than 1 and less than or equal to N;
one or more calculation modules connected to the weight shift module, configured to perform convolution calculation on the one-dimensional weight vector of the ith neuron of each neuron and the axon vector of the ith neuron corresponding to each neuron, so as to obtain a neuron membrane voltage calculation result of the ith neuron corresponding to each neuron.
9. The circuit for implementing convolution operations with reduced weight storage in a spiking neural network according to claim 8, further comprising:
and the neuron counting module is connected with the weight shifting module and is used for counting the neurons of each shifted neural nucleus.
10. A convolution operation implementation terminal for reducing weight storage in a pulse neural network is characterized by comprising the following components:
a memory for storing a computer program;
a processor for performing a convolution operation implementation method of reducing weight storage in a spiking neural network as claimed in any of claims 1 to 7.
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