CN107086772B

CN107086772B - Boost circuit

Info

Publication number: CN107086772B
Application number: CN201710264109.XA
Authority: CN
Inventors: 易克
Original assignee: Chipsea Technologies Shenzhen Co Ltd
Current assignee: Chipsea Technologies Shenzhen Co Ltd
Priority date: 2017-04-20
Filing date: 2017-04-20
Publication date: 2023-04-25
Anticipated expiration: 2037-04-20
Also published as: CN107086772A

Abstract

The invention discloses a booster circuit, which comprises a power input end, a power output end, a first NMOS tube, a second NMOS tube, a first drive circuit unit, a second drive circuit unit, an inductor, an output capacitor array and a main control circuit unit, wherein the power input end is connected with the power output end; the power input end is connected with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube through an inductor, the drain electrode of the first NMOS tube is connected with one end of the output capacitor array and the power output end, the other end of the output capacitor array is grounded, and the grid electrode of the first NMOS tube is connected with the output end of the first drive circuit unit; the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the output end of the second drive circuit unit; the input ends of the first driving circuit unit and the second driving circuit unit are connected with the main control circuit unit, and the main control circuit unit is also connected with the power supply output end. The invention can meet the boosting requirement and improve the carrying capacity and simultaneously reduce the cost.

Description

Boost circuit

Technical Field

The invention relates to the technical field of electronics, in particular to a booster circuit.

Background

At present, lithium batteries are widely used in various consumer electronic products, such as desk lamps, mobile power supplies, atomizers, shavers, small fans, toys and the like, but as the discharge voltage range of the lithium batteries is usually 2.8V to 4.3V, the above consumer electronic products usually need to use 5V or higher, and therefore, the consumer electronic products powered by the lithium batteries are all provided with corresponding DC-DC boost circuits.

In the prior art, a Boost chip is adopted by a DC-DC Boost circuit in most consumer electronic products to realize the Boost function of the lithium battery voltage, however, the voltage value output by the DC-DC Boost circuit which adopts the Boost chip to realize the Boost is fixed, and the load current is usually within 1A, so that the maximum power value of the consumer electronic products is limited; in addition, when the DC-DC booster circuit is applied to the application scene of high voltage or heavy load, an additional MOSFET driving chip is needed to realize the purpose of adjusting the boost value, and the additional MOSFET driving chip has the defect of higher circuit cost due to the higher price of the MOSFET driving chip.

Disclosure of Invention

The invention mainly aims to provide a booster circuit, which aims to meet the boosting requirement, improve the carrying capacity and reduce the cost of the circuit.

In order to achieve the above object, the present invention provides a boost circuit, which includes a power input terminal, a power output terminal, a first NMOS transistor, a second NMOS transistor, a first driving circuit unit for driving the first NMOS transistor to switch, a second driving circuit unit for driving the second NMOS transistor to switch, an inductor for storing or releasing electric energy according to the switching actions of the first NMOS transistor and the second NMOS transistor, an output capacitor array for storing electric energy of the power input terminal and electric energy released by the inductor, supplying power to the power output terminal and filtering voltage of the power output terminal, and a main control circuit unit for controlling the first driving circuit unit and the second driving circuit unit to operate according to the voltage of the power output terminal and a preset target boost value; wherein:

the power input end is connected with the first end of the inductor, the second end of the inductor is respectively connected with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube, the drain electrode of the first NMOS tube is respectively connected with one end of the output capacitor array and the power output end, the other end of the output capacitor array is grounded, and the grid electrode of the first NMOS tube is connected with the output end of the first drive circuit unit; the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the output end of the second drive circuit unit; the input end of the first driving circuit unit and the input end of the second driving circuit unit are connected with the control output end of the main control circuit unit; and the sampling input end of the main control circuit unit is connected with the power supply output end.

Preferably, the first driving circuit unit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first NPN triode, a first PNP triode, a third NMOS tube, a first capacitor, and a first diode; wherein:

the grid electrode of the third NMOS tube is an input end of the first driving circuit unit, the grid electrode of the third NMOS tube is respectively connected with the control output end of the main control circuit unit and the first end of the first resistor, the drain electrode of the third NMOS tube is respectively connected with the base electrode of the first NPN triode and the base electrode of the first PNP triode, and the source electrode of the third NMOS tube and the second end of the first resistor are grounded; the collector of the first NPN triode is connected with the first end of the second resistor, the second end of the second resistor is connected with the base electrode of the first NPN triode, and the emitter of the first NPN triode is respectively connected with the emitter of the first PNP triode and the first end of the third resistor; the collector electrode of the first PNP triode is grounded; the second end of the third resistor is an output end of the first driving circuit unit and is connected with the grid electrode of the first NMOS tube; the first end of the fourth resistor is connected with the grid electrode of the first NMOS tube, and the second end of the fourth resistor is connected with the drain electrode of the second NMOS tube; the first end of the second resistor is also connected with the cathode of the first diode and the first end of the first capacitor respectively; the anode of the first diode is connected with the power supply output end; the second end of the first capacitor is connected with the second end of the inductor.

Preferably, the second driving circuit unit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a second NPN triode and a second PNP triode; wherein:

the first end of the fifth resistor is an input end of the second driving circuit unit, the first end of the fifth resistor is connected with the control output end of the main control circuit unit, the second end of the fifth resistor is respectively connected with the base electrode of the second NPN triode, the base electrode of the second PNP triode and the first end of the sixth resistor, and the second end of the sixth resistor is grounded; the collector of the second NPN triode is connected with the power supply output end, and the emitter of the second NPN triode is respectively connected with the emitter of the second PNP triode and the first end of the seventh resistor; the collector electrode of the second PNP triode is grounded; the second end of the seventh resistor is the output end of the second driving circuit unit, the second end of the seventh resistor is connected with the grid electrode of the second NMOS tube, the first end of the eighth resistor is connected with the grid electrode of the second NMOS tube, and the second end of the eighth resistor is grounded.

Preferably, the output capacitor array comprises at least 2 capacitors, one end of the at least 2 capacitors connected in parallel is connected with the power supply output end, and the other end of the at least 2 capacitors connected in parallel is grounded.

Preferably, the main control circuit unit includes a voltage sampling circuit subunit for sampling the voltage of the power output end, and a controller for controlling the first driving circuit unit and the second driving circuit unit to work according to the voltage sampled by the voltage sampling circuit subunit and the preset target boost value; wherein:

the sampling input end of the voltage sampling circuit subunit is connected with the power supply output end, and the sampling output end of the voltage sampling circuit subunit is connected with the sampling input end of the controller; the control output end of the controller comprises a first control output end and a second control output end, the first control output end of the controller is connected with the input end of the first driving circuit unit, and the second control output end of the controller is connected with the input end of the second driving circuit unit.

Preferably, the voltage sampling circuit subunit includes a ninth resistor and a tenth resistor; wherein:

the first end of the ninth resistor is a sampling input end of the voltage sampling circuit subunit, the first end of the ninth resistor is connected with the power output end, the second end of the ninth resistor is a sampling output end of the voltage sampling circuit subunit, the second end of the ninth resistor is connected with the sampling input end of the controller and the first end of the tenth resistor respectively, and the second end of the tenth resistor is grounded.

Preferably, the boost circuit further comprises a filter circuit unit for filtering the voltage of the power input end, one end of the filter circuit unit is connected with the power input end, and the other end of the filter circuit unit is grounded.

Preferably, the filter circuit unit includes a second capacitor, a third capacitor and a fourth capacitor; wherein:

one end of the second capacitor, the third capacitor and the fourth capacitor which are connected in parallel with each other is connected with the power input end, and the other end of the second capacitor, the third capacitor and the fourth capacitor which are connected in parallel with each other is grounded.

The invention provides a boost circuit, which comprises a power input end, a power output end, a first NMOS tube, a second NMOS tube, a first driving circuit unit for driving the first NMOS tube to switch, a second driving circuit unit for driving the second NMOS tube to switch, an inductor for storing or releasing electric energy according to the switching actions of the first NMOS tube and the second NMOS tube, an output capacitor array for storing the electric energy of the power input end and the electric energy released by the inductor, supplying power to the power output end and filtering the voltage of the power output end, and a main control circuit unit for controlling the first driving circuit unit and the second driving circuit unit to work according to the voltage of the power output end and a preset target boost value; the power input end is connected with the first end of the inductor, the second end of the inductor is respectively connected with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube, the drain electrode of the first NMOS tube is respectively connected with one end of the output capacitor array and the power output end, the other end of the output capacitor array is grounded, and the grid electrode of the first NMOS tube is connected with the output end of the first drive circuit unit; the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the output end of the second drive circuit unit; the input end of the first driving circuit unit and the input end of the second driving circuit unit are connected with the control output end of the main control circuit unit; and the sampling input end of the main control circuit unit is connected with the power supply output end. The booster circuit meets the boosting requirement, improves the carrying capacity and reduces the cost of the circuit; meanwhile, the invention has the advantages of simple structure and easy realization.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a boosting circuit according to an embodiment of the present invention;

fig. 2 is a schematic waveform diagram of a first control signal PWM1 and a second control signal PWM2 output by the controller in an embodiment of the boost circuit of the present invention.

The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a boost circuit according to the present invention, where the boost circuit includes a power input terminal VIN, a power output terminal VOUT, a first NMOS transistor 101, a second NMOS transistor 102, a first driving circuit unit 103 for driving a switching operation of the first NMOS transistor 101, a second driving circuit unit 104 for driving a switching operation of the second NMOS transistor 102, an inductor L1 for storing or releasing electric energy according to the switching operations of the first NMOS transistor 101 and the second NMOS transistor 102, an output capacitor array 105 for storing electric energy of the power input terminal VIN and electric energy released by the inductor L1, supplying power to the power output terminal VOUT, and filtering a voltage of the power output terminal VOUT, and a main control unit 106 for controlling the operation of the first driving circuit unit 103 and the second driving circuit unit 104 according to the voltage of the power output terminal VOUT and a preset target boost value. In this embodiment, the voltage of the power input terminal VIN is provided by a lithium battery.

Specifically, in this embodiment, the power input terminal VIN is connected to a first end of the inductor L1, a second end of the inductor L1 is connected to a source of the first NMOS 101 and a drain of the second NMOS 102, the drain of the first NMOS 101 is connected to one end of the output capacitor array 105 and the power output terminal VOUT, the other end of the output capacitor array 105 is grounded, and a gate of the first NMOS 101 is connected to an output terminal of the first driving circuit unit 103; the source electrode of the second NMOS tube 102 is grounded, and the gate electrode of the second NMOS tube 102 is connected with the output end of the second driving circuit unit 104; the input end of the first driving circuit unit 103 and the input end of the second driving circuit unit 104 are connected with the control output end of the main control circuit unit 106; the sampling input terminal of the main control circuit unit 106 is connected to the power output terminal VOUT.

In this embodiment, the first NMOS transistor 101 and the second NMOS transistor 102 are all NMOS transistors packaged with 8 pins. The 1 st, 2 nd and 3 rd pins of the first NMOS 101 are all sources of the first NMOS 101, the 4 th pin of the first NMOS 101 is a gate of the first NMOS 101, the 5 th, 6 th, 7 th and 8 th pins of the first NMOS 101 are drains of the first NMOS 101, a cathode of a diode D2 inside the first NMOS 101 is connected with the drain of the first NMOS 101, and an anode of the diode D2 is connected with the source of the first NMOS 101. The 1 st, 2 nd and 3 rd pins of the second NMOS 102 are all sources of the second NMOS 102, the 4 th pin of the second NMOS 102 is a gate of the second NMOS 102, the 5 th, 6 th, 7 th and 8 th pins of the second NMOS 102 are drains of the second NMOS 102, a cathode of a diode D3 inside the second NMOS 102 is connected with the drain of the second NMOS 102, and an anode of the diode D3 is connected with the source of the second NMOS 102.

In this embodiment, the first driving circuit unit 103 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NPN transistor Q1, a first PNP transistor Q2, a third NMOS transistor Q3, a first capacitor C1, and a first diode D1.

Specifically, the third NMOS transistor Q3 is a 3-pin packaged NMOS transistor, the gate G of the third NMOS transistor Q3 is an input end of the first driving circuit unit 103, the gate G of the third NMOS transistor Q3 is connected to the first control output end P1 of the main control circuit unit 106 and the first end of the first resistor R1, the drain of the third NMOS transistor Q3 is connected to the base of the first NPN transistor Q1 and the base of the first PNP transistor Q2, and both the source of the third NMOS transistor Q3 and the second end of the first resistor R1 are grounded; the collector of the first NPN triode Q1 is connected with the first end of the second resistor R2, the second end of the second resistor R2 is connected with the base of the first NPN triode Q1, and the emitter of the first NPN triode Q1 is respectively connected with the emitter of the first PNP triode Q2 and the first end of the third resistor R3; the collector electrode of the first PNP triode Q2 is grounded; the second end of the third resistor R3 is an output end of the first driving circuit unit 103, and the second end of the third resistor R3 is connected with the gate of the first NMOS tube 101; the first end of the fourth resistor R4 is connected with the gate of the first NMOS 101, and the second end of the fourth resistor R4 is connected with the drain of the second NMOS 102; the first end of the second resistor R2 is also connected with the cathode of the first diode D1 and the first end of the first capacitor C1 respectively; the anode of the first diode D1 is connected with the power supply output end VOUT; the second end of the first capacitor C1 is connected to the second end of the inductor L1.

In this embodiment, the second driving circuit unit 104 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a second NPN transistor Q4, and a second PNP transistor Q5.

Specifically, the first end of the fifth resistor R5 is an input end of the second driving circuit unit 104, the first end of the fifth resistor R5 is connected to the second control output end P2 of the main control circuit unit 106, the second end of the fifth resistor R5 is connected to the base of the second NPN triode Q4, the base of the second PNP triode Q5 and the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is grounded; the collector of the second NPN triode Q4 is connected to the power output terminal VOUT, and the emitter of the second NPN triode Q4 is connected to the emitter of the second PNP triode Q5 and the first end of the seventh resistor R7, respectively; the collector electrode of the second PNP triode Q5 is grounded; the second end of the seventh resistor R7 is an output end of the second driving circuit unit 104, the second end of the seventh resistor R7 is connected to the gate of the second NMOS transistor 102, the first end of the eighth resistor R8 is connected to the gate of the second NMOS transistor 102, and the second end of the eighth resistor R8 is grounded.

In this embodiment, the output capacitor array 105 includes 4 capacitors, which are a capacitor C5, a capacitor C6, a capacitor C7, and a capacitor C8, wherein one end of the capacitor C5, the capacitor C6, the capacitor C7, and the capacitor C8 connected in parallel is connected to the power output terminal VOUT, and the other end of the capacitor C5, the capacitor C6, the capacitor C7, and the capacitor C8 connected in parallel is grounded.

In this embodiment, the main control circuit unit 106 includes a voltage sampling circuit sub-unit 1061 for sampling the voltage of the power output terminal VOUT, and a controller 1062 for controlling the operation of the first driving circuit unit 103 and the second driving circuit unit 104 according to the voltage sampled by the voltage sampling circuit sub-unit 1061 and the preset target boost value. Wherein a sampling input terminal of the voltage sampling circuit subunit 1061 is connected to the power output terminal VOUT, and a sampling output terminal of the voltage sampling circuit subunit 1061 is connected to a sampling input terminal (not numbered) of the controller 1062; the control output end of the controller 1062 includes a first control output end P1 and a second control output end P2, the first control output end P1 of the controller 1062 is connected to the input end of the first driving circuit unit 103, that is, the first control output end P1 of the controller 1062 is connected to the gate G of the third NMOS Q3, and the second control output end P2 of the controller 1062 is connected to the input end of the second driving circuit unit 104, that is, the second control output end P2 of the controller 1062 is connected to the first end of the fifth resistor R5.

In this embodiment, the voltage sampling circuit subunit 1061 includes a ninth resistor R9 and a tenth resistor R10. The first end of the ninth resistor R9 is a sampling input end of the voltage sampling circuit subunit 1061, the first end of the ninth resistor R9 is connected to the power output end VOUT, the second end of the ninth resistor R9 is a sampling output end of the voltage sampling circuit subunit 1061, the second ends of the ninth resistor R9 are respectively connected to the sampling input end of the controller 1062 and the first end of the tenth resistor R10, and the second end of the tenth resistor R10 is grounded.

The boost circuit of the present embodiment further includes a filter circuit unit 107 for filtering the voltage of the power input terminal VIN, one end of the filter circuit unit 107 is connected to the power input terminal VIN, and the other end of the filter circuit unit 107 is grounded. Specifically, in the present embodiment, the filter circuit unit 107 includes a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. One end of the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 connected in parallel with each other is connected to the power input terminal VIN, and the other end of the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 connected in parallel with each other is grounded.

The working principle of the booster circuit of this embodiment is specifically described as follows: in this embodiment, the controller 1062 outputs a first PWM control signal PWM1 from the first control output terminal P1 to the input terminal of the first driving circuit unit 103 according to the voltage sampled by the voltage sampling circuit subunit 1061 and a preset target boost value, and the first driving circuit unit 103 drives the switching action of the first NMOS transistor 101 according to the received first PWM control signal PWM 1; meanwhile, the controller 1062 outputs a second PWM control signal PWM2 from the second control output terminal P2 to the input terminal of the second driving circuit unit 104, the second driving circuit unit 104 drives the switching action of the second NMOS 102 according to the received second PWM control signal PWM2, the inductor L1 stores or releases electric energy according to the switching actions of the first NMOS 101 and the second NMOS 102, and the inductor L1 is matched with the output capacitor array 105 to realize the voltage boosting function of the power supply input terminal VIN.

Specifically, in this embodiment, when the voltage difference between the gate and the source of the second NMOS 102 is higher than the on threshold of the second NMOS 102, the second NMOS 102 may be turned on; when the voltage difference between the gate and the source of the second NMOS transistor 102 is lower than the on threshold of the second NMOS transistor 102, the second NMOS transistor 102 is turned off. In this embodiment, the base of the second PNP transistor Q5 is turned on only when it is at a low level, and the base of the second NPN transistor Q4 is turned on only when it is at a high level. Therefore, when the second control signal PWM2 output from the second control output terminal P2 of the controller 1062 is at a high level, the second PNP transistor Q5 is turned off, the second NPN transistor Q4 is turned on, and the voltage of the power output terminal VOUT is directly applied to the gate of the second NMOS transistor 102 through the CE junction of the second NPN transistor Q4, so that the second NMOS transistor 102 is turned on; and when the second control signal PWM2 output from the second control output terminal P2 of the controller 1062 is at a low level, the second NPN transistor Q4 is turned off, and the second PNP transistor Q5 is turned on, so that the gate of the second NMOS transistor 102 is at a low level, and the second NMOS transistor 102 is turned off.

In this embodiment, when the voltage difference between the gate and the source of the first NMOS 101 is higher than the turn-on threshold of the first NMOS 101, the first NMOS 101 may be turned on; when the voltage difference between the gate and the source of the first NMOS 101 is lower than the on threshold of the first NMOS 101, the first NMOS 101 is turned off. In this embodiment, the base of the first PNP transistor Q2 is turned on only when it is at a low level, and the base of the first NPN transistor Q1 is turned on only when it is at a high level. Therefore, when the first control signal PWM1 output from the first control output terminal P1 of the controller 1062 is at a high level, the third NMOS transistor Q3 is turned on, the base of the first PNP transistor Q2 and the base of the first NPN transistor Q1 are both at a low level, and the first PNP transistor Q2 is turned on, so that the gate of the first NMOS transistor 101 is at a low level, and the first NMOS transistor 101 is turned off. When the first control signal PWM1 output from the first control output terminal P1 of the controller 1062 is at a low level, the third NMOS transistor Q3 is turned off, the base of the first PNP transistor Q2 and the base of the first NPN transistor Q1 are both at a high level, and the first NPN transistor Q1 is turned on, so that the gate of the first NMOS transistor 101 is at a high level, and the first NMOS transistor 101 is turned on.

In the boost circuit of this embodiment, when the second NMOS transistor 102 is turned on and the first NMOS transistor 101 is turned off, the inductor L1 stores the electric energy of the power input terminal VIN, and at this time, the output capacitor array 105 formed by the capacitor C5, the capacitor C6, the capacitor C7 and the capacitor C8 supplies power to the power output terminal VOUT; when the first NMOS 101 is turned on and the second NMOS 102 is turned off, the inductor L1 releases electric energy, at this time, the voltage at the power input end VIN and the voltage on the inductor L1 are superimposed to supply power to the power output end VOUT, and charge the output capacitor array 105 at the same time, at this time, the voltage at the power output end VOUT is far higher than the voltage at the power input end VIN, and when the first NMOS 101 and the second NMOS 102 continue to switch, the voltage at the power output end VOUT can reach a preset target boost value, so that the boost circuit in this embodiment achieves the boost function. It can be appreciated that the preset target boost value in this embodiment may be set according to actual needs.

In this embodiment, when the second NMOS 102 is turned off, the inductor L1 generates a reverse electromotive force, the current on the inductor L1 is not suddenly changed, but is gradually reduced, at this time, the first NMOS 101 is controlled to be turned on, at this time, the voltage at the power input terminal VIN and the voltage on the inductor L1 are superimposed and then power is supplied to the power output terminal VOUT, and meanwhile, the output capacitor array 105 is charged, at this time, the voltage at the power output terminal VOUT is equal to the sum of the voltage at the power input terminal VIN and the voltage on the inductor L1, which is the boosting principle of the boost circuit in this embodiment.

In addition, it should be noted that, in the embodiment, the seventh resistor R7 is a gate current limiting resistor of the second NMOS transistor 102, the eighth resistor R8 is a gate pull-down resistor of the second NMOS transistor 102, and the gate of the second NMOS transistor 102 is guaranteed to be at a low level during power-up, that is, the second NMOS transistor 102 is guaranteed to be turned off during power-up. Similarly, in this embodiment, the third resistor R3 is a gate current limiting resistor of the first NMOS 101, and the fourth resistor R4 is a gate pull-down resistor of the first NMOS 101.

Fig. 2 is a schematic waveform diagram of a first control signal PWM1 and a second control signal PWM2 output by the controller in an embodiment of the boost circuit of the present invention. Referring to fig. 1 and 2 together, in the boost circuit of the present embodiment, when the second PWM control signal PWM2 output from the second control output terminal P2 of the controller 1062 is at a high level, the second NMOS 102 is turned on, and when the second PWM control signal PWM2 output from the second control output terminal P2 of the controller 1062 is at a low level, the second NMOS 102 is turned off. Just because of the conduction of the second NMOS 102, the power input terminal VIN, the inductor L1 and the second NMOS 102 form a loop, and the inductor L1 stores the electric energy of the power input terminal VIN. In this embodiment, the function of the first capacitor C1 is mainly to raise the voltage at the point a in fig. 1 (i.e., the voltage of the collector of the first NPN triode Q1), so as to ensure that the gate voltage of the first NMOS tube 101 is higher than the source voltage of the first NMOS tube 101, thereby realizing the conduction of the first NMOS tube 101. Specifically, when the second NMOS 102 is turned on and the inductor L1 stores the electric energy of the power input terminal VIN, the voltage of the second terminal of the first capacitor C1 (corresponding to the left end of the first capacitor C1 in the drawing) is at a low level, and the voltage value of the first terminal of the first capacitor C1 (corresponding to the right end of the first capacitor C1 in the drawing) is equal to the voltage of the power output terminal VOUT minus the voltage drop of the first diode D1; when the second NMOS 102 is turned off, the inductor L1 generates a reverse electromotive force, the inductor L1 charges the first capacitor C1, resulting in a voltage rise at the first end of the first capacitor C1, and when the first PWM control signal PWM1 output from the first control output terminal P1 of the controller 1062 is at a low level, the third NMOS Q3 is turned off, at this time, the voltage Va at the point a is applied to the gate of the first NMOS 101 through the CE junction of the first NPN triode Q1, and the voltage Va at the point a is higher than the source voltage of the first NMOS 101, so that the first NMOS 101 is turned on, and at this time, the first diode D1 plays an isolating role.

In summary, in the boost circuit of this embodiment, when the second PWM control signal PWM2 output by the second control output terminal P2 of the controller 1062 and the first PWM control signal PWM1 output by the first control output terminal P1 of the controller 1062 are both at low level, the second NMOS 102 is turned off, the first NMOS 101 is turned on, the inductor L1 releases electric energy, and at this time, the voltage at the power input terminal VIN and the voltage on the inductor L1 are superimposed to supply power to the power output terminal VOUT and charge the output capacitor array 105; when the second PWM control signal PWM2 output from the second control output terminal P2 of the controller 1062 is at a low level and the first PWM control signal PWM1 output from the first control output terminal P1 of the controller 1062 is at a high level, neither the first NMOS transistor 101 nor the second NMOS transistor 102 is turned on; when the second PWM control signal PWM2 output by the second control output terminal P2 of the controller 1062 and the first PWM control signal PWM1 output by the first control output terminal P1 of the controller 1062 are at a high level at the same time, the second NMOS 102 is turned on, the first NMOS 101 is turned off, at this time, the inductor L1 stores energy of the power input terminal VIN, and the output capacitor array 105 supplies power to the power output terminal VOUT.

In the boost circuit of the embodiment, the first driving circuit unit 103 for driving the first NMOS 101 to switch and the second driving circuit unit 104 for driving the second NMOS 102 to switch are both composed of simple components, so that the scheme of adopting a MOSFET driving chip in the prior art is replaced, and the boost circuit of the embodiment can reduce the cost of the circuit while meeting the boost requirement and improving the load capacity; in addition, the embodiment can also improve the boosting efficiency and the output power; meanwhile, the embodiment also has the advantages of simple structure and easy realization.

The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims

1. The boost circuit is characterized by comprising a power input end, a power output end, a first NMOS tube, a second NMOS tube, a first driving circuit unit for driving the first NMOS tube to switch, a second driving circuit unit for driving the second NMOS tube to switch, an inductor for storing or releasing electric energy according to the switching actions of the first NMOS tube and the second NMOS tube, an output capacitor array for storing the electric energy of the power input end and the electric energy released by the inductor, supplying power to the power output end and filtering the voltage of the power output end, and a main control circuit unit for controlling the first driving circuit unit and the second driving circuit unit to work according to the voltage of the power output end and a preset target boost value; wherein:

2. The boost circuit of claim 1, wherein said first drive circuit unit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first NPN transistor, a first PNP transistor, a third NMOS transistor, a first capacitor, and a first diode; wherein:

3. The boost circuit of claim 1, wherein said second drive circuit unit comprises a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a second NPN transistor, and a second PNP transistor; wherein:

4. The boost circuit of claim 1, wherein said output capacitor array comprises at least 2 capacitors, one end of said at least 2 capacitors connected in parallel is connected to said power supply output, and the other end of said at least 2 capacitors connected in parallel is grounded.

5. The booster circuit of claim 1 wherein the master control circuit unit includes a voltage sampling circuit subunit for sampling a voltage of the power supply output terminal and a controller for controlling the operation of the first drive circuit unit and the second drive circuit unit according to the voltage sampled by the voltage sampling circuit subunit and the preset target boost value; wherein:

6. The boost circuit of claim 5, wherein said voltage sampling circuit subunit comprises a ninth resistor and a tenth resistor; wherein:

7. The booster circuit according to any one of claims 1 to 6, further comprising a filter circuit unit for filtering a voltage of the power supply input terminal, one end of the filter circuit unit being connected to the power supply input terminal, and the other end of the filter circuit unit being grounded.

8. The boost circuit of claim 7, wherein said filter circuit unit comprises a second capacitor, a third capacitor, and a fourth capacitor; wherein: