CN107086772A - Booster circuit - Google Patents
Booster circuit Download PDFInfo
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- CN107086772A CN107086772A CN201710264109.XA CN201710264109A CN107086772A CN 107086772 A CN107086772 A CN 107086772A CN 201710264109 A CN201710264109 A CN 201710264109A CN 107086772 A CN107086772 A CN 107086772A
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- Prior art keywords
- nmos tube
- resistance
- circuit unit
- output end
- drive circuit
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a kind of booster circuit, the booster circuit includes power input, power output end, the first NMOS tube, the second NMOS tube, the first drive circuit unit, the second drive circuit unit, inductance, output capacitance array and main control circuit unit；Power input is connected through inductance with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube, the drain electrode of first NMOS tube is connected with one end of output capacitance array and power output end, the other end ground connection of output capacitance array, the grid of the first NMOS tube is connected with the output end of the first drive circuit unit；The source ground of second NMOS tube, the grid of the second NMOS tube is connected with the output end of the second drive circuit unit；The input of first drive circuit unit and the second drive circuit unit is connected with main control circuit unit, and main control circuit unit is also connected with power output end.The present invention reduces cost while meeting boosting requirement and improving load capacity.
Description
Technical field
The present invention relates to electronic technology field, more particularly to a kind of booster circuit.
Background technology
At present, lithium battery is widely used in all kinds of consumer electronics products, such as desk lamp, portable power source, atomizer, shaves
Knife, small fan and toy etc., but be due to lithium battery discharge voltage range be usually 2.8V to 4.3V, and for above-mentioned consumption
Electronic product, is generally required for using 5V voltages or higher voltage, therefore, is produced using the consumer electronics of lithium battery power supply
Corresponding DC-DC booster circuit is both provided with product.
In the prior art, the DC-DC booster circuit in most of consumer electronics products is all to use Boost boost chips
To realize the boost function to lithium battery voltage, but the DC-DC booster circuit institute of boosting is realized using Boost boost chips
The magnitude of voltage of output is changeless, and its band carries electric current generally all within 1A, so as to limit consumer electronics product
Maximum power value；Also, when above-mentioned DC-DC booster circuit is applied to the application scenarios of high pressure or heavy duty, it is necessary to additional
MOSFET driving chips realize the purpose of adjustment boost value, and the DC-DC booster circuit of additional MOSFET driving chips, due to
The price of MOSFET driving chips is costly so that the DC-DC booster circuit has the higher defect of circuit cost.
The content of the invention
The main object of the present invention is to propose a kind of booster circuit, it is intended to meets boosting and requires and improve load capacity
Meanwhile, reduce the cost of circuit.
To achieve these goals, the present invention provides a kind of booster circuit, and the booster circuit includes power input, electricity
Source output terminal, the first NMOS tube, the second NMOS tube, the first drive circuit list for driving the first NMOS tube switch motion
Member, the second drive circuit unit for driving the second NMOS tube switch motion, for according to first NMOS tube and
The switch motion of second NMOS tube carries out electrical power storage or electric releasable inductance, for the electricity to the power input
The electric energy that can be discharged with the inductance is stored, the power output end is powered and to the power output end
The output capacitance array that is filtered of voltage and boosted for the voltage according to the power output end and default target
Value controls the main control circuit unit of first drive circuit unit and second drive circuit unit work；Wherein：
The power input is connected with the first end of the inductance, the second end of the inductance respectively with the first NMOS tube
Source electrode and the second NMOS tube drain electrode connection, drain electrode one end respectively with the output capacitance array of first NMOS tube
And power output end connection, the other end ground connection of the output capacitance array, the grid of first NMOS tube with it is described
The output end connection of first drive circuit unit；The source ground of second NMOS tube, the grid of second NMOS tube with
The output end connection of second drive circuit unit；The input of first drive circuit unit and the second driving electricity
Control output end of the input of road unit with the main control circuit unit is connected；The sampling input of the main control circuit unit
End is connected with the power output end.
Preferably, first drive circuit unit includes first resistor, second resistance, 3rd resistor, the 4th resistance, the
One NPN triode, the first PNP triode, the 3rd NMOS tube, the first electric capacity and the first diode；Wherein：
The grid of 3rd NMOS tube is the input of first drive circuit unit, the grid of the 3rd NMOS tube
Pole is connected with the control output end of the main control circuit unit and the first end of the first resistor respectively, the 3rd NMOS tube
Drain electrode be connected respectively with the base stage of first NPN triode and the base stage of first PNP triode, the 3rd NMOS
Second end of the source electrode of pipe and the first resistor is grounded；The colelctor electrode of first NPN triode and the second resistance
First end connection, the second end of the second resistance is connected with the base stage of first NPN triode, the first NPN tri-
The emitter stage of pole pipe is connected with the emitter stage of first PNP triode and the first end of the 3rd resistor respectively；Described
The grounded collector of one PNP triode；Second end of the 3rd resistor is the output end of first drive circuit unit, institute
The second end for stating 3rd resistor is connected with the grid of first NMOS tube；The first end and described first of 4th resistance
The grid connection of NMOS tube, the second end of the 4th resistance is connected with the drain electrode of second NMOS tube；The second resistance
First end be also connected respectively with the negative electrode of first diode and the first end of first electric capacity；First diode
Anode be connected with the power output end；Second end of first electric capacity is connected with the second end of the inductance.
Preferably, second drive circuit unit includes the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the
Two NPN triodes and the second PNP triode；Wherein：
The first end of 5th resistance is the input of second drive circuit unit, the first of the 5th resistance
End is connected with the control output end of the main control circuit unit, the second end of the 5th resistance respectively with the 2nd NPN tri-
The first end connection of the base stage of pole pipe, the base stage of second PNP triode and the 6th resistance, the of the 6th resistance
Two ends are grounded；The colelctor electrode of second NPN triode is connected with the power output end, the hair of second NPN triode
Emitter-base bandgap grading is connected with the emitter stage of second PNP triode and the first end of the 7th resistance respectively；The poles of 2nd PNP tri-
The grounded collector of pipe；Second end of the 7th resistance is the output end of second drive circuit unit, the 7th electricity
Second end of resistance is connected with the grid of second NMOS tube, the first end of the 8th resistance and the grid of second NMOS tube
Pole is connected, the second end ground connection of the 8th resistance.
Preferably, the output capacitance array includes at least two electric capacity, one end after at least two electric capacity is in parallel with
The power output end connection, the other end ground connection after at least two electric capacity is in parallel.
Preferably, the voltage that the main control circuit unit includes being used to sample to the voltage of the power output end is adopted
Sample circuit subelement and voltage and the default target for being sampled according to the voltage sampling circuit subelement
Boost value controls the controller of first drive circuit unit and second drive circuit unit work；Wherein：
The sampling input of the voltage sampling circuit subelement is connected with the power output end, the voltage sample electricity
The sampled output of way unit is connected with the sampling input of the controller；The control output end of the controller includes the
One control output end and the second control output end, the first control output end of the controller and first drive circuit unit
Input connection, the second control output end of the controller is connected with the input of second drive circuit unit.
Preferably, the voltage sampling circuit subelement includes the 9th resistance and the tenth resistance；Wherein：
The first end of 9th resistance is the sampling input of the voltage sampling circuit subelement, the 9th resistance
First end be connected with the power output end, the second end of the 9th resistance being adopted for the voltage sampling circuit subelement
Sample output end, the second end of the 9th resistance respectively with the sampling input of the controller and the tenth resistance first
End connection, the second end ground connection of the tenth resistance.
Preferably, the booster circuit also includes the filter circuit for being used to be filtered the voltage of the power input
Unit, one end of the filter circuit unit is connected with the power input, the other end ground connection of the filter circuit unit.
Preferably, the filter circuit unit includes the second electric capacity, the 3rd electric capacity and the 4th electric capacity；Wherein：
Second electric capacity, the 3rd electric capacity and the 4th electric capacity it is parallel with one another after one end and the power input
End connection, second electric capacity, the 3rd electric capacity and the 4th electric capacity it is parallel with one another after the other end ground connection.
The present invention provides a kind of booster circuit, and the booster circuit includes power input, power output end, the first NMOS
Pipe, the second NMOS tube, the first drive circuit unit for driving the first NMOS tube switch motion, for driving described
Second drive circuit unit of two NMOS tube switch motions, for opening according to first NMOS tube and second NMOS tube
Pass action carries out electrical power storage or electric releasable inductance, discharged for the electric energy to the power input and the inductance
Electric energy stored, the power output end is powered and the voltage of the power output end be filtered it is defeated
Go out capacitor array and for first driving of the voltage according to the power output end and the control of default target boost value
Circuit unit and the main control circuit unit of second drive circuit unit work；The of the power input and the inductance
One end is connected, and the second end of the inductance is connected with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube respectively, and described the
The drain electrode of one NMOS tube is connected with one end of the output capacitance array and the power output end respectively, the output capacitance battle array
The other end ground connection of row, the grid of first NMOS tube is connected with the output end of first drive circuit unit；Described
The source ground of two NMOS tubes, the grid of second NMOS tube is connected with the output end of second drive circuit unit；Institute
State the first drive circuit unit input and second drive circuit unit input with the main control circuit unit
Control output end connection；The sampling input of the main control circuit unit is connected with the power output end.Present invention boosting
Circuit reduces the cost of circuit while meeting boosting requirement and improving load capacity；Meanwhile, the present invention also has knot
Structure is simple and the advantage easily realized.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Structure according to these accompanying drawings obtains other accompanying drawings.
Fig. 1 is the structural representation of the embodiment of booster circuit one of the present invention；
Fig. 2 is the controls of the first control signal PWM1 and second of controller output described in the embodiment of booster circuit one of the present invention
Signal PWM2 processed waveform diagram.
The realization, functional characteristics and advantage of the object of the invention will be described further referring to the drawings in conjunction with the embodiments.
Embodiment
It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not intended to limit the present invention.
The present invention provides a kind of booster circuit, reference picture 1, and Fig. 1 is the structural representation of the embodiment of booster circuit one of the present invention
In figure, the present embodiment, the booster circuit includes power input VIN, power output end VOUT, the first NMOS tube 101, second
NMOS tube 102, the first drive circuit unit 103 of switch motion for driving first NMOS tube 101, for driving
State the second drive circuit unit 104 of the switch motion of the second NMOS tube 102, for according to first NMOS tube 101 and institute
The switch motion for stating the second NMOS tube 102 carries out electrical power storage or electric releasable inductance L1, for the power input
The electric energy that VIN electric energy and the inductance L1 are discharged is stored, the power output end VOUT is powered and right
Output capacitance array 105 that the voltage of the power output end VOUT is filtered, for according to the power output end VOUT
Voltage and default target boost value control first drive circuit unit 103 and second drive circuit unit
The main control circuit unit 106 of 104 work.In the present embodiment, the voltage of the power input VIN is provided by lithium battery.
Specifically, in the present embodiment, the power input VIN is connected with the first end of the inductance L1, the inductance
L1 the second end is connected with the source electrode of the first NMOS tube 101 and the drain electrode of the second NMOS tube 102 respectively, first NMOS tube
101 drain electrode is connected with one end of the output capacitance array 105 and the power output end VOUT respectively, the output capacitance
The other end ground connection of array 105, the output end of the grid of first NMOS tube 101 and first drive circuit unit 103
Connection；The source ground of second NMOS tube 102, the grid of second NMOS tube 102 and the second drive circuit list
The output end connection of member 104；The input of first drive circuit unit 103 and second drive circuit unit 104
Control output end of the input with the main control circuit unit 106 is connected；The sampling input of the main control circuit unit 106
It is connected with the power output end VOUT.
In the present embodiment, first NMOS tube 101 and second NMOS tube 102 are the NMOS of 8 pin packages
Pipe.Wherein, the 1st pin, the 2nd pin and the 3rd pin of first NMOS tube 101 are the source electrode of first NMOS tube 101, described
4th pin of the first NMOS tube 101 is the grid of first NMOS tube 101, the 5th pin of first NMOS tube 101, the 6th pin,
7th pin and the 8th pin are the drain electrode of first NMOS tube 101, the negative electrode of the diode D2 inside first NMOS tube 101
Drain electrode with first NMOS tube 101 is connected, and the anode of the diode D2 and the source electrode of first NMOS tube 101 connect
Connect.The 1st pin, the 2nd pin and the 3rd pin of second NMOS tube 102 are the source electrode of second NMOS tube 102, described second
4th pin of NMOS tube 102 is the grid of second NMOS tube 102, the 5th pin of second NMOS tube 102, the 6th pin, the 7th
Pin and the 8th pin be the diode D3 inside the drain electrode of second NMOS tube 102, second NMOS tube 102 negative electrode with
The drain electrode connection of second NMOS tube 102, the anode of the diode D3 is connected with the source electrode of second NMOS tube 102.
In the present embodiment, first drive circuit unit 103 includes first resistor R1, second resistance R2,3rd resistor
R3, the 4th resistance R4, the first NPN triode Q1, the first PNP triode Q2, the 3rd NMOS tube Q3, the first electric capacity C1 and the one or two
Pole pipe D1.
Specifically, the 3rd NMOS tube Q3 is the NMOS tube that 3 pin are encapsulated, and the grid G of the 3rd NMOS tube Q3 is
The input of first drive circuit unit 103, the grid G of the 3rd NMOS tube Q3 respectively with the main control circuit unit
106 the first control output end P1 and the first resistor R1 first end connection, the drain electrode point of the 3rd NMOS tube Q3
It is not connected with the base stage of first NPN triode Q1 and the base stage of the first PNP triode Q2, the 3rd NMOS tube Q3
Source electrode and the second end of the first resistor R1 be grounded；The colelctor electrode of first NPN triode Q1 and the described second electricity
R2 first end connection is hindered, the second end of the second resistance R2 is connected with the base stage of first NPN triode Q1, described the
The emitter stage of one NPN triode Q1 respectively with the emitter stage of the first PNP triode Q2 and the 3rd resistor R3 first
End connection；The grounded collector of the first PNP triode Q2；The second end of the 3rd resistor R3 is the described first driving electricity
The output end of road unit 103, the second end of the 3rd resistor R3 is connected with the grid of first NMOS tube 101；Described
Four resistance R4 first end is connected with the grid of first NMOS tube 101, the second end of the 4th resistance R4 and described the
The drain electrode connection of two NMOS tubes 102；The first end of the second resistance R2 also respectively with the negative electrode of the first diode D1 and
The first end connection of the first electric capacity C1；The anode of the first diode D1 is connected with the power output end VOUT；Institute
The second end for stating the first electric capacity C1 is connected with the second end of the inductance L1.
In the present embodiment, second drive circuit unit 104 includes the 5th resistance R5, the 6th resistance R6, the 7th resistance
R7, the 8th resistance R8, the second NPN triode Q4 and the second PNP triode Q5.
Specifically, the first end of the 5th resistance R5 is the input of second drive circuit unit 104, described the
Five resistance R5 first end is connected with the second control output end P2 of the main control circuit unit 106, the 5th resistance R5's
Base stage, the base stage of the second PNP triode Q5 and the 6th resistance of second end respectively with the second NPN triode Q4
R6 first end connection, the second end ground connection of the 6th resistance R6；The colelctor electrode of the second NPN triode Q4 and the electricity
Source output terminal VOUT connections, the emitter stage of the emitter stage of the second NPN triode Q4 respectively with the second PNP triode Q5
And the first end connection of the 7th resistance R7；The grounded collector of the second PNP triode Q5；The 7th resistance R7's
Second end is the output end of second drive circuit unit 104, the second end and the 2nd NMOS of the 7th resistance R7
The grid connection of pipe 102, the first end of the 8th resistance R8 is connected with the grid of second NMOS tube 102, and the described 8th
Resistance R8 the second end ground connection.
In the present embodiment, the output capacitance array 105 includes 4 electric capacity, respectively electric capacity C5, electric capacity C6, electric capacity C7
And electric capacity C8, the electric capacity C5, electric capacity C6, electric capacity C7 and electric capacity C8 it is parallel with one another after one end and the power output end VOUT
Connection, the electric capacity C5, electric capacity C6, electric capacity C7 and electric capacity C8 it is parallel with one another after the other end ground connection.
In the present embodiment, the main control circuit unit 106 includes being used for carrying out the voltage of the power output end VOUT
The voltage sampling circuit subelement 1061 of sampling and the electricity for being sampled according to the voltage sampling circuit subelement 1061
Pressure and the default target boost value control first drive circuit unit 103 and second drive circuit unit
The controller 1062 of 104 work.Wherein, the sampling input of the voltage sampling circuit subelement 1061 is exported with the power supply
Hold VOUT connections, the sampling input of the sampled output of the voltage sampling circuit subelement 1061 and the controller 1062
(the non-label of figure) connection；The control output end of the controller 1062 includes the first control output end P1 and the second control output end
P2, the first control output end P1 of the controller 1062 is connected with the input of first drive circuit unit 103, i.e. institute
The the first control output end P1 for stating controller 1062 is connected with the grid G of the 3rd NMOS tube Q3, the controller 1062
The second control output end P2 be connected with the input of second drive circuit unit 104, i.e., the of described controller 1062
Two control output end P2 are connected with the first end of the 5th resistance R5.
In the present embodiment, the voltage sampling circuit subelement 1061 includes the 9th resistance R9 and the tenth resistance R10.Its
In, the first end of the 9th resistance R9 is the sampling input of the voltage sampling circuit subelement 1061, the 9th electricity
Resistance R9 first end is connected with the power output end VOUT, and the second end of the 9th resistance R9 is the voltage sampling circuit
The sampled output of subelement 1061, the sampling input of the second end of the 9th resistance R9 respectively with the controller 1062
And the first end connection of the tenth resistance R10, the second end ground connection of the tenth resistance R10.
The present embodiment booster circuit also includes the filter circuit for being used to be filtered the voltage of the power input VIN
Unit 107, one end of the filter circuit unit 107 is connected with the power input VIN, the filter circuit unit 107
The other end ground connection.Specifically, in the present embodiment, the filter circuit unit 107 include the second electric capacity C2, the 3rd electric capacity C3 and
4th electric capacity C4.Wherein, one end after the second electric capacity C2, the 3rd electric capacity C3 and the 4th electric capacity C4 are parallel with one another
It is connected with the power input VIN, the second electric capacity C2, the 3rd electric capacity C3 and the 4th electric capacity C4 are parallel with one another
Other end ground connection afterwards.
The operation principle of the present embodiment booster circuit is described in detail below：In the present embodiment, the basis of controller 1062
Voltage and default target boost value that the voltage sampling circuit subelement 1061 is sampled, from its first control output
P1 is held to export the first pwm control signal PWM1 to the input of first drive circuit unit 103, first drive circuit
Unit 103 drives the switch motion of first NMOS tube 101 according to the first pwm control signal PWM1 received；Together
When, the controller 1062 is electric from its second control output end P2 output drivings of the second pwm control signal PWM2 to described second
The input of road unit 104, second drive circuit unit 104 is according to the second pwm control signal PWM2 received
The switch motion of second NMOS tube 102 is driven, the inductance L1 is according to first NMOS tube 101 and the 2nd NMOS
The switch motion of pipe 102 carries out electrical power storage or electric energy release, and the inductance L1 coordinates the output capacitance array 105 to realize again
To the boost function of the power input VIN voltage.
Specifically, in the present embodiment, when the voltage difference between the grid and source electrode of second NMOS tube 102 is higher than described
During the unlatching threshold values of the second NMOS tube 102, second NMOS tube 102 can be turned on；When the grid of second NMOS tube 102
When voltage difference between source electrode is less than the unlatching threshold values of second NMOS tube 102, second NMOS tube 102 is then turned off.
In the present embodiment, it could be turned on when due to the base stage of the second PNP triode Q5 being low level, and poles of the 2nd NPN tri-
Pipe Q4 base stage could be turned on when being high level.Therefore, when the second control output end P2 of the controller 1062 export the
When two control signal PWM2 are high level, the second PNP triode Q5 shut-offs, the second NPN triode Q4 conductings are described
Power output end VOUT voltage is directly added to second NMOS tube 102 by the CE knots of the second NPN triode Q4
Grid so that second NMOS tube 102 is turned on；And second of the second control output end P2 outputs when the controller 1062
When control signal PWM2 is low level, the second NPN triode Q4 shut-offs, the second PNP triode Q5 conductings, so that
The grid for obtaining second NMOS tube 102 is low level so that second NMOS tube 102 is turned off.
In the present embodiment, when the voltage difference between the grid and source electrode of first NMOS tube 101 is higher than described first
During the unlatching threshold values of NMOS tube 101, first NMOS tube 101 can be turned on；Grid and source when first NMOS tube 101
When voltage difference between pole is less than the unlatching threshold values of first NMOS tube 101, first NMOS tube 101 is then turned off.This reality
Apply in example, could be turned on when due to the base stage of the first PNP triode Q2 being low level, and first NPN triode Q1
Base stage be high level when could turn on.Therefore, when the first control that the first control output end P1 of the controller 1062 is exported
When signal PWM1 processed is high level, the 3rd NMOS tube Q3 conductings, the base stage and described first of the first PNP triode Q2
The base stage of NPN triode Q1 is low level, the first PNP triode Q2 conductings, so that first NMOS tube 101
Grid be low level, first NMOS tube 101 turns off.Exported as the first control output end P1 of the controller 1062
When first control signal PWM1 is low level, the 3rd NMOS tube Q3 is turned off, the base stage of the first PNP triode Q2 and institute
The base stage for stating the first NPN triode Q1 is high level, the first NPN triode Q1 conducting, so that described first
The grid of NMOS tube 101 is high level so that first NMOS tube 101 is turned on.
The present embodiment booster circuit, it is described when second NMOS tube 102 is turned on, and first NMOS tube 101 is turned off
Inductance L1 carries out energy storage to the electric energy of the power input VIN, now by electric capacity C5, electric capacity C6, electric capacity C7 and electric capacity C8 institutes
105 pairs of the output capacitance array power output end VOUT of composition powers；When first NMOS tube 101 is turned on, institute
When stating the shut-off of the second NMOS tube 102, the inductance L1 discharges the voltage and the electricity of electric energy, now the power input VIN
Sense L1 on voltage it is superimposed after the power output end VOUT is powered, while being filled to the output capacitance array 105
Electricity, now the voltage of the power output end VOUT be far above the voltage of the power input VIN, the present embodiment is when described the
When one NMOS tube 101 and the persistent switch of the second NMOS tube 102 action, the voltage of the power output end VOUT is with regard to that can reach
Default target boost value so that the present embodiment booster circuit realizes the function of boosting.It is understood that in the present embodiment
The default target boost value can be set according to actual needs.
In the present embodiment, when second NMOS tube 102 is turned off, the inductance L1 can produce inverse electromotive force, described
Electric current on inductance L1 will not be mutated, but slowly be diminished, and now control first NMOS tube 101 to turn on again, now institute
State the voltage on power input VIN voltage and the inductance L1 it is superimposed after the power output end VOUT is powered, together
When the output capacitance array 105 is charged, now the voltage of the power output end VOUT be equal to the power input
VIN voltage and the voltage sum on the inductance L1 is held, here it is the boosting principle of the present embodiment booster circuit.
In addition, it is necessary to which in explanation, the present embodiment, the 7th resistance R7 is the grid of second NMOS tube 102
Current-limiting resistance, the 8th resistance R8 is the grid pull down resistor of second NMOS tube 102, it is ensured that second described in during upper electricity
The grid of NMOS tube 102 is low level, that is, ensures what the second NMOS tube 102 described in during upper electricity was off.Similarly, the present embodiment
In, the 3rd resistor R3 is the grid current-limiting resistance of first NMOS tube 101, and the 4th resistance R4 is described first
The grid pull down resistor of NMOS tube 101.
Fig. 2 is the controls of the first control signal PWM1 and second of controller output described in the embodiment of booster circuit one of the present invention
Signal PWM2 processed waveform diagram.Fig. 1 and Fig. 2, the present embodiment booster circuit, when the of the controller 1062 are referred in the lump
When second pwm control signal PWM2 of two control output end P2 outputs is high level, second NMOS tube 102 is turned on, and works as institute
When the second pwm control signal PWM2 for stating the second control output end P2 outputs of controller 1062 is low level, described second
NMOS tube 102 is turned off.Exactly because the conducting of second NMOS tube 102, the power input VIN, the inductance L1 and
Second NMOS tube 102 can just form loop, and the inductance L1 carries out energy storage to the electric energy of the power input VIN.This
In embodiment, the effect of the first electric capacity C1 is primarily to raise voltage (i.e. described first NPN triode of a points in Fig. 1
The voltage of Q1 colelctor electrode), so as to ensure the grid voltage of first NMOS tube 101 higher than first NMOS tube 101
Source voltage, realizes the conducting of first NMOS tube 101.Specifically, when second NMOS tube 102 is turned on, the inductance
When L1 carries out energy storage to the electric energy of the power input VIN, the second end of the first electric capacity C1 is (first described in corresponding diagram
Electric capacity C1 left end) voltage be low level, first end (the first electric capacity C1 right side described in corresponding diagram of the first electric capacity C1
End) magnitude of voltage be equal to the voltage of the power output end VOUT and subtract the pressure drop of the first diode D1；When described second
When NMOS tube 102 is turned off, the inductance L1 can produce inverse electromotive force, and the inductance L1 can charge to the first electric capacity C1,
Cause the voltage rise of the first end of the first electric capacity C1, and when the first control output end P1 of the controller 1062 is exported
The first pwm control signal PWM1 when being low level, the 3rd NMOS tube Q3 shut-off, now the voltage Va of a points passes through described
The CE knots of first NPN triode Q1 are added on the grid of first NMOS tube 101, and the voltage Va of a points is higher than described first
The source voltage of NMOS tube 101 so that first NMOS tube 101 is turned on, now, the first diode D1 plays isolation and made
With.
In summary, the present embodiment booster circuit, when the second control output end P2 of the controller 1062 export the
First pwm control signal PWM1 of the first control output end P1 outputs of two pwm control signal PWM2 and the controller 1062
When simultaneously for low level, second NMOS tube 102 is turned off, and first NMOS tube 101 is turned on, the inductance L1 releases electricity
Can, to the power output end after now the voltage on the voltage of the power input VIN and the inductance L1 is superimposed
VOUT powers, while being charged to the output capacitance array 105；As the second control output end P2 of the controller 1062
Second pwm control signal PWM2 of output is low level, the first of the first control output end P1 outputs of the controller 1062
When pwm control signal PWM1 is high level, first NMOS tube 101 and second NMOS tube 102 are not turned on；When described
The the second pwm control signal PWM2 and the controller 1062 of the second control output end P2 outputs of controller 1062 the first control
When first pwm control signal PWM1 of output end P1 outputs processed is high level simultaneously, second NMOS tube 102 is turned on, described
First NMOS tube 101 is turned off, and now the inductance L1 carries out energy storage, the output electricity to the electric energy of the power input VIN
Hold array 105 to power to the power output end VOUT ends.
The present embodiment booster circuit, due to driving first drive circuit of the switch motion of the first NMOS tube 101
Unit 103 and second drive circuit unit 104 of the driving switch motion of the second NMOS tube 102 are by simple
Component is constituted, and instead of the scheme for using MOSFET driving chips in the prior art, therefore, the present embodiment booster circuit can
While meeting boosting requirement and improving load capacity, the cost of circuit is reduced；Also, the present embodiment can also improve liter
Press efficiency and power output；Meanwhile, the present embodiment also has the advantages that simple in construction and easily realized.
The preferred embodiments of the present invention are these are only, are not intended to limit the scope of the invention, it is every to utilize this hair
Equivalent structure or equivalent flow conversion that bright specification and accompanying drawing content are made, or directly or indirectly it is used in other related skills
Art field, is included within the scope of the present invention.
Claims (8)
1. a kind of booster circuit, it is characterised in that the booster circuit includes power input, power output end, the first NMOS
Pipe, the second NMOS tube, the first drive circuit unit for driving the first NMOS tube switch motion, for driving described
Second drive circuit unit of two NMOS tube switch motions, for opening according to first NMOS tube and second NMOS tube
Pass action carries out electrical power storage or electric releasable inductance, discharged for the electric energy to the power input and the inductance
Electric energy stored, the power output end is powered and the voltage of the power output end be filtered it is defeated
Go out capacitor array and for first driving of the voltage according to the power output end and the control of default target boost value
Circuit unit and the main control circuit unit of second drive circuit unit work；Wherein：
The power input is connected with the first end of the inductance, the source of the second end of the inductance respectively with the first NMOS tube
The drain electrode connection of pole and the second NMOS tube, the one end and the institute that drain respectively with the output capacitance array of first NMOS tube
State power output end connection, the other end ground connection of the output capacitance array, the grid of first NMOS tube and described first
The output end connection of drive circuit unit；The source ground of second NMOS tube, the grid of second NMOS tube with it is described
The output end connection of second drive circuit unit；The input of first drive circuit unit and the second drive circuit list
Control output end of the input of member with the main control circuit unit is connected；The sampling input of the main control circuit unit with
The power output end connection.
2. booster circuit as claimed in claim 1, it is characterised in that first drive circuit unit include first resistor,
Second resistance, 3rd resistor, the 4th resistance, the first NPN triode, the first PNP triode, the 3rd NMOS tube, the first electric capacity and
First diode；Wherein：
The grid of 3rd NMOS tube is the input of first drive circuit unit, the grid point of the 3rd NMOS tube
It is not connected with the control output end of the main control circuit unit and the first end of the first resistor, the leakage of the 3rd NMOS tube
Pole is connected with the base stage of first NPN triode and the base stage of first PNP triode respectively, the 3rd NMOS tube
Second end of source electrode and the first resistor is grounded；The of the colelctor electrode of first NPN triode and the second resistance
One end is connected, and the second end of the second resistance is connected with the base stage of first NPN triode, first NPN triode
Emitter stage be connected respectively with the emitter stage of first PNP triode and the first end of the 3rd resistor；First PNP
The grounded collector of triode；Second end of the 3rd resistor is the output end of first drive circuit unit, described the
Second end of three resistance is connected with the grid of first NMOS tube；The first end of 4th resistance and first NMOS tube
Grid connection, the second end of the 4th resistance is connected with the drain electrode of second NMOS tube；The first of the second resistance
End is also connected with the negative electrode of first diode and the first end of first electric capacity respectively；The anode of first diode
It is connected with the power output end；Second end of first electric capacity is connected with the second end of the inductance.
3. booster circuit as claimed in claim 1, it is characterised in that second drive circuit unit include the 5th resistance,
6th resistance, the 7th resistance, the 8th resistance, the second NPN triode and the second PNP triode；Wherein：
The first end of 5th resistance be second drive circuit unit input, the first end of the 5th resistance with
The control output end connection of the main control circuit unit, the second end of the 5th resistance respectively with second NPN triode
Base stage, the connection of the first end of the base stage of second PNP triode and the 6th resistance, the second end of the 6th resistance
Ground connection；The colelctor electrode of second NPN triode is connected with the power output end, the emitter stage of second NPN triode
It is connected respectively with the emitter stage of second PNP triode and the first end of the 7th resistance；Second PNP triode
Grounded collector；Second end of the 7th resistance is the output end of second drive circuit unit, the 7th resistance
Second end is connected with the grid of second NMOS tube, and the first end of the 8th resistance connects with the grid of second NMOS tube
Connect, the second end ground connection of the 8th resistance.
4. booster circuit as claimed in claim 1, it is characterised in that the output capacitance array includes at least two electric capacity, institute
State one end after the parallel connection of at least two electric capacity to be connected with the power output end, another termination after at least two electric capacity is in parallel
Ground.
5. booster circuit as claimed in claim 1, it is characterised in that the main control circuit unit includes being used for the power supply
Voltage sampling circuit subelement that the voltage of output end is sampled and for being adopted according to the voltage sampling circuit subelement
The voltage and the default target boost value that sample is arrived control first drive circuit unit and second drive circuit
The controller of cell operation；Wherein：
The sampling input of the voltage sampling circuit subelement is connected with the power output end, voltage sampling circuit
The sampled output of unit is connected with the sampling input of the controller；The control output end of the controller includes the first control
Output end processed and the second control output end, the first control output end of the controller are defeated with first drive circuit unit
Enter end connection, the second control output end of the controller is connected with the input of second drive circuit unit.
6. booster circuit as claimed in claim 5, it is characterised in that the voltage sampling circuit subelement includes the 9th resistance
With the tenth resistance；Wherein：
The first end of 9th resistance is the sampling input of the voltage sampling circuit subelement, the of the 9th resistance
One end is connected with the power output end, and the second end of the 9th resistance is defeated for the sampling of the voltage sampling circuit subelement
Go out end, the second end of the 9th resistance connects with the sampling input of the controller and the first end of the tenth resistance respectively
Connect, the second end ground connection of the tenth resistance.
7. the booster circuit as any one of claim 1 to 6, it is characterised in that the booster circuit also includes being used for
The filter circuit unit being filtered to the voltage of the power input, one end and the power supply of the filter circuit unit
Input is connected, the other end ground connection of the filter circuit unit.
8. booster circuit as claimed in claim 7, it is characterised in that the filter circuit unit includes the second electric capacity, the 3rd
Electric capacity and the 4th electric capacity；Wherein：
Second electric capacity, the 3rd electric capacity and the 4th electric capacity it is parallel with one another after one end and the power input connect
Connect, second electric capacity, the 3rd electric capacity and the 4th electric capacity it is parallel with one another after the other end ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710264109.XA CN107086772B (en) | 2017-04-20 | 2017-04-20 | Boost circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710264109.XA CN107086772B (en) | 2017-04-20 | 2017-04-20 | Boost circuit |
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| Publication Number | Publication Date |
|---|---|
| CN107086772A true CN107086772A (en) | 2017-08-22 |
| CN107086772B CN107086772B (en) | 2023-04-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710264109.XA Active CN107086772B (en) | 2017-04-20 | 2017-04-20 | Boost circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111273593A (en) * | 2020-03-23 | 2020-06-12 | 珠海嘉润医用影像科技有限公司 | Endoscope intelligent control circuit |
| CN112165254A (en) * | 2020-08-28 | 2021-01-01 | 苏州浪潮智能科技有限公司 | BBU charging control circuit and storage system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104393755A (en) * | 2014-11-20 | 2015-03-04 | 无锡中星微电子有限公司 | High-efficiency booster circuit |
| CN205092770U (en) * | 2015-10-28 | 2016-03-16 | 深圳市新芯矽创电子科技有限公司 | Power management circuit that steps up |
| CN105553258A (en) * | 2016-01-21 | 2016-05-04 | 长安大学 | Synchronous step-up DC (Direct Current)-DC converter circuit with fixed on-time mode |
-
2017
- 2017-04-20 CN CN201710264109.XA patent/CN107086772B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104393755A (en) * | 2014-11-20 | 2015-03-04 | 无锡中星微电子有限公司 | High-efficiency booster circuit |
| CN205092770U (en) * | 2015-10-28 | 2016-03-16 | 深圳市新芯矽创电子科技有限公司 | Power management circuit that steps up |
| CN105553258A (en) * | 2016-01-21 | 2016-05-04 | 长安大学 | Synchronous step-up DC (Direct Current)-DC converter circuit with fixed on-time mode |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111273593A (en) * | 2020-03-23 | 2020-06-12 | 珠海嘉润医用影像科技有限公司 | Endoscope intelligent control circuit |
| CN111273593B (en) * | 2020-03-23 | 2021-09-21 | 珠海嘉润医用影像科技有限公司 | Endoscope intelligent control circuit |
| CN112165254A (en) * | 2020-08-28 | 2021-01-01 | 苏州浪潮智能科技有限公司 | BBU charging control circuit and storage system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107086772B (en) | 2023-04-25 |
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