CN107071964B - Low voltage difference output current overshoot suppression circuit - Google Patents
Low voltage difference output current overshoot suppression circuit Download PDFInfo
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- CN107071964B CN107071964B CN201710074334.7A CN201710074334A CN107071964B CN 107071964 B CN107071964 B CN 107071964B CN 201710074334 A CN201710074334 A CN 201710074334A CN 107071964 B CN107071964 B CN 107071964B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
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Abstract
The present invention provides a kind of low voltage difference output current overshoot suppression circuit, applied to a constant current driver circuit for LED, the constant current driver circuit for LED includes a power tube drive circuit, the low voltage difference output current overshoot suppression circuit includes a limiting circuit, and the limiting circuit is electrically connected power tube drive circuit to inhibit the output current overshoot in the constant current driver circuit for LED.The low voltage difference output current overshoot suppression circuit has been determined output current overshoot problem of the conventional open-loop constant-current control circuit when input and output voltage is close, and system reliability is improved, and scheme is simply easily achieved.
Description
Technical field
The present invention relates to electronic technology product scope more particularly to a kind of low voltage difference output current overshoot suppression circuits.
Background technique
The constant current driver circuit for LED of opened loop control has many advantages, such as that circuit structure is simple, fast response time, therefore application is wide
It is general.Such as constant current driver circuit for LED such as Fig. 1 based on sluggishness control, the LED constant current based on fixed TOFF and constant peak electric current
Driving circuit Fig. 2.In Fig. 1, traditional sluggish control constant-current drive circuit includes inductive current detection circuit 11, voltage-reference
Circuit 12, retarding window control circuit 13 and power tube drive circuit 14.In Fig. 2, traditional fixation TOFF and constant peak electricity
Flowing constant-current drive circuit includes inductance peak current control circuitry 21, turn-off time control circuit 22, pwm signal generation circuit 23
With power tube drive circuit 14.But foregoing circuit have the shortcomings that one it is common, i.e., when input and output pressure difference is close, export electric current
There are biggish overshoots.As shown in figure 3, when input voltage is reduced to close near output voltage export electric current there are one section compared with
Big overshoot.In the patent application application No. is CN201210591445.2, adopted in buck Switching Power Supply and its controller
Peak point current is limited with maximum turn-on time limiting circuit.For sluggish control or the circuit of constant peak current control,
Because having contained peak current limit circuit in the inherent structure of hysteresis control circuit, same constant peak current control
Circuit inherent structure itself has also contained peak current limit circuit.In traditional hysteresis control circuit, or fixed peak
It is worth in current control circuit, does not need additionally to increase maximum turn-on time limiting circuit to realize that peak point current limits.Tradition
There is no solve the problems, such as low voltage difference output current overshoot in circuit.To solve the problems, such as that foregoing circuit exists, the present invention is proposed
A kind of low voltage difference output current overshoot suppression circuit.
Summary of the invention
The object of the present invention is to provide a kind of when input and output voltage is close effectively inhibits the low pressure of output current overshoot
Poor output current overshoot suppression circuit.
The purpose of the present invention can be achieved by the following technical measures: a kind of low voltage difference output current overshoot suppression circuit,
Applied to a constant current driver circuit for LED, the constant current driver circuit for LED includes a power tube drive circuit, and the low voltage difference is defeated
Current over pulse suppression circuit includes a limiting circuit out, and the limiting circuit is electrically connected power tube drive circuit to inhibit described
Output current overshoot in constant current driver circuit for LED.
Preferably, the limiting circuit is a maximum turn-on time limiting circuit.
Preferably, the power tube drive circuit includes an output end and an at least input terminal, the maximum turn-on time
Limiting circuit includes a phase inverter, a constant-current source, a capacitor, a switch and a comparator, and the switch includes a control terminal, one
First end and a second end, the comparator include a first input end, one second input terminal and an output end, the phase inverter
Input terminal be electrically connected the output end of the power tube drive circuit, the output end of the phase inverter is electrically connected the switch
Control terminal, the first end of the switch is electrically connected the constant-current source, the second end ground connection of the switch, the one of the capacitor
End is electrically connected the first end of the switch, the other end ground connection of the capacitor, and the first input end of the comparator electrically connects
One end of the capacitor is connect, the second input terminal of the comparator receives a reference voltage, and the output end of the comparator is electrical
An at least input terminal for the power tube drive circuit is connected to trigger the shutdown of the power tube drive circuit.
Preferably, the power tube drive circuit includes an output end and an at least input terminal, the maximum turn-on time
Limiting circuit includes a counter, and the counter includes a clock signal input terminal, a reset terminal and an output end, the meter
The clock signal input terminal of number device is electrically connected the power tube driving to receive clock signal, the reset terminal of the counter
For the output end of circuit to receive driving signal, the output end of the counter is electrically connected the power tube drive circuit at least
One input terminal is to trigger the shutdown of the power tube drive circuit.
Preferably, the limiting circuit is a lowermost switch frequency limit circuit.
Preferably, the power tube drive circuit includes an output end and an at least input terminal, the lowermost switch frequency
Limiting circuit includes a monostable flipflop, a constant-current source, a capacitor, a switch and a comparator, and the switch includes a control
End, a first end and a second end processed, the comparator include a first input end, one second input terminal and an output end, institute
The input terminal for stating monostable flipflop is electrically connected the output end of the power tube drive circuit to receive driving signal, the list
The output end of steady state trigger is electrically connected the control terminal of the switch, and the first end of the switch is electrically connected the constant current
Source, the second end ground connection of the switch, one end of the capacitor are electrically connected the first end of the switch, the capacitor it is another
End ground connection, the first input end of the comparator are electrically connected one end of the capacitor, the second input termination of the comparator
A reference voltage is received, the output end of the comparator is electrically connected an at least input terminal for the power tube drive circuit to trigger
The shutdown of the power tube drive circuit.
Preferably, the power tube drive circuit includes an output end and an at least input terminal, the lowermost switch frequency
Limiting circuit includes a counter and a monostable flipflop, and the counter includes a clock signal input terminal, a reset terminal
And an output end, the input terminal of the monostable flipflop are electrically connected the output end of the power tube drive circuit to receive and drive
Dynamic signal, the output end of the monostable flipflop are electrically connected the reset terminal of the counter, the clock letter of the counter
Number input terminal is electrically connected at least the one of the power tube drive circuit to receive clock signal, the output end of the counter
Input terminal is to trigger the shutdown of the power tube drive circuit.
Low voltage difference output current overshoot suppression circuit in the present invention, passes through the constant-current drive circuit controlled in conventional open-loop
The maximum turn-on time limiting circuit of middle addition or lowermost switch frequency limit circuit, the average current (peak of control output electric current
The function of value current limit has had other circuits to go to realize), to inhibit low voltage difference output current overshoot.Low voltage difference output
Current over pulse suppression circuit solves output current overshoot of the conventional open-loop constant-current control circuit when input and output voltage is close
Problem, improves system reliability, and scheme is simply easily achieved.
Detailed description of the invention
Fig. 1 is the structure chart of the constant current driver circuit for LED of traditional sluggish control；
Fig. 2 is the structure chart of traditional fixation TOFF and constant peak electric current constant-current drive circuit；
Fig. 3 is the output electric current and input voltage performance diagram of conventional open-loop control circuit；
Fig. 4 is the circuit structure diagram of the output current overshoot of solution hysteresis control circuit of the invention；
Fig. 5 is the circuit knot of the output current overshoot of the fixed TOFF of solution of the invention and constant peak current control circuit
Composition；
Fig. 6 is the circuit diagram of the LED drive circuit of fixed TOFF and constant peak current control；
Fig. 7 A and Fig. 7 B are that low voltage difference overshoots schematic illustration；
Fig. 8 A and Fig. 8 B are that critical point power tube leads directly to schematic diagram；
Fig. 9 is the output current wave figure introduced after maximum turn-on time limiting circuit；
Figure 10 is the circuit structure diagram of maximum turn-on time limiting circuit embodiment one of the invention；
Figure 11 is the circuit structure diagram of maximum turn-on time limiting circuit embodiment two of the invention；
Figure 12 is the circuit structure diagram of lowermost switch frequency limit circuit embodiments one of the invention；
Figure 13 is the circuit structure diagram of lowermost switch frequency limit circuit embodiments two of the invention.
Specific embodiment
To enable above and other objects, features and advantages of the invention to be clearer and more comprehensible, preferably implementation is cited below particularly out
Example, and cooperate shown in attached drawing, it is described in detail below.
Below for based on fixed TOFF (fixed turn-off time) and the constant current driver circuit for LED of constant peak electric current come
Illustrate that low voltage difference overshoots principle.Fig. 6 is the complete circuit of the LED drive circuit of fixed TOFF and constant peak current control.
Fixed TOFF and the LED drive circuit of constant peak current control include LED load D1, D2, inductance L, sustained diode 3,
MOS switch Q, supplying resistance R11, filter capacitor C11, TOFF time set capacitor C12, and peak point current sets resistance R12, fixed
TOFF and constant peak electric current integrated circuit U.Fixed TOFF and constant peak electric current integrated circuit U includes power input pin
Pin TOFF is arranged in VDD, turn-off time, drives end DRV, peak current detection pin CS, ground terminal VSS.It fixes TOFF and consolidates
After determining peak point current integrated circuit U initial power-on, driving end DRV is low level, and MOS switch Q is disconnected, peak current detection pin
CS voltage is zero.After driving end DRV the low level duration reaches the TOFF time span of setting, driving end DRV switchs to high electricity
Flat, MOS switch Q conducting, by LED load D1, D2, what inductance L, MOS switch Q to resistance R12 were formed returns input voltage source VIN
It charges to inductance L on road；Inductive current is gradually increasing；When the voltage of peak current detection pin CS rises to the reference of setting
After voltage, driving end DRV switchs to low level, and MOS switch Q is turned off, LED load D1, D2, inductance L, and the formation of sustained diode 3 is put
Electrical circuit, inductive current are gradually reduced, when driving end DRV in the TOFF that the low level duration is more than setting (when fixed shutdown
Between) after, then driving end DRV overturning is that high level is transferred to charged state again.
Based on Fig. 6, the principle of ease of explanation low voltage difference output overshoot.When input and output voltage pressure difference is larger, inductance electricity
Cleanliness rises, therefore exports electric current are as follows:
Io=Ipk-0.5* △ I
Wherein, Io refers to output electric current；Ipk refers to inductance peak point current；△ I refers to inductance ripple current.
And when input and output voltage (voltage difference at the both ends LED load D1, D2 is output voltage) is close, in the TON stage
(i.e. inductance is in the charging stage), inductance L both ends pressure drop increase with electric current and are become smaller, the non-linear rising of inductive current, such case
Lower output current average is greater than the situation of inductive current linear rise.
Fig. 7 A and Fig. 7 B are low voltage difference overshoot schematic illustrations.
Fig. 7 A is the output current wave figure of inductive current linear rise when input and output pressure difference is larger, exports electricity in Fig. 7 A
Stream mean value Io is equal to the half that inductance peak point current Ipk subtracts inductance ripple current △ I.
Fig. 7 B is the output current wave figure of inductive current non-linear rising when input and output pressure difference is smaller, can from Fig. 7 B
See, in inductive current charging stage (TON stage), due to the non-linear rising of inductive current, the mean value for exporting electric current is greater than
Output electric current mean value in Fig. 7 A in the case of linear rise, when this is low voltage difference the reason of output current overshoot.
Fig. 8 A and Fig. 8 B are that critical point MOS switch Q leads directly to schematic diagram, inductive current linear rise in Fig. 8 A, and is inputting
When voltage and the close specific critical point of output voltage, because the peak point current of default is not achieved in inductance peak point current always
Point, can as shown in Figure 8 B, and MOS switch Q is straight-through to cause output electric current to be nearly equal to peak point current Ipk.Low voltage difference explained above
The principle of output current overshoot.
The present invention is that maximum turn-on time limitation or lowermost switch frequency are introduced in the constant current driver circuit for LED of opened loop control
Rate limiting circuit, can be effectively suppressed output current overshoot.Specific structure is respectively such as Fig. 4, shown in Fig. 5.In Fig. 4, sluggishness control is permanent
Flowing driving circuit includes inductive current detection circuit 11, voltage reference source circuit 12, retarding window control circuit 13 and power tube
Driving circuit 14.Maximum turn-on time limiting circuit 15 of the invention is connected to power tube drive circuit 14.It is fixed in Fig. 5
TOFF and constant peak electric current integrated circuit include inductance peak current control circuitry 21, turn-off time control circuit 22, PWM letter
Number generation circuit 23 and power tube drive circuit 14.Maximum turn-on time limiting circuit 15 of the invention is connected to power tube driving
Circuit 14.
Maximum turn-on time limiting circuit in Fig. 4, Fig. 5 can also be replaced with lowermost switch frequency limit circuit.
Referring to Fig. 9, overstriking solid line waveform figure is the output current wave figure introduced after maximum turn-on time limiting circuit.By
In introducing maximum turn-on time limiting circuit, in the close situation of input and output pressure difference, power tube MOS switch Q turn-on time one
Denier reaches maximum turn-on time and is then transferred to shutdown (peak point current not up to setting of traditional control circuit in inductive current immediately
Peak point current before power tube can be constantly on state), therefore limit output electric current overshoot.Figure 10, Tu11Fen
The embodiment of 2 kinds of maximum turn-on time limiting circuits is not given.
Maximum turn-on time limiting circuit in Figure 10 includes constant-current source I1, phase inverter IV, capacitor C1, switch S1, compares
Device COMP1.The input terminal of phase inverter INV is connected to the driving signal DRV of the grid of MOS switch Q, and output end is connected to this
The control terminal of switch S1, one end of switch S1 are connected to constant-current source I1, and other end ground connection, one end of capacitor C1 is connected to
One end of switch S1, other end ground connection, the first input end of comparator COMP1 are connected to one end of capacitor C1, and second
Input terminal is connected to reference voltage VREF, and the input terminal that output end is connected to power tube drive circuit 14 is opened with triggering the MOS
Close the shutdown of Q.
When driving end DRV is high level, switch S1 is disconnected, and constant-current source I1 charges to capacitor C1.When voltage exceeds on C1
When reference voltage VREF, comparator COMP1 overturning output high level, output signal TONMAX_MARK becomes high level.Output letter
Number TONMAX_MARK is that high level then shows that the turn-on time for driving DRV output drive signal in end to control MOS switch Q has reached
It is limited to maximum turn-on time, output signal TONMAX_MARK is connected to the input terminal of the power tube drive circuit 14 of Fig. 4 or Fig. 5
To trigger the shutdown of MOS switch Q.
In Figure 11, by counter 5D to clock signal clk timing.Driving end DRV is function in switching mode LED drive circuit
The driving signal of MOS switch Q grid in rate tube drive circuit 14.The clock signal input terminal of counter 5D receives a clock signal
The reset terminal of CLK, counter 5D receive the driving signal (low level reset) from driving end DRV.When driving signal DRV is height
Level then starts counter 5D timing, and when driving signal DRV is low level, then counter 5D is reset.If driving signal DRV
High level is continuously more than setting time, then the output signal TONMAX_MARK overturning of counter 5D, triggers power tube, i.e. Fig. 6
In MOS switch Q shutdown.
The embodiment of 2 kinds of lowermost switch frequency limit circuits is set forth in Figure 12, Figure 13.
Lowermost switch frequency limit circuit in Figure 12 includes: monostable flipflop 6D, constant-current source I1, capacitor C1, switch
S1, comparator COMP1.The input terminal of monostable flipflop 6D receives the driving signal from driving end DRV, output end connection
In the control terminal of switch S1, one end of switch S1 is connected to constant-current source I1, and one end of other end ground connection, capacitor C1 connects
It is connected to one end of switch S1, other end ground connection, the first input end of comparator COMP1 is connected to one end of capacitor C1,
Second input terminal is connected to reference voltage VREF, and output end is connected to an input terminal of the power tube drive circuit 14, with triggering
The power tube, the i.e. shutdown of MOS switch Q in Fig. 6.
Driving signal DRV is input to monostable flipflop 6D and generates pulse signal Y.When pulse signal Y is low level, switch
S1 is disconnected, and constant-current source I1 charges to capacitor C1, when voltage exceeds reference voltage VREF on C1, comparator COMP1 overturning output
High level, TSMAX_MARK signal become high level.TSMAX_MARK signal is that high level has then shown system operating frequency
Reach lowermost switch frequency limit, TSMAX_MARK signal is connected to the input terminal of the power tube drive circuit 14 of Fig. 4 or Fig. 5, touching
Hair opens new switch periods.
Lowermost switch frequency limit circuit in Figure 13 includes: monostable flipflop 6D and counter 5D.DRV is switching mode
The driving signal of the grid of power tube drive circuit in LED drive circuit.Driving signal DRV send monostable flipflop 6D to generate arteries and veins
Rush signal Y.Wherein clock signal clk connects the clock signal input terminal of counter 5D, and pulse signal Y connects the reset terminal of counter 5D
(high level reset).When pulse signal Y is that low level then starts counter 5D timing, when pulse signal Y is that high level then counts
Device 5D is reset.If pulse signal Y is continuously low level more than setting time, the output signal TSMAX_MARK of counter 5D
Overturning, output signal TSMAX_MARK are connected to the input terminal of the power tube drive circuit 14 of Fig. 4 or Fig. 5, and new open is opened in triggering
Close the period.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (7)
1. a kind of low voltage difference output current overshoot suppression circuit is applied to a constant current driver circuit for LED, the LED constant current driving
Circuit includes a power tube drive circuit, LED and inductance, it is characterised in that: and the power tube drive circuit has off state,
The first end of the LED is driven for receiving an input voltage, the second end of the LED by the inductance and the power tube
Circuit is electrically connected, wherein the second end of the LED is for providing an output voltage to the inductance；The low voltage difference output
Current over pulse suppression circuit includes a limiting circuit, and the limiting circuit is electrically connected the power tube drive circuit；The limit
Voltage difference of the circuit processed between the input voltage and output voltage is smaller and the current non-linear of the inductance is made to increase
When control that the power tube drive circuit is in an off state, to inhibit the output electric current mistake in the constant current driver circuit for LED
Punching.
2. low voltage difference output current overshoot suppression circuit according to claim 1, which is characterized in that the limiting circuit is
One maximum turn-on time limiting circuit.
3. low voltage difference output current overshoot suppression circuit according to claim 2, which is characterized in that the power tube driving
Circuit include an output end and an at least input terminal, it is described maximum turn-on time limiting circuit including a phase inverter, a constant-current source,
One capacitor, a switch and a comparator, the switch include a control terminal, a first end and a second end, the comparator packet
A first input end, one second input terminal and an output end are included, the input terminal of the phase inverter is electrically connected the power tube and drives
The output end of dynamic circuit, the output end of the phase inverter are electrically connected the control terminal of the switch, the first end electricity of the switch
Property the connection constant-current source, the second end ground connection of the switch, one end of the capacitor is electrically connected the first end of the switch,
The other end of the capacitor is grounded, and the first input end of the comparator is electrically connected one end of the capacitor, the comparator
The second input terminal receive a reference voltage, the output end of the comparator is electrically connected the power tube drive circuit at least
One input terminal is to trigger the shutdown of the power tube drive circuit.
4. low voltage difference output current overshoot suppression circuit according to claim 2, which is characterized in that the power tube driving
Circuit includes an output end and an at least input terminal, and the maximum turn-on time limiting circuit includes a counter, the counting
Device includes a clock signal input terminal, a reset terminal and an output end, and the clock signal input terminal of the counter is to receive
Clock signal, the reset terminal of the counter are electrically connected the output end of the power tube drive circuit to receive driving signal,
The output end of the counter is electrically connected an at least input terminal for the power tube drive circuit to trigger the power tube and drive
The shutdown of dynamic circuit.
5. low voltage difference output current overshoot suppression circuit according to claim 1, which is characterized in that the limiting circuit is
One lowermost switch frequency limit circuit.
6. low voltage difference output current overshoot suppression circuit according to claim 5, which is characterized in that the power tube driving
Circuit includes an output end and an at least input terminal, and the lowermost switch frequency limit circuit includes a monostable flipflop, one
Constant-current source, a capacitor, a switch and a comparator, the switch include a control terminal, a first end and a second end, the ratio
It include a first input end, one second input terminal and an output end compared with device, the input terminal of the monostable flipflop is electrically connected
The output end of the power tube drive circuit is to receive driving signal, described in the output end of the monostable flipflop is electrically connected
The control terminal of switch, the first end of the switch are electrically connected the constant-current source, the second end ground connection of the switch, the capacitor
One end be electrically connected the first end of the switch, the other end ground connection of the capacitor, the first input end electricity of the comparator
Property connect one end of the capacitor, the second input terminal of the comparator receives a reference voltage, the output end of the comparator
An at least input terminal for the power tube drive circuit is electrically connected to trigger the shutdown of the power tube drive circuit.
7. low voltage difference output current overshoot suppression circuit according to claim 5, which is characterized in that the power tube driving
Circuit includes an output end and an at least input terminal, and the lowermost switch frequency limit circuit includes a counter and a monostable
Trigger, the counter include a clock signal input terminal, a reset terminal and an output end, the monostable flipflop it is defeated
Enter end and is electrically connected the output end of the power tube drive circuit to receive driving signal, the output end of the monostable flipflop
It is electrically connected the reset terminal of the counter, the clock signal input terminal of the counter is to receive clock signal, the meter
The output end of number device is electrically connected an at least input terminal for the power tube drive circuit to trigger the power tube drive circuit
Shutdown.
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| CN201710074334.7A CN107071964B (en) | 2017-02-10 | 2017-02-10 | Low voltage difference output current overshoot suppression circuit |
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| CN201710074334.7A CN107071964B (en) | 2017-02-10 | 2017-02-10 | Low voltage difference output current overshoot suppression circuit |
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| CN107071964B true CN107071964B (en) | 2019-04-30 |
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| CN107690213A (en) * | 2017-10-17 | 2018-02-13 | 无锡恒芯微科技有限公司 | Non-isolated low pressure does not flash LED drive circuit |
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|---|---|---|---|---|
| CN104159355A (en) * | 2014-06-13 | 2014-11-19 | 矽力杰半导体技术(杭州)有限公司 | LED drive circuit, and control circuit and control method of LED drive circuit |
| CN105517244A (en) * | 2016-01-13 | 2016-04-20 | 上海新进芯微电子有限公司 | LED (light-emitting diode) driving circuit and method for controlling conduction/cut-off time of switching power supply |
| CN206640829U (en) * | 2017-02-10 | 2017-11-14 | 深圳欧创芯半导体有限公司 | Low voltage difference output current overshoot suppression circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5691712B2 (en) * | 2011-03-23 | 2015-04-01 | サンケン電気株式会社 | Constant current power supply |
| CN102307007B (en) * | 2011-09-13 | 2013-11-06 | 矽力杰半导体技术(杭州)有限公司 | PFC (power factor correction) control circuit based on master-slave interlaced critical conduction mode and control method thereof |
| CN205726571U (en) * | 2016-06-16 | 2016-11-23 | 深圳欧创芯半导体有限公司 | Wide input voltage high precision constant current driving means |
| CN106304484B (en) * | 2016-08-22 | 2018-11-13 | 上海晶丰明源半导体股份有限公司 | Controllable silicon light modulation LED drive power and its dimming controlling method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104159355A (en) * | 2014-06-13 | 2014-11-19 | 矽力杰半导体技术(杭州)有限公司 | LED drive circuit, and control circuit and control method of LED drive circuit |
| CN105517244A (en) * | 2016-01-13 | 2016-04-20 | 上海新进芯微电子有限公司 | LED (light-emitting diode) driving circuit and method for controlling conduction/cut-off time of switching power supply |
| CN206640829U (en) * | 2017-02-10 | 2017-11-14 | 深圳欧创芯半导体有限公司 | Low voltage difference output current overshoot suppression circuit |
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